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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [simulation/] [modelsim/] [spw_fifo_ulight.vo] - Rev 40
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// Copyright (C) 2017 Intel Corporation. All rights reserved.// Your use of Intel Corporation's design tools, logic functions// and other software and tools, and its AMPP partner logic// functions, and any output files from any of the foregoing// (including device programming or simulation files), and any// associated documentation or information are expressly subject// to the terms and conditions of the Intel Program License// Subscription Agreement, the Intel Quartus Prime License Agreement,// the Intel MegaCore Function License Agreement, or other// applicable license agreement, including, without limitation,// that your use is for the sole purpose of programming logic// devices manufactured by Intel and sold by Intel or its// authorized distributors. Please refer to the applicable// agreement for further details.// VENDOR "Altera"// PROGRAM "Quartus Prime"// VERSION "Version 17.0.2 Build 602 07/19/2017 SJ Lite Edition"// DATE "11/10/2017 11:13:11"//// Device: Altera 5CSEMA4U23C6 Package UFBGA672////// This Verilog file should be used for ModelSim-Altera (Verilog) only//`timescale 1 ps/ 1 psmodule SPW_ULIGHT_FIFO (\sout_a(n) ,\dout_a(n) ,\din_a(n) ,\sin_a(n) ,FPGA_CLK1_50,KEY,din_a,sin_a,dout_a,sout_a,LED);output \sout_a(n) ;output \dout_a(n) ;input \din_a(n) ;input \sin_a(n) ;input FPGA_CLK1_50;input [1:0] KEY;input din_a;input sin_a;output dout_a;output sout_a;output [7:0] LED;// Design Ports Information// sout_a => Location: PIN_AF20, I/O Standard: LVDS, Current Strength: Default// LED[5] => Location: PIN_AE26, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA// LED[7] => Location: PIN_AA23, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA// dout_a => Location: PIN_AG28, I/O Standard: LVDS, Current Strength: Default// LED[0] => Location: PIN_W15, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA// LED[1] => Location: PIN_AA24, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA// LED[2] => Location: PIN_V16, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA// LED[3] => Location: PIN_V15, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA// LED[4] => Location: PIN_AF26, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA// KEY[0] => Location: PIN_AH17, I/O Standard: 3.3-V LVTTL, Current Strength: Default// LED[6] => Location: PIN_Y16, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA// FPGA_CLK1_50 => Location: PIN_Y13, I/O Standard: 3.3-V LVTTL, Current Strength: Default// KEY[1] => Location: PIN_AH16, I/O Standard: 3.3-V LVTTL, Current Strength: Default// din_a => Location: PIN_Y15, I/O Standard: LVDS, Current Strength: Default// sin_a => Location: PIN_AE20, I/O Standard: LVDS, Current Strength: Default// sout_a(n) => Location: PIN_AG20, I/O Standard: LVDS, Current Strength: Default// dout_a(n) => Location: PIN_AH27, I/O Standard: LVDS, Current Strength: Default// din_a(n) => Location: PIN_AA15, I/O Standard: LVDS, Current Strength: Default// sin_a(n) => Location: PIN_AD20, I/O Standard: LVDS, Current Strength: Defaultwire gnd;wire vcc;wire unknown;assign gnd = 1'b0;assign vcc = 1'b1;assign unknown = 1'bx;tri1 devclrn;tri1 devpor;tri1 devoe;wire \u0|hps_0|fpga_interfaces|fpga2hps~arready ;wire \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_10 ;wire \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_11 ;wire \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_12 ;wire \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_13 ;wire \u0|hps_0|fpga_interfaces|tpiu~trace_data ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA1 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA2 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA3 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA4 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA5 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA6 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA7 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA8 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA9 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA10 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA11 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA12 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA13 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA14 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA15 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA16 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA17 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA18 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA19 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA20 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA21 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA22 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA23 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA24 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA25 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA26 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA27 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA28 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA29 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA30 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA31 ;wire \u0|hps_0|fpga_interfaces|boot_from_fpga~fake_dout ;wire \u0|hps_0|fpga_interfaces|debug_apb~O_P_ADDR_31 ;wire \u0|hps_0|fpga_interfaces|clocks_resets~h2f_cold_rst_n ;wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|clk0bad ;wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|blockselect ;wire \KEY[0]~input_o ;wire \~QUARTUS_CREATED_GND~I_combout ;wire \FPGA_CLK1_50~input_o ;wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|refclk_select_extswitchbuf_wire ;wire \FPGA_CLK1_50~inputCLKENA0_outclk ;wire \KEY[1]~input_o ;wire \db_system_spwulight_b|Add0~61_sumout ;wire \db_system_spwulight_b|counter~15_combout ;wire \db_system_spwulight_b|Add0~62 ;wire \db_system_spwulight_b|Add0~57_sumout ;wire \db_system_spwulight_b|counter~14_combout ;wire \db_system_spwulight_b|Add0~58 ;wire \db_system_spwulight_b|Add0~53_sumout ;wire \db_system_spwulight_b|counter~13_combout ;wire \db_system_spwulight_b|Add0~54 ;wire \db_system_spwulight_b|Add0~49_sumout ;wire \db_system_spwulight_b|counter~12_combout ;wire \db_system_spwulight_b|Add0~50 ;wire \db_system_spwulight_b|Add0~38 ;wire \db_system_spwulight_b|Add0~41_sumout ;wire \db_system_spwulight_b|counter~10_combout ;wire \db_system_spwulight_b|Add0~42 ;wire \db_system_spwulight_b|Add0~45_sumout ;wire \db_system_spwulight_b|counter~11_combout ;wire \db_system_spwulight_b|Add0~46 ;wire \db_system_spwulight_b|Add0~29_sumout ;wire \db_system_spwulight_b|counter~7_combout ;wire \db_system_spwulight_b|Add0~30 ;wire \db_system_spwulight_b|Add0~33_sumout ;wire \db_system_spwulight_b|counter~8_combout ;wire \db_system_spwulight_b|Add0~34 ;wire \db_system_spwulight_b|Add0~9_sumout ;wire \db_system_spwulight_b|counter~2_combout ;wire \db_system_spwulight_b|Add0~10 ;wire \db_system_spwulight_b|Add0~13_sumout ;wire \db_system_spwulight_b|counter~3_combout ;wire \db_system_spwulight_b|Add0~14 ;wire \db_system_spwulight_b|Add0~17_sumout ;wire \db_system_spwulight_b|counter~4_combout ;wire \db_system_spwulight_b|Add0~18 ;wire \db_system_spwulight_b|Add0~21_sumout ;wire \db_system_spwulight_b|counter~5_combout ;wire \db_system_spwulight_b|Add0~22 ;wire \db_system_spwulight_b|Add0~25_sumout ;wire \db_system_spwulight_b|counter~6_combout ;wire \db_system_spwulight_b|Add0~26 ;wire \db_system_spwulight_b|Add0~1_sumout ;wire \db_system_spwulight_b|counter~0_combout ;wire \db_system_spwulight_b|LessThan0~0_combout ;wire \db_system_spwulight_b|LessThan0~2_combout ;wire \db_system_spwulight_b|Add0~37_sumout ;wire \db_system_spwulight_b|counter~9_combout ;wire \db_system_spwulight_b|LessThan0~1_combout ;wire \db_system_spwulight_b|Add0~2 ;wire \db_system_spwulight_b|Add0~5_sumout ;wire \db_system_spwulight_b|counter~1_combout ;wire \db_system_spwulight_b|aux_pb~0_combout ;wire \db_system_spwulight_b|aux_pb~q ;wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|refclk_select_clkout_wire ;wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|pll_reconfig_up_wire ;wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|pll_reconfig_shiftenm_wire ;wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shift ;wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|cntnen ;wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|tclk ;wire \u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ;wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ;wire \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~2_combout ;wire \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout ;wire \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ;wire \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ;wire \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][69]~q ;wire \u0|mm_interconnect_0|cmd_mux|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux|packet_in_progress~q ;wire \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4_combout ;wire \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~6 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~29_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~8_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~30 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~33_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~9_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~34 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~37_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~10_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~38 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~41_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~11_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|LessThan16~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~42 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~13_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~4_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~14 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~17_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~5_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~18 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~21_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~6_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~22 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~25_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~7_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~9_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~3_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~10 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~1_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~1_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~2 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~5_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~2_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ;wire \A_SPW_TOP|tx_data|counter_writer[0]~0_combout ;wire \A_SPW_TOP|tx_data|Add1~1_combout ;wire \A_SPW_TOP|tx_data|Add1~2_combout ;wire \A_SPW_TOP|tx_data|Add1~3_combout ;wire \A_SPW_TOP|tx_data|counter_reader[0]~0_combout ;wire \sin_a~input_o ;wire \din_a~input_o ;wire \A_SPW_TOP|SPW|RX|always3~0_combout ;wire \A_SPW_TOP|SPW|RX|counter_neg[0]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|always2~0_combout ;wire \A_SPW_TOP|SPW|RX|ready_data_p~combout ;wire \A_SPW_TOP|SPW|RX|ready_data~combout ;wire \A_SPW_TOP|SPW|RX|bit_d_1~feeder_combout ;wire \A_SPW_TOP|SPW|RX|bit_d_1~q ;wire \A_SPW_TOP|SPW|RX|bit_d_3~feeder_combout ;wire \A_SPW_TOP|SPW|RX|bit_d_3~q ;wire \A_SPW_TOP|SPW|RX|bit_d_5~q ;wire \A_SPW_TOP|SPW|RX|bit_d_7~q ;wire \A_SPW_TOP|SPW|RX|bit_d_9~feeder_combout ;wire \A_SPW_TOP|SPW|RX|bit_d_9~q ;wire \A_SPW_TOP|SPW|RX|parity_rec_d~feeder_combout ;wire \A_SPW_TOP|SPW|RX|parity_rec_d~q ;wire \A_SPW_TOP|SPW|RX|bit_d_0~q ;wire \A_SPW_TOP|SPW|RX|bit_d_2~q ;wire \A_SPW_TOP|SPW|RX|bit_d_4~q ;wire \A_SPW_TOP|SPW|RX|bit_d_6~feeder_combout ;wire \A_SPW_TOP|SPW|RX|bit_d_6~q ;wire \A_SPW_TOP|SPW|RX|bit_d_8~feeder_combout ;wire \A_SPW_TOP|SPW|RX|bit_d_8~q ;wire \A_SPW_TOP|SPW|RX|dta_timec[8]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|always15~0_combout ;wire \A_SPW_TOP|SPW|RX|control_bit_found~q ;wire \A_SPW_TOP|SPW|RX|Selector0~1_combout ;wire \A_SPW_TOP|SPW|RX|Selector0~3_combout ;wire \A_SPW_TOP|SPW|RX|is_control~q ;wire \A_SPW_TOP|SPW|RX|ready_data_p_r~0_combout ;wire \A_SPW_TOP|SPW|RX|ready_data_p_r~q ;wire \A_SPW_TOP|SPW|RX|last_is_control~0_combout ;wire \A_SPW_TOP|SPW|RX|next_state_data_process.01~0_combout ;wire \A_SPW_TOP|SPW|RX|state_data_process.01~feeder_combout ;wire \A_SPW_TOP|SPW|RX|state_data_process.01~q ;wire \A_SPW_TOP|SPW|RX|last_is_control~q ;wire \A_SPW_TOP|SPW|RX|rx_error_c~0_combout ;wire \A_SPW_TOP|SPW|RX|bit_c_1~q ;wire \A_SPW_TOP|SPW|RX|control_r[1]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|control~1_combout ;wire \A_SPW_TOP|SPW|RX|bit_c_0~q ;wire \A_SPW_TOP|SPW|RX|control~2_combout ;wire \A_SPW_TOP|SPW|RX|rx_error_d~0_combout ;wire \A_SPW_TOP|SPW|RX|dta_timec[3]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|bit_c_2~q ;wire \A_SPW_TOP|SPW|RX|control~0_combout ;wire \A_SPW_TOP|SPW|RX|control[2]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|data~0_combout ;wire \A_SPW_TOP|SPW|RX|data~5_combout ;wire \A_SPW_TOP|SPW|RX|dta_timec[6]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|dta_timec_p[6]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|data~2_combout ;wire \A_SPW_TOP|SPW|RX|dta_timec[2]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|data~6_combout ;wire \A_SPW_TOP|SPW|RX|dta_timec[7]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|data~1_combout ;wire \A_SPW_TOP|SPW|RX|dta_timec[4]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|data~4_combout ;wire \A_SPW_TOP|SPW|RX|dta_timec[5]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|dta_timec_p[5]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|data~3_combout ;wire \A_SPW_TOP|SPW|RX|always16~0_combout ;wire \A_SPW_TOP|SPW|RX|dta_timec[0]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|dta_timec_p[0]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|data~8_combout ;wire \A_SPW_TOP|SPW|RX|dta_timec[1]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|dta_timec_p[1]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|data~7_combout ;wire \A_SPW_TOP|SPW|RX|always16~1_combout ;wire \A_SPW_TOP|SPW|RX|rx_error_d~1_combout ;wire \A_SPW_TOP|SPW|RX|rx_error_d~q ;wire \A_SPW_TOP|SPW|RX|bit_c_3~q ;wire \A_SPW_TOP|SPW|RX|parity_rec_c~q ;wire \A_SPW_TOP|SPW|RX|always16~2_combout ;wire \A_SPW_TOP|SPW|RX|rx_error_c~1_combout ;wire \A_SPW_TOP|SPW|RX|rx_error_c~2_combout ;wire \A_SPW_TOP|SPW|RX|rx_error_c~q ;wire \A_SPW_TOP|SPW|RX|last_is_timec~0_combout ;wire \A_SPW_TOP|SPW|RX|last_is_timec~q ;wire \A_SPW_TOP|SPW|RX|rx_got_null~0_combout ;wire \A_SPW_TOP|SPW|RX|rx_got_null~q ;wire \u0|mm_interconnect_0|router|Equal20~0_combout ;wire \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout ;wire \u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0_outclk ;wire \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][5]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~4_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][6]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][9]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ;wire \A_SPW_TOP|SPW|FSM|enable_tx~0_combout ;wire \A_SPW_TOP|SPW|FSM|enable_tx~q ;wire \A_SPW_TOP|tx_data|Add2~0_combout ;wire \A_SPW_TOP|tx_data|Add2~1_combout ;wire \A_SPW_TOP|tx_data|Add3~2 ;wire \A_SPW_TOP|tx_data|Add3~3 ;wire \A_SPW_TOP|tx_data|Add3~6 ;wire \A_SPW_TOP|tx_data|Add3~7 ;wire \A_SPW_TOP|tx_data|Add3~9_sumout ;wire \A_SPW_TOP|tx_data|Add3~1_sumout ;wire \A_SPW_TOP|tx_data|Add3~10 ;wire \A_SPW_TOP|tx_data|Add3~11 ;wire \A_SPW_TOP|tx_data|Add3~13_sumout ;wire \A_SPW_TOP|tx_data|Add1~4_combout ;wire \A_SPW_TOP|tx_data|Add2~4_combout ;wire \A_SPW_TOP|tx_data|Add3~14 ;wire \A_SPW_TOP|tx_data|Add3~15 ;wire \A_SPW_TOP|tx_data|Add3~18 ;wire \A_SPW_TOP|tx_data|Add3~19 ;wire \A_SPW_TOP|tx_data|Add3~21_sumout ;wire \A_SPW_TOP|tx_data|LessThan0~0_combout ;wire \A_SPW_TOP|tx_data|f_empty~q ;wire \A_SPW_TOP|tx_data|state_data_read~10_combout ;wire \A_SPW_TOP|tx_data|state_data_read.01~q ;wire \A_SPW_TOP|tx_data|state_data_read.00~0_combout ;wire \A_SPW_TOP|tx_data|state_data_read~11_combout ;wire \A_SPW_TOP|tx_data|state_data_read.00~feeder_combout ;wire \A_SPW_TOP|tx_data|state_data_read.00~q ;wire \A_SPW_TOP|tx_data|write_tx~q ;wire \A_SPW_TOP|SPW|TX|LessThan3~0_combout ;wire \m_x|control_bit_found~q ;wire \m_x|counter_neg[0]~feeder_combout ;wire \m_x|Selector2~0_combout ;wire \m_x|Selector2~1_combout ;wire \m_x|WideOr7~0_combout ;wire \m_x|Selector3~0_combout ;wire \m_x|Selector3~1_combout ;wire \m_x|Selector1~0_combout ;wire \m_x|Selector1~1_combout ;wire \m_x|Selector5~0_combout ;wire \m_x|Selector0~1_combout ;wire \m_x|Selector5~1_combout ;wire \m_x|Selector0~0_combout ;wire \m_x|Selector4~0_combout ;wire \m_x|Selector0~2_combout ;wire \m_x|Selector0~3_combout ;wire \m_x|is_control~q ;wire \m_x|always1~0_combout ;wire \m_x|always2~0_combout ;wire \m_x|ready_control_p_r~0_combout ;wire \m_x|ready_control_p_r~q ;wire \m_x|bit_c_1~feeder_combout ;wire \m_x|bit_c_1~q ;wire \m_x|control_p_r[1]~feeder_combout ;wire \m_x|control~1_combout ;wire \m_x|ready_data~combout ;wire \m_x|ready_data_p~combout ;wire \m_x|ready_data_p_r~0_combout ;wire \m_x|ready_data_p_r~q ;wire \m_x|next_state_data_process.01~0_combout ;wire \m_x|state_data_process.01~q ;wire \m_x|control_l_r~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~13_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~1_combout ;wire \m_x|bit_c_0~q ;wire \m_x|bit_c_2~q ;wire \m_x|control_r[2]~feeder_combout ;wire \m_x|control~2_combout ;wire \m_x|control_l_r~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][12]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][12]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~32_combout ;wire \m_x|bit_c_3~q ;wire \m_x|control_r[3]~feeder_combout ;wire \m_x|control~3_combout ;wire \m_x|control_l_r~3_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][13]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][13]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~33_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|router_001|Equal2~2_combout ;wire \u0|mm_interconnect_0|router_001|Equal2~1_combout ;wire \u0|mm_interconnect_0|router_001|Equal1~3_combout ;wire \u0|mm_interconnect_0|router_001|src_data[102]~0_combout ;wire \u0|mm_interconnect_0|router_001|src_data[100]~1_combout ;wire \u0|mm_interconnect_0|router_001|src_data[101]~2_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0_combout ;wire \u0|mm_interconnect_0|router_001|src_data[103]~3_combout ;wire \u0|mm_interconnect_0|router_001|src_data[104]~4_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|router_001|Equal9~0_combout ;wire \u0|mm_interconnect_0|router_001|Equal9~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;wire \u0|mm_interconnect_0|router_001|Equal1~4_combout ;wire \u0|mm_interconnect_0|router_001|Equal15~0_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src9_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~q ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][69]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][69]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][68]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][68]~q ;wire \u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout ;wire \u0|mm_interconnect_0|rsp_demux_009|WideOr0~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|m0_write~combout ;wire \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_011|src_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|router_001|Equal17~0_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src11_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~5_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~2_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|m0_read~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|m0_write~combout ;wire \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|router_001|Equal19~0_combout ;wire \u0|mm_interconnect_0|router_001|Equal19~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[13]~feeder_combout ;wire \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|router_001|Equal12~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4]~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5]~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~21_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~feeder_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|router_001|Equal20~0_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src14_valid~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|cmd_demux_001|src14_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write~combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][68]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][68]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][69]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69]~q ;wire \u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout ;wire \u0|mm_interconnect_0|rsp_demux_014|WideOr0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~2_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|arb|grant[1]~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|saved_grant[1]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~21_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~201_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~21_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~21_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~200_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~11_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~11_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|router_001|Equal14~0_combout ;wire \u0|mm_interconnect_0|router_001|Equal14~1_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src8_valid~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|router|Equal14~1_combout ;wire \u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_008|update_grant~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][68]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][68]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][69]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][69]~q ;wire \u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|router_001|Equal7~0_combout ;wire \u0|mm_interconnect_0|router_001|Equal8~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~feeder_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ;wire \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_019|update_grant~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~11_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~198_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~199_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~11_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~11_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4_combout ;wire \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][69]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][69]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][68]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][68]~q ;wire \u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~11_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~196_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~197_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;wire \u0|mm_interconnect_0|cmd_mux_018|src_valid~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~21_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21_combout ;wire \u0|mm_interconnect_0|rsp_demux_015|WideOr0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~202_combout ;wire \u0|mm_interconnect_0|router_001|Equal18~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_012|update_grant~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~11_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|router_001|Equal1~5_combout ;wire \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ;wire \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_001|update_grant~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~3_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|cmd_mux|src_valid~0_combout ;wire \u0|mm_interconnect_0|router|src_data[103]~0_combout ;wire \u0|mm_interconnect_0|router|Equal6~7_combout ;wire \u0|mm_interconnect_0|cmd_demux|src0_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_demux|src0_valid~1_combout ;wire \u0|mm_interconnect_0|cmd_demux|src0_valid~2_combout ;wire \u0|mm_interconnect_0|cmd_demux|src0_valid~3_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~21_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_read~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_write~combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~4_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77]~feeder_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~11_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|router_001|Equal3~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ;wire \u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_002|update_grant~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~11_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~56_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~203_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_003|update_grant~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~11_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|router_001|Equal11~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ;wire \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_006|update_grant~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~11_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~57_combout ;wire \u0|mm_interconnect_0|router_001|Equal7~1_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src4_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src4_valid~1_combout ;wire \u0|mm_interconnect_0|router|Equal7~2_combout ;wire \u0|mm_interconnect_0|router|Equal7~3_combout ;wire \u0|mm_interconnect_0|cmd_demux|src4_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_demux|src4_valid~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_004|src_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_004|arb|grant[1]~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_004|src_valid~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~feeder_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~2_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][77]~feeder_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg[0]~feeder_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write~combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_004|update_grant~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_004|arb|grant[0]~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][68]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][68]~feeder_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][68]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][69]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][69]~feeder_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][69]~q ;wire \u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~21_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~11_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~204_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~205_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~190_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~10_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~188_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~10_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115]~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~10_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~189_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~192_combout ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~10_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~54_combout ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~10_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~193_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~10_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~10_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~10_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~55_combout ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~10_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~194_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~195_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~10_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~10_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~10_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~186_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~187_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~191_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~180_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~9_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~176_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~9_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~9_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][114]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~177_combout ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~9_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~53_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~9_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~184_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~9_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~9_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~9_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~52_combout ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~9_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][114]~feeder_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~183_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~185_combout ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~9_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~9_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~9_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~178_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~179_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~181_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~182_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_021|update_grant~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~8_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113]~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~8_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~168_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~8_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~169_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~8_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][113]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~8_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~8_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~50_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~173_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~8_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~8_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~51_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~8_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~174_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~175_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~170_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~172_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~8_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~166_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~8_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~8_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~167_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~171_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~162_combout ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~7_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~158_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~7_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~7_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~159_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~7_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][112]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~7_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~7_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~156_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~157_combout ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~7_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~49_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~7_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~164_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~7_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~7_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~7_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~48_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~163_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~7_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~165_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~160_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~161_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_013|update_grant~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~6_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~146_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~6_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][111]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~6_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~147_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~150_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~151_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~6_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~6_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~46_combout ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~6_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~feeder_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~153_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~6_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~47_combout ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~6_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111]~feeder_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~154_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~6_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~155_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~152_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~6_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~6_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][111]~feeder_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~148_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~6_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~149_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~3_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|router_001|Equal13~0_combout ;wire \u0|mm_interconnect_0|router_001|Equal13~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~2_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~3_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[4]~5_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan14~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~4_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~5_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan12~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~6_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~21_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~77_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan10~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector29~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~78 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~73_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~22 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~17_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~74 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~69_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~18 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~13_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector27~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~70 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~65_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~14 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~9_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector26~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~10 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~5_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~66 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~9_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector25~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~10 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~6 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~17_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector23~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~18 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~13_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector22~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~14 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~25_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector21~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~26 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~21_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector20~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~22 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~41_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector19~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~42 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~37_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector18~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~38 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~33_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector17~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~34 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~49_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector16~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~50 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~29_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector15~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~30 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~46 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~61_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector13~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~62 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~1_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector12~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~2 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~58 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~53_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector10~0_combout ;wire \u0|mm_interconnect_0|router|Equal6~5_combout ;wire \u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|local_write~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~feeder_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~5_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~136_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~137_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~140_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~5_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110]~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~5_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~138_combout ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~5_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~139_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~5_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~5_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~44_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~143_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~5_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~5_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~5_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~45_combout ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~5_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~144_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~145_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~141_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~142_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_011|update_grant~0_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src11_valid~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_011|arb|grant[1]~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|m0_read~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|rsp_demux_011|WideOr0~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129]~feeder_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~131_combout ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~4_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~4_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~128_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~4_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~129_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~132_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~4_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][109]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~4_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~126_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~127_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~130_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~4_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~4_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~4_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~43_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~134_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~4_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~4_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~42_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~4_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~133_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~135_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_009|update_grant~0_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src9_valid~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_009|arb|grant[1]~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~120_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~3_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][108]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~116_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~117_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~122_combout ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~3_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~3_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~118_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~3_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~119_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~3_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~40_combout ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~3_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~123_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~3_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~41_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~3_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~124_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~3_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~125_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~121_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ;wire \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_005|update_grant~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~2_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~39_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][107]~feeder_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~114_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~2_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][107]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~2_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~38_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~113_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~2_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~115_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~112_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107]~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~108_combout ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~109_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~111_combout ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~106_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~107_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~110_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_016|update_grant~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~96_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][106]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~97_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~36_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~103_combout ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~37_combout ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~104_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~105_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106]~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~98_combout ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~99_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~100_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~101_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~102_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~90_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~88_combout ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~89_combout ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~35_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~94_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~34_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~93_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][105]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~95_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~91_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][105]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~86_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~87_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~92_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~14_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~16_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~15_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~2_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~2_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~3_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~14 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~9_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~17_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~13_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~18_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][11]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][11]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~31_combout ;wire \u0|mm_interconnect_0|cmd_mux_004|src_payload~0_combout ;wire \u0|data_read_en_rx|data_out~feeder_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~14 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~10 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~5_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~13_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~9_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~6 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~1_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|data_read_en_rx|always0~0_combout ;wire \u0|data_read_en_rx|data_out~q ;wire \A_SPW_TOP|rx_data|Add9~1_sumout ;wire \A_SPW_TOP|rx_data|counter_writer[0]~0_combout ;wire \A_SPW_TOP|SPW|RX|rx_buffer_write~1_combout ;wire \A_SPW_TOP|SPW|RX|rx_buffer_write~0_combout ;wire \A_SPW_TOP|SPW|RX|rx_buffer_write~q ;wire \A_SPW_TOP|rx_data|counter_reader[0]~0_combout ;wire \A_SPW_TOP|rx_data|state_data_read~9_combout ;wire \A_SPW_TOP|rx_data|state_data_read.10~feeder_combout ;wire \A_SPW_TOP|rx_data|state_data_read.10~q ;wire \A_SPW_TOP|rx_data|state_data_read~8_combout ;wire \A_SPW_TOP|rx_data|state_data_read.01~feeder_combout ;wire \A_SPW_TOP|rx_data|state_data_read.01~q ;wire \A_SPW_TOP|rx_data|always5~0_combout ;wire \A_SPW_TOP|rx_data|Add8~1_sumout ;wire \A_SPW_TOP|rx_data|Add7~0_combout ;wire \A_SPW_TOP|rx_data|Add6~0_combout ;wire \A_SPW_TOP|rx_data|Add8~2 ;wire \A_SPW_TOP|rx_data|Add8~3 ;wire \A_SPW_TOP|rx_data|Add8~5_sumout ;wire \A_SPW_TOP|rx_data|Add7~1_combout ;wire \A_SPW_TOP|rx_data|Add7~2_combout ;wire \A_SPW_TOP|rx_data|Add7~3_combout ;wire \A_SPW_TOP|rx_data|Add7~4_combout ;wire \A_SPW_TOP|rx_data|Add6~1_combout ;wire \A_SPW_TOP|rx_data|Add6~3_combout ;wire \A_SPW_TOP|rx_data|Add6~4_combout ;wire \A_SPW_TOP|rx_data|Add8~6 ;wire \A_SPW_TOP|rx_data|Add8~7 ;wire \A_SPW_TOP|rx_data|Add8~10 ;wire \A_SPW_TOP|rx_data|Add8~11 ;wire \A_SPW_TOP|rx_data|Add8~14 ;wire \A_SPW_TOP|rx_data|Add8~15 ;wire \A_SPW_TOP|rx_data|Add8~18 ;wire \A_SPW_TOP|rx_data|Add8~19 ;wire \A_SPW_TOP|rx_data|Add8~21_sumout ;wire \A_SPW_TOP|rx_data|Add8~17_sumout ;wire \A_SPW_TOP|rx_data|Add8~9_sumout ;wire \A_SPW_TOP|rx_data|Equal9~0_combout ;wire \A_SPW_TOP|rx_data|f_full~q ;wire \A_SPW_TOP|rx_data|state_data_write~8_combout ;wire \A_SPW_TOP|rx_data|state_data_write.01~q ;wire \A_SPW_TOP|rx_data|state_data_write~7_combout ;wire \A_SPW_TOP|rx_data|state_data_write.00~q ;wire \A_SPW_TOP|rx_data|state_data_write~9_combout ;wire \A_SPW_TOP|rx_data|state_data_write.10~q ;wire \A_SPW_TOP|rx_data|Add6~2_combout ;wire \A_SPW_TOP|rx_data|Add8~13_sumout ;wire \A_SPW_TOP|rx_data|Equal10~0_combout ;wire \A_SPW_TOP|rx_data|f_empty~q ;wire \A_SPW_TOP|rx_data|state_data_read~7_combout ;wire \A_SPW_TOP|rx_data|state_data_read.00~feeder_combout ;wire \A_SPW_TOP|rx_data|state_data_read.00~q ;wire \A_SPW_TOP|rx_data|Add9~2 ;wire \A_SPW_TOP|rx_data|Add9~13_sumout ;wire \A_SPW_TOP|rx_data|Add9~14 ;wire \A_SPW_TOP|rx_data|Add9~9_sumout ;wire \A_SPW_TOP|rx_data|always3~0_combout ;wire \A_SPW_TOP|rx_data|state_open_slot~8_combout ;wire \A_SPW_TOP|rx_data|state_open_slot.00~q ;wire \A_SPW_TOP|rx_data|Selector8~1_combout ;wire \A_SPW_TOP|rx_data|Selector1~0_combout ;wire \A_SPW_TOP|rx_data|Add0~30 ;wire \A_SPW_TOP|rx_data|Add0~25_sumout ;wire \A_SPW_TOP|rx_data|Selector14~0_combout ;wire \A_SPW_TOP|rx_data|Add0~26 ;wire \A_SPW_TOP|rx_data|Add0~21_sumout ;wire \A_SPW_TOP|rx_data|Selector13~0_combout ;wire \A_SPW_TOP|rx_data|Add0~22 ;wire \A_SPW_TOP|rx_data|Add0~17_sumout ;wire \A_SPW_TOP|rx_data|Selector12~0_combout ;wire \A_SPW_TOP|rx_data|Add0~18 ;wire \A_SPW_TOP|rx_data|Add0~13_sumout ;wire \A_SPW_TOP|rx_data|Selector11~0_combout ;wire \A_SPW_TOP|rx_data|Add0~14 ;wire \A_SPW_TOP|rx_data|Add0~9_sumout ;wire \A_SPW_TOP|rx_data|Selector10~0_combout ;wire \A_SPW_TOP|rx_data|Add0~10 ;wire \A_SPW_TOP|rx_data|Add0~5_sumout ;wire \A_SPW_TOP|rx_data|Selector9~0_combout ;wire \A_SPW_TOP|rx_data|Add0~6 ;wire \A_SPW_TOP|rx_data|Add0~1_sumout ;wire \A_SPW_TOP|rx_data|Selector8~2_combout ;wire \A_SPW_TOP|rx_data|Equal0~0_combout ;wire \A_SPW_TOP|rx_data|Add0~41_sumout ;wire \A_SPW_TOP|rx_data|Selector18~0_combout ;wire \A_SPW_TOP|rx_data|Selector18~1_combout ;wire \A_SPW_TOP|rx_data|Add0~42 ;wire \A_SPW_TOP|rx_data|Add0~37_sumout ;wire \A_SPW_TOP|rx_data|Selector17~0_combout ;wire \A_SPW_TOP|rx_data|Add0~38 ;wire \A_SPW_TOP|rx_data|Add0~33_sumout ;wire \A_SPW_TOP|rx_data|Selector16~0_combout ;wire \A_SPW_TOP|rx_data|Add0~34 ;wire \A_SPW_TOP|rx_data|Add0~29_sumout ;wire \A_SPW_TOP|rx_data|Selector15~0_combout ;wire \A_SPW_TOP|rx_data|Equal0~1_combout ;wire \A_SPW_TOP|rx_data|state_open_slot~9_combout ;wire \A_SPW_TOP|rx_data|state_open_slot.10~q ;wire \A_SPW_TOP|rx_data|state_open_slot~7_combout ;wire \A_SPW_TOP|rx_data|state_open_slot.01~q ;wire \A_SPW_TOP|rx_data|Selector8~0_combout ;wire \A_SPW_TOP|rx_data|open_slot_fct~q ;wire \A_SPW_TOP|SPW|TX|fct_flag~2_combout ;wire \A_SPW_TOP|SPW|TX|state_fct_send.001~q ;wire \A_SPW_TOP|SPW|TX|fct_flag~0_combout ;wire \A_SPW_TOP|SPW|RX|rx_got_fct_fsm~feeder_combout ;wire \A_SPW_TOP|SPW|RX|control_l_r~0_combout ;wire \A_SPW_TOP|SPW|RX|control_l_r~2_combout ;wire \A_SPW_TOP|SPW|RX|control_l_r~1_combout ;wire \A_SPW_TOP|SPW|RX|always8~0_combout ;wire \A_SPW_TOP|SPW|RX|always10~0_combout ;wire \A_SPW_TOP|SPW|RX|rx_got_fct_fsm~q ;wire \A_SPW_TOP|SPW|RX|rx_got_time_code~0_combout ;wire \A_SPW_TOP|SPW|RX|rx_got_time_code~q ;wire \A_SPW_TOP|SPW|FSM|state_fsm~21_combout ;wire \A_SPW_TOP|SPW|FSM|always0~1_combout ;wire \A_SPW_TOP|SPW|FSM|always0~0_combout ;wire \A_SPW_TOP|SPW|FSM|state_fsm~18_combout ;wire \A_SPW_TOP|SPW|FSM|state_fsm.connecting~q ;wire \A_SPW_TOP|SPW|FSM|send_fct_tx~0_combout ;wire \A_SPW_TOP|SPW|FSM|send_fct_tx~q ;wire \u0|mm_interconnect_0|cmd_mux_015|src_payload~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_write~combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|timecode_tx_enable|always0~0_combout ;wire \u0|timecode_tx_enable|data_out~q ;wire \A_SPW_TOP|SPW|TX|Equal0~5_combout ;wire \A_SPW_TOP|SPW|TX|Equal0~6_combout ;wire \A_SPW_TOP|SPW|TX|Selector42~1_combout ;wire \A_SPW_TOP|SPW|TX|tx_tcode_in~0_combout ;wire \A_SPW_TOP|tx_data|rd_ptr~5_combout ;wire \A_SPW_TOP|tx_data|rd_ptr~1_combout ;wire \A_SPW_TOP|tx_data|rd_ptr~3_combout ;wire \A_SPW_TOP|tx_data|rd_ptr~2_combout ;wire \A_SPW_TOP|tx_data|Add4~0_combout ;wire \A_SPW_TOP|tx_data|rd_ptr~4_combout ;wire \A_SPW_TOP|tx_data|rd_ptr~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~8_combout ;wire \u0|write_data_fifo_tx|always0~0_combout ;wire \A_SPW_TOP|tx_data|wr_ptr[0]~0_combout ;wire \A_SPW_TOP|tx_data|Add0~4_combout ;wire \A_SPW_TOP|tx_data|Add0~1_combout ;wire \A_SPW_TOP|tx_data|Add0~2_combout ;wire \A_SPW_TOP|tx_data|Add0~3_combout ;wire \A_SPW_TOP|tx_data|wr_ptr[4]~feeder_combout ;wire \A_SPW_TOP|tx_data|Add0~0_combout ;wire \A_SPW_TOP|tx_data|wr_ptr[5]~feeder_combout ;wire \A_SPW_TOP|tx_data|Decoder0~13_combout ;wire \A_SPW_TOP|tx_data|Selector401~0_combout ;wire \A_SPW_TOP|tx_data|Decoder0~20_combout ;wire \A_SPW_TOP|tx_data|Selector437~0_combout ;wire \A_SPW_TOP|tx_data|Selector437~1_combout ;wire \A_SPW_TOP|tx_data|mem[48][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~18_combout ;wire \A_SPW_TOP|tx_data|Selector185~0_combout ;wire \A_SPW_TOP|tx_data|Selector185~1_combout ;wire \A_SPW_TOP|tx_data|mem[20][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~16_combout ;wire \A_SPW_TOP|tx_data|Selector149~0_combout ;wire \A_SPW_TOP|tx_data|Selector149~1_combout ;wire \A_SPW_TOP|tx_data|mem[16][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~22_combout ;wire \A_SPW_TOP|tx_data|Selector473~0_combout ;wire \A_SPW_TOP|tx_data|Selector473~1_combout ;wire \A_SPW_TOP|tx_data|mem[52][8]~q ;wire \A_SPW_TOP|tx_data|Mux0~2_combout ;wire \A_SPW_TOP|tx_data|Decoder0~17_combout ;wire \A_SPW_TOP|tx_data|Selector221~0_combout ;wire \A_SPW_TOP|tx_data|Selector221~1_combout ;wire \A_SPW_TOP|tx_data|mem[24][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~21_combout ;wire \A_SPW_TOP|tx_data|Selector509~0_combout ;wire \A_SPW_TOP|tx_data|Selector509~1_combout ;wire \A_SPW_TOP|tx_data|mem[56][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~23_combout ;wire \A_SPW_TOP|tx_data|Selector545~0_combout ;wire \A_SPW_TOP|tx_data|Selector545~1_combout ;wire \A_SPW_TOP|tx_data|mem[60][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~19_combout ;wire \A_SPW_TOP|tx_data|Selector257~0_combout ;wire \A_SPW_TOP|tx_data|Selector257~1_combout ;wire \A_SPW_TOP|tx_data|mem[28][8]~q ;wire \A_SPW_TOP|tx_data|Mux0~3_combout ;wire \A_SPW_TOP|tx_data|Decoder0~4_combout ;wire \A_SPW_TOP|tx_data|Selector77~0_combout ;wire \A_SPW_TOP|tx_data|Selector77~1_combout ;wire \A_SPW_TOP|tx_data|mem[8][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~12_combout ;wire \A_SPW_TOP|tx_data|Selector113~0_combout ;wire \A_SPW_TOP|tx_data|Selector113~1_combout ;wire \A_SPW_TOP|tx_data|mem[12][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~5_combout ;wire \A_SPW_TOP|tx_data|Selector365~0_combout ;wire \A_SPW_TOP|tx_data|Selector365~1_combout ;wire \A_SPW_TOP|tx_data|mem[40][8]~q ;wire \A_SPW_TOP|tx_data|Mux0~1_combout ;wire \A_SPW_TOP|tx_data|Decoder0~1_combout ;wire \A_SPW_TOP|tx_data|Selector293~0_combout ;wire \A_SPW_TOP|tx_data|Selector293~1_combout ;wire \A_SPW_TOP|tx_data|mem[32][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~0_combout ;wire \A_SPW_TOP|tx_data|Selector5~0_combout ;wire \A_SPW_TOP|tx_data|Selector5~1_combout ;wire \A_SPW_TOP|tx_data|mem[0][8]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[0][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~9_combout ;wire \A_SPW_TOP|tx_data|Selector329~0_combout ;wire \A_SPW_TOP|tx_data|Selector329~1_combout ;wire \A_SPW_TOP|tx_data|mem[36][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~8_combout ;wire \A_SPW_TOP|tx_data|Selector41~0_combout ;wire \A_SPW_TOP|tx_data|Selector41~1_combout ;wire \A_SPW_TOP|tx_data|mem[4][8]~q ;wire \A_SPW_TOP|tx_data|Mux0~0_combout ;wire \A_SPW_TOP|tx_data|Mux0~4_combout ;wire \A_SPW_TOP|tx_data|Decoder0~58_combout ;wire \A_SPW_TOP|tx_data|Selector212~0_combout ;wire \A_SPW_TOP|tx_data|Selector212~1_combout ;wire \A_SPW_TOP|tx_data|mem[23][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~42_combout ;wire \A_SPW_TOP|tx_data|Selector68~0_combout ;wire \A_SPW_TOP|tx_data|Selector68~1_combout ;wire \A_SPW_TOP|tx_data|mem[7][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~59_combout ;wire \A_SPW_TOP|tx_data|Selector284~0_combout ;wire \A_SPW_TOP|tx_data|Selector284~1_combout ;wire \A_SPW_TOP|tx_data|mem[31][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~46_combout ;wire \A_SPW_TOP|tx_data|Selector140~0_combout ;wire \A_SPW_TOP|tx_data|Selector140~1_combout ;wire \A_SPW_TOP|tx_data|mem[15][8]~q ;wire \A_SPW_TOP|tx_data|Mux0~17_combout ;wire \A_SPW_TOP|tx_data|Decoder0~47_combout ;wire \A_SPW_TOP|tx_data|Selector428~0_combout ;wire \A_SPW_TOP|tx_data|Selector428~1_combout ;wire \A_SPW_TOP|tx_data|mem[47][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~62_combout ;wire \A_SPW_TOP|tx_data|Selector500~0_combout ;wire \A_SPW_TOP|tx_data|Selector500~1_combout ;wire \A_SPW_TOP|tx_data|mem[55][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~63_combout ;wire \A_SPW_TOP|tx_data|Selector572~0_combout ;wire \A_SPW_TOP|tx_data|Selector572~1_combout ;wire \A_SPW_TOP|tx_data|mem[63][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~43_combout ;wire \A_SPW_TOP|tx_data|Selector356~0_combout ;wire \A_SPW_TOP|tx_data|Selector356~1_combout ;wire \A_SPW_TOP|tx_data|mem[39][8]~q ;wire \A_SPW_TOP|tx_data|Mux0~18_combout ;wire \A_SPW_TOP|tx_data|Decoder0~34_combout ;wire \A_SPW_TOP|tx_data|Selector32~0_combout ;wire \A_SPW_TOP|tx_data|Selector32~1_combout ;wire \A_SPW_TOP|tx_data|mem[3][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~38_combout ;wire \A_SPW_TOP|tx_data|Selector104~0_combout ;wire \A_SPW_TOP|tx_data|Selector104~1_combout ;wire \A_SPW_TOP|tx_data|mem[11][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~56_combout ;wire \A_SPW_TOP|tx_data|Selector176~0_combout ;wire \A_SPW_TOP|tx_data|Selector176~1_combout ;wire \A_SPW_TOP|tx_data|mem[19][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~57_combout ;wire \A_SPW_TOP|tx_data|Selector248~0_combout ;wire \A_SPW_TOP|tx_data|Selector248~1_combout ;wire \A_SPW_TOP|tx_data|mem[27][8]~q ;wire \A_SPW_TOP|tx_data|Mux0~15_combout ;wire \A_SPW_TOP|tx_data|Decoder0~39_combout ;wire \A_SPW_TOP|tx_data|Selector392~0_combout ;wire \A_SPW_TOP|tx_data|Selector392~1_combout ;wire \A_SPW_TOP|tx_data|mem[43][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~35_combout ;wire \A_SPW_TOP|tx_data|Selector320~0_combout ;wire \A_SPW_TOP|tx_data|Selector320~1_combout ;wire \A_SPW_TOP|tx_data|mem[35][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~60_combout ;wire \A_SPW_TOP|tx_data|Selector464~0_combout ;wire \A_SPW_TOP|tx_data|Selector464~1_combout ;wire \A_SPW_TOP|tx_data|mem[51][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~61_combout ;wire \A_SPW_TOP|tx_data|Selector536~0_combout ;wire \A_SPW_TOP|tx_data|Selector536~1_combout ;wire \A_SPW_TOP|tx_data|mem[59][8]~q ;wire \A_SPW_TOP|tx_data|Mux0~16_combout ;wire \A_SPW_TOP|tx_data|Mux0~19_combout ;wire \A_SPW_TOP|tx_data|Decoder0~27_combout ;wire \A_SPW_TOP|tx_data|Selector275~0_combout ;wire \A_SPW_TOP|tx_data|Selector275~1_combout ;wire \A_SPW_TOP|tx_data|mem[30][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~26_combout ;wire \A_SPW_TOP|tx_data|Selector203~0_combout ;wire \A_SPW_TOP|tx_data|Selector203~1_combout ;wire \A_SPW_TOP|tx_data|mem[22][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~14_combout ;wire \A_SPW_TOP|tx_data|Selector131~0_combout ;wire \A_SPW_TOP|tx_data|Selector131~1_combout ;wire \A_SPW_TOP|tx_data|mem[14][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~10_combout ;wire \A_SPW_TOP|tx_data|Selector59~0_combout ;wire \A_SPW_TOP|tx_data|Selector59~1_combout ;wire \A_SPW_TOP|tx_data|mem[6][8]~q ;wire \A_SPW_TOP|tx_data|Mux0~7_combout ;wire \A_SPW_TOP|tx_data|Decoder0~24_combout ;wire \A_SPW_TOP|tx_data|Selector167~0_combout ;wire \A_SPW_TOP|tx_data|Selector167~1_combout ;wire \A_SPW_TOP|tx_data|mem[18][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~2_combout ;wire \A_SPW_TOP|tx_data|Selector23~0_combout ;wire \A_SPW_TOP|tx_data|Selector23~1_combout ;wire \A_SPW_TOP|tx_data|mem[2][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~25_combout ;wire \A_SPW_TOP|tx_data|Selector239~0_combout ;wire \A_SPW_TOP|tx_data|Selector239~1_combout ;wire \A_SPW_TOP|tx_data|mem[26][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~6_combout ;wire \A_SPW_TOP|tx_data|Selector95~0_combout ;wire \A_SPW_TOP|tx_data|Selector95~1_combout ;wire \A_SPW_TOP|tx_data|mem[10][8]~q ;wire \A_SPW_TOP|tx_data|Mux0~5_combout ;wire \A_SPW_TOP|tx_data|Decoder0~7_combout ;wire \A_SPW_TOP|tx_data|Selector383~0_combout ;wire \A_SPW_TOP|tx_data|Selector383~1_combout ;wire \A_SPW_TOP|tx_data|mem[42][8]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[42][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~28_combout ;wire \A_SPW_TOP|tx_data|Selector455~0_combout ;wire \A_SPW_TOP|tx_data|Selector455~1_combout ;wire \A_SPW_TOP|tx_data|mem[50][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~29_combout ;wire \A_SPW_TOP|tx_data|Selector527~0_combout ;wire \A_SPW_TOP|tx_data|Selector527~1_combout ;wire \A_SPW_TOP|tx_data|mem[58][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~3_combout ;wire \A_SPW_TOP|tx_data|Selector311~0_combout ;wire \A_SPW_TOP|tx_data|Selector311~1_combout ;wire \A_SPW_TOP|tx_data|mem[34][8]~q ;wire \A_SPW_TOP|tx_data|Mux0~6_combout ;wire \A_SPW_TOP|tx_data|Decoder0~15_combout ;wire \A_SPW_TOP|tx_data|Selector419~0_combout ;wire \A_SPW_TOP|tx_data|Selector419~1_combout ;wire \A_SPW_TOP|tx_data|mem[46][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~30_combout ;wire \A_SPW_TOP|tx_data|Selector491~0_combout ;wire \A_SPW_TOP|tx_data|Selector491~1_combout ;wire \A_SPW_TOP|tx_data|mem[54][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~11_combout ;wire \A_SPW_TOP|tx_data|Selector347~0_combout ;wire \A_SPW_TOP|tx_data|Selector347~1_combout ;wire \A_SPW_TOP|tx_data|mem[38][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~31_combout ;wire \A_SPW_TOP|tx_data|Selector563~0_combout ;wire \A_SPW_TOP|tx_data|Selector563~1_combout ;wire \A_SPW_TOP|tx_data|mem[62][8]~q ;wire \A_SPW_TOP|tx_data|Mux0~8_combout ;wire \A_SPW_TOP|tx_data|Mux0~9_combout ;wire \A_SPW_TOP|tx_data|Decoder0~37_combout ;wire \A_SPW_TOP|tx_data|Selector374~0_combout ;wire \A_SPW_TOP|tx_data|Selector374~1_combout ;wire \A_SPW_TOP|tx_data|mem[41][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~45_combout ;wire \A_SPW_TOP|tx_data|Selector410~0_combout ;wire \A_SPW_TOP|tx_data|Selector410~1_combout ;wire \A_SPW_TOP|tx_data|mem[45][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~36_combout ;wire \A_SPW_TOP|tx_data|Selector86~0_combout ;wire \A_SPW_TOP|tx_data|Selector86~1_combout ;wire \A_SPW_TOP|tx_data|mem[9][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~44_combout ;wire \A_SPW_TOP|tx_data|Selector122~0_combout ;wire \A_SPW_TOP|tx_data|Selector122~1_combout ;wire \A_SPW_TOP|tx_data|mem[13][8]~q ;wire \A_SPW_TOP|tx_data|Mux0~11_combout ;wire \A_SPW_TOP|tx_data|Decoder0~32_combout ;wire \A_SPW_TOP|tx_data|Selector14~0_combout ;wire \A_SPW_TOP|tx_data|Selector14~1_combout ;wire \A_SPW_TOP|tx_data|mem[1][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~40_combout ;wire \A_SPW_TOP|tx_data|Selector50~0_combout ;wire \A_SPW_TOP|tx_data|Selector50~1_combout ;wire \A_SPW_TOP|tx_data|mem[5][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~33_combout ;wire \A_SPW_TOP|tx_data|Selector302~0_combout ;wire \A_SPW_TOP|tx_data|Selector302~1_combout ;wire \A_SPW_TOP|tx_data|mem[33][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~41_combout ;wire \A_SPW_TOP|tx_data|Selector338~0_combout ;wire \A_SPW_TOP|tx_data|Selector338~1_combout ;wire \A_SPW_TOP|tx_data|mem[37][8]~q ;wire \A_SPW_TOP|tx_data|Mux0~10_combout ;wire \A_SPW_TOP|tx_data|Decoder0~55_combout ;wire \A_SPW_TOP|tx_data|Selector554~0_combout ;wire \A_SPW_TOP|tx_data|Selector554~1_combout ;wire \A_SPW_TOP|tx_data|mem[61][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~49_combout ;wire \A_SPW_TOP|tx_data|Selector230~0_combout ;wire \A_SPW_TOP|tx_data|Selector230~1_combout ;wire \A_SPW_TOP|tx_data|mem[25][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~53_combout ;wire \A_SPW_TOP|tx_data|Selector518~0_combout ;wire \A_SPW_TOP|tx_data|Selector518~1_combout ;wire \A_SPW_TOP|tx_data|mem[57][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~51_combout ;wire \A_SPW_TOP|tx_data|Selector266~0_combout ;wire \A_SPW_TOP|tx_data|Selector266~1_combout ;wire \A_SPW_TOP|tx_data|mem[29][8]~q ;wire \A_SPW_TOP|tx_data|Mux0~13_combout ;wire \A_SPW_TOP|tx_data|Decoder0~48_combout ;wire \A_SPW_TOP|tx_data|Selector158~0_combout ;wire \A_SPW_TOP|tx_data|Selector158~1_combout ;wire \A_SPW_TOP|tx_data|mem[17][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~52_combout ;wire \A_SPW_TOP|tx_data|Selector446~0_combout ;wire \A_SPW_TOP|tx_data|Selector446~1_combout ;wire \A_SPW_TOP|tx_data|mem[49][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~54_combout ;wire \A_SPW_TOP|tx_data|Selector482~0_combout ;wire \A_SPW_TOP|tx_data|Selector482~1_combout ;wire \A_SPW_TOP|tx_data|mem[53][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~50_combout ;wire \A_SPW_TOP|tx_data|Selector194~0_combout ;wire \A_SPW_TOP|tx_data|Selector194~1_combout ;wire \A_SPW_TOP|tx_data|mem[21][8]~q ;wire \A_SPW_TOP|tx_data|Mux0~12_combout ;wire \A_SPW_TOP|tx_data|Mux0~14_combout ;wire \A_SPW_TOP|tx_data|Mux0~20_combout ;wire \A_SPW_TOP|tx_data|Selector401~1_combout ;wire \A_SPW_TOP|tx_data|mem[44][8]~q ;wire \A_SPW_TOP|tx_data|Mux9~3_combout ;wire \A_SPW_TOP|tx_data|Mux9~2_combout ;wire \A_SPW_TOP|tx_data|Mux9~0_combout ;wire \A_SPW_TOP|tx_data|Mux9~1_combout ;wire \A_SPW_TOP|tx_data|Mux9~4_combout ;wire \A_SPW_TOP|tx_data|Mux9~17_combout ;wire \A_SPW_TOP|tx_data|Mux9~18_combout ;wire \A_SPW_TOP|tx_data|Mux9~16_combout ;wire \A_SPW_TOP|tx_data|Mux9~15_combout ;wire \A_SPW_TOP|tx_data|Mux9~19_combout ;wire \A_SPW_TOP|tx_data|Mux9~10_combout ;wire \A_SPW_TOP|tx_data|Mux9~11_combout ;wire \A_SPW_TOP|tx_data|Mux9~12_combout ;wire \A_SPW_TOP|tx_data|Mux9~13_combout ;wire \A_SPW_TOP|tx_data|Mux9~14_combout ;wire \A_SPW_TOP|tx_data|Mux9~8_combout ;wire \A_SPW_TOP|tx_data|Mux9~7_combout ;wire \A_SPW_TOP|tx_data|Mux9~6_combout ;wire \A_SPW_TOP|tx_data|Mux9~5_combout ;wire \A_SPW_TOP|tx_data|Mux9~9_combout ;wire \A_SPW_TOP|tx_data|Mux9~20_combout ;wire \A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector32~0_combout ;wire \A_SPW_TOP|SPW|TX|next_state_tx~1_combout ;wire \A_SPW_TOP|SPW|TX|state_tx~15_combout ;wire \A_SPW_TOP|SPW|TX|next_state_tx~0_combout ;wire \A_SPW_TOP|SPW|TX|state_tx~13_combout ;wire \A_SPW_TOP|SPW|TX|state_tx~14_combout ;wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c_0~q ;wire \A_SPW_TOP|SPW|TX|state_tx~30_combout ;wire \A_SPW_TOP|SPW|TX|state_tx~29_combout ;wire \A_SPW_TOP|SPW|TX|state_tx~31_combout ;wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_time_code_c~q ;wire \A_SPW_TOP|SPW|TX|Selector39~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector40~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector32~1_combout ;wire \A_SPW_TOP|SPW|TX|Selector42~0_combout ;wire \A_SPW_TOP|SPW|TX|state_fct_p~16_combout ;wire \A_SPW_TOP|SPW|TX|state_fct_p.100~q ;wire \A_SPW_TOP|SPW|RX|always8~1_combout ;wire \A_SPW_TOP|SPW|RX|rx_got_fct~q ;wire \A_SPW_TOP|SPW|TX|state_fct_receive.000~0_combout ;wire \A_SPW_TOP|SPW|TX|state_fct_receive~13_combout ;wire \A_SPW_TOP|SPW|TX|state_fct_receive.000~q ;wire \A_SPW_TOP|SPW|TX|state_fct_receive~14_combout ;wire \A_SPW_TOP|SPW|TX|state_fct_receive.010~q ;wire \A_SPW_TOP|SPW|TX|state_fct_receive~11_combout ;wire \A_SPW_TOP|SPW|TX|state_fct_receive.001~q ;wire \A_SPW_TOP|SPW|TX|Selector11~0_combout ;wire \A_SPW_TOP|SPW|TX|state_fct_p~12_combout ;wire \A_SPW_TOP|SPW|TX|state_fct_p.001~q ;wire \A_SPW_TOP|SPW|TX|clear_reg~q ;wire \A_SPW_TOP|SPW|TX|state_fct_receive~15_combout ;wire \A_SPW_TOP|SPW|TX|state_fct_receive.011~q ;wire \A_SPW_TOP|SPW|TX|state_fct_receive~12_combout ;wire \A_SPW_TOP|SPW|TX|state_fct_receive.100~q ;wire \A_SPW_TOP|SPW|TX|Selector12~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector10~0_combout ;wire \A_SPW_TOP|SPW|TX|state_fct_p~14_combout ;wire \A_SPW_TOP|SPW|TX|state_fct_p~15_combout ;wire \A_SPW_TOP|SPW|TX|state_fct_p.000~q ;wire \A_SPW_TOP|SPW|TX|state_fct_p~13_combout ;wire \A_SPW_TOP|SPW|TX|state_fct_p.010~q ;wire \A_SPW_TOP|SPW|TX|state_fct_p.000~0_combout ;wire \A_SPW_TOP|SPW|TX|state_fct_p~11_combout ;wire \A_SPW_TOP|SPW|TX|state_fct_p.011~q ;wire \A_SPW_TOP|SPW|TX|Selector17~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector17~2_combout ;wire \A_SPW_TOP|SPW|TX|Selector21~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector22~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector21~1_combout ;wire \A_SPW_TOP|SPW|TX|Selector20~0_combout ;wire \A_SPW_TOP|SPW|TX|LessThan2~1_combout ;wire \A_SPW_TOP|SPW|TX|Selector19~0_combout ;wire \A_SPW_TOP|SPW|TX|LessThan2~2_combout ;wire \A_SPW_TOP|SPW|TX|Selector18~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector17~1_combout ;wire \A_SPW_TOP|SPW|TX|LessThan2~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector42~2_combout ;wire \A_SPW_TOP|SPW|TX|Selector40~2_combout ;wire \A_SPW_TOP|SPW|TX|Selector42~3_combout ;wire \A_SPW_TOP|SPW|TX|process_data_0~q ;wire \A_SPW_TOP|SPW|TX|state_tx~21_combout ;wire \A_SPW_TOP|SPW|TX|state_tx~22_combout ;wire \A_SPW_TOP|SPW|TX|Selector23~0_combout ;wire \A_SPW_TOP|SPW|TX|state_tx~23_combout ;wire \A_SPW_TOP|SPW|TX|state_tx~19_combout ;wire \A_SPW_TOP|SPW|TX|state_tx~20_combout ;wire \A_SPW_TOP|SPW|TX|state_tx~24_combout ;wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_c~q ;wire \A_SPW_TOP|SPW|TX|Selector51~1_combout ;wire \A_SPW_TOP|SPW|TX|Selector51~0_combout ;wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~5_combout ;wire \A_SPW_TOP|SPW|TX|Selector50~1_combout ;wire \A_SPW_TOP|SPW|TX|Selector51~2_combout ;wire \A_SPW_TOP|SPW|TX|tcode_rdy_trnsp~q ;wire \A_SPW_TOP|SPW|TX|state_tx~27_combout ;wire \A_SPW_TOP|SPW|TX|state_tx~28_combout ;wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct~q ;wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~1_combout ;wire \A_SPW_TOP|SPW|TX|LessThan6~1_combout ;wire \A_SPW_TOP|SPW|TX|Selector72~0_combout ;wire \A_SPW_TOP|SPW|TX|Equal0~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector72~1_combout ;wire \A_SPW_TOP|SPW|TX|fct_sent~q ;wire \A_SPW_TOP|SPW|TX|state_fct_send_p~12_combout ;wire \A_SPW_TOP|SPW|TX|state_fct_send_p.001~q ;wire \A_SPW_TOP|SPW|TX|state_fct_send_p.001~0_combout ;wire \A_SPW_TOP|SPW|TX|state_fct_send_p~11_combout ;wire \A_SPW_TOP|SPW|TX|state_fct_send_p.010~q ;wire \A_SPW_TOP|SPW|TX|state_fct_send_p~9_combout ;wire \A_SPW_TOP|SPW|TX|state_fct_send_p~10_combout ;wire \A_SPW_TOP|SPW|TX|state_fct_send_p.000~q ;wire \A_SPW_TOP|SPW|TX|Selector2~1_combout ;wire \A_SPW_TOP|SPW|TX|clear_reg_fct_flag~q ;wire \A_SPW_TOP|SPW|TX|fct_flag~1_combout ;wire \A_SPW_TOP|SPW|TX|Selector2~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector6~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector6~1_combout ;wire \A_SPW_TOP|SPW|TX|Selector5~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector5~1_combout ;wire \A_SPW_TOP|SPW|TX|Selector4~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector4~1_combout ;wire \A_SPW_TOP|SPW|TX|state_fct_send_p~8_combout ;wire \A_SPW_TOP|SPW|TX|state_tx~32_combout ;wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_fct_c~q ;wire \A_SPW_TOP|SPW|TX|Selector30~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector30~1_combout ;wire \A_SPW_TOP|SPW|TX|Selector30~2_combout ;wire \A_SPW_TOP|SPW|TX|Selector23~1_combout ;wire \A_SPW_TOP|SPW|TX|Selector63~0_combout ;wire \A_SPW_TOP|SPW|TX|WideOr12~combout ;wire \A_SPW_TOP|SPW|TX|Selector73~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector73~2_combout ;wire \A_SPW_TOP|SPW|TX|char_sent~q ;wire \A_SPW_TOP|SPW|TX|Selector41~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector41~1_combout ;wire \A_SPW_TOP|SPW|TX|Selector41~3_combout ;wire \A_SPW_TOP|SPW|TX|Selector30~4_combout ;wire \A_SPW_TOP|SPW|TX|Selector41~2_combout ;wire \A_SPW_TOP|SPW|TX|Selector41~4_combout ;wire \A_SPW_TOP|SPW|TX|process_data~q ;wire \A_SPW_TOP|SPW|TX|state_tx~17_combout ;wire \A_SPW_TOP|SPW|TX|state_tx~16_combout ;wire \A_SPW_TOP|SPW|TX|state_tx~18_combout ;wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_data_c~q ;wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~2_combout ;wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~3_combout ;wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~4_combout ;wire \A_SPW_TOP|SPW|TX|state_tx~12_combout ;wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q ;wire \A_SPW_TOP|SPW|TX|Selector65~0_combout ;wire \A_SPW_TOP|SPW|TX|Equal0~1_combout ;wire \A_SPW_TOP|SPW|TX|state_tx~25_combout ;wire \A_SPW_TOP|SPW|TX|state_tx~26_combout ;wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q ;wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~0_combout ;wire \A_SPW_TOP|SPW|TX|Add4~1_combout ;wire \A_SPW_TOP|SPW|TX|Selector62~1_combout ;wire \A_SPW_TOP|SPW|TX|Selector62~2_combout ;wire \A_SPW_TOP|SPW|TX|Equal0~3_combout ;wire \A_SPW_TOP|SPW|TX|Selector62~0_combout ;wire \A_SPW_TOP|SPW|TX|Add4~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector63~1_combout ;wire \A_SPW_TOP|SPW|TX|Selector63~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~1_combout ;wire \A_SPW_TOP|tx_data|Selector300~0_combout ;wire \A_SPW_TOP|tx_data|mem[32][1]~q ;wire \A_SPW_TOP|tx_data|Selector309~0_combout ;wire \A_SPW_TOP|tx_data|mem[33][1]~q ;wire \A_SPW_TOP|tx_data|Selector327~0_combout ;wire \A_SPW_TOP|tx_data|mem[35][1]~q ;wire \A_SPW_TOP|tx_data|Selector318~0_combout ;wire \A_SPW_TOP|tx_data|mem[34][1]~q ;wire \A_SPW_TOP|tx_data|Mux7~2_combout ;wire \A_SPW_TOP|tx_data|Selector21~0_combout ;wire \A_SPW_TOP|tx_data|mem[1][1]~q ;wire \A_SPW_TOP|tx_data|Selector30~0_combout ;wire \A_SPW_TOP|tx_data|mem[2][1]~q ;wire \A_SPW_TOP|tx_data|Selector12~0_combout ;wire \A_SPW_TOP|tx_data|mem[0][1]~q ;wire \A_SPW_TOP|tx_data|Selector39~0_combout ;wire \A_SPW_TOP|tx_data|mem[3][1]~q ;wire \A_SPW_TOP|tx_data|Mux7~0_combout ;wire \A_SPW_TOP|tx_data|Selector102~0_combout ;wire \A_SPW_TOP|tx_data|mem[10][1]~q ;wire \A_SPW_TOP|tx_data|Selector111~0_combout ;wire \A_SPW_TOP|tx_data|mem[11][1]~q ;wire \A_SPW_TOP|tx_data|Selector84~0_combout ;wire \A_SPW_TOP|tx_data|mem[8][1]~q ;wire \A_SPW_TOP|tx_data|Selector93~0_combout ;wire \A_SPW_TOP|tx_data|mem[9][1]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[9][1]~q ;wire \A_SPW_TOP|tx_data|Mux7~1_combout ;wire \A_SPW_TOP|tx_data|Selector399~0_combout ;wire \A_SPW_TOP|tx_data|mem[43][1]~q ;wire \A_SPW_TOP|tx_data|Selector381~0_combout ;wire \A_SPW_TOP|tx_data|mem[41][1]~q ;wire \A_SPW_TOP|tx_data|Selector372~0_combout ;wire \A_SPW_TOP|tx_data|mem[40][1]~q ;wire \A_SPW_TOP|tx_data|Selector390~0_combout ;wire \A_SPW_TOP|tx_data|mem[42][1]~q ;wire \A_SPW_TOP|tx_data|Mux7~3_combout ;wire \A_SPW_TOP|tx_data|Mux7~4_combout ;wire \A_SPW_TOP|tx_data|Selector210~0_combout ;wire \A_SPW_TOP|tx_data|mem[22][1]~q ;wire \A_SPW_TOP|tx_data|Selector507~0_combout ;wire \A_SPW_TOP|tx_data|mem[55][1]~q ;wire \A_SPW_TOP|tx_data|Selector498~0_combout ;wire \A_SPW_TOP|tx_data|mem[54][1]~q ;wire \A_SPW_TOP|tx_data|Selector219~0_combout ;wire \A_SPW_TOP|tx_data|mem[23][1]~q ;wire \A_SPW_TOP|tx_data|Mux7~17_combout ;wire \A_SPW_TOP|tx_data|Selector291~0_combout ;wire \A_SPW_TOP|tx_data|mem[31][1]~q ;wire \A_SPW_TOP|tx_data|Selector282~0_combout ;wire \A_SPW_TOP|tx_data|mem[30][1]~q ;wire \A_SPW_TOP|tx_data|Selector579~0_combout ;wire \A_SPW_TOP|tx_data|mem[63][1]~q ;wire \A_SPW_TOP|tx_data|Selector570~0_combout ;wire \A_SPW_TOP|tx_data|mem[62][1]~q ;wire \A_SPW_TOP|tx_data|Mux7~18_combout ;wire \A_SPW_TOP|tx_data|Selector552~0_combout ;wire \A_SPW_TOP|tx_data|mem[60][1]~q ;wire \A_SPW_TOP|tx_data|Selector264~0_combout ;wire \A_SPW_TOP|tx_data|mem[28][1]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[28][1]~q ;wire \A_SPW_TOP|tx_data|Selector273~0_combout ;wire \A_SPW_TOP|tx_data|mem[29][1]~q ;wire \A_SPW_TOP|tx_data|Selector561~0_combout ;wire \A_SPW_TOP|tx_data|mem[61][1]~q ;wire \A_SPW_TOP|tx_data|Mux7~16_combout ;wire \A_SPW_TOP|tx_data|Selector201~0_combout ;wire \A_SPW_TOP|tx_data|mem[21][1]~q ;wire \A_SPW_TOP|tx_data|Selector192~0_combout ;wire \A_SPW_TOP|tx_data|mem[20][1]~q ;wire \A_SPW_TOP|tx_data|Selector480~0_combout ;wire \A_SPW_TOP|tx_data|mem[52][1]~q ;wire \A_SPW_TOP|tx_data|Selector489~0_combout ;wire \A_SPW_TOP|tx_data|mem[53][1]~q ;wire \A_SPW_TOP|tx_data|Mux7~15_combout ;wire \A_SPW_TOP|tx_data|Mux7~19_combout ;wire \A_SPW_TOP|tx_data|Selector471~0_combout ;wire \A_SPW_TOP|tx_data|mem[51][1]~q ;wire \A_SPW_TOP|tx_data|Selector462~0_combout ;wire \A_SPW_TOP|tx_data|mem[50][1]~q ;wire \A_SPW_TOP|tx_data|Selector453~0_combout ;wire \A_SPW_TOP|tx_data|mem[49][1]~q ;wire \A_SPW_TOP|tx_data|Selector444~0_combout ;wire \A_SPW_TOP|tx_data|mem[48][1]~q ;wire \A_SPW_TOP|tx_data|Mux7~7_combout ;wire \A_SPW_TOP|tx_data|Selector246~0_combout ;wire \A_SPW_TOP|tx_data|mem[26][1]~q ;wire \A_SPW_TOP|tx_data|Selector237~0_combout ;wire \A_SPW_TOP|tx_data|mem[25][1]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[25][1]~q ;wire \A_SPW_TOP|tx_data|Selector228~0_combout ;wire \A_SPW_TOP|tx_data|mem[24][1]~q ;wire \A_SPW_TOP|tx_data|Selector255~0_combout ;wire \A_SPW_TOP|tx_data|mem[27][1]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[27][1]~q ;wire \A_SPW_TOP|tx_data|Mux7~6_combout ;wire \A_SPW_TOP|tx_data|Selector165~0_combout ;wire \A_SPW_TOP|tx_data|mem[17][1]~q ;wire \A_SPW_TOP|tx_data|Selector174~0_combout ;wire \A_SPW_TOP|tx_data|mem[18][1]~q ;wire \A_SPW_TOP|tx_data|Selector183~0_combout ;wire \A_SPW_TOP|tx_data|mem[19][1]~q ;wire \A_SPW_TOP|tx_data|Selector156~0_combout ;wire \A_SPW_TOP|tx_data|mem[16][1]~q ;wire \A_SPW_TOP|tx_data|Mux7~5_combout ;wire \A_SPW_TOP|tx_data|Selector543~0_combout ;wire \A_SPW_TOP|tx_data|mem[59][1]~q ;wire \A_SPW_TOP|tx_data|Selector525~0_combout ;wire \A_SPW_TOP|tx_data|mem[57][1]~q ;wire \A_SPW_TOP|tx_data|Selector516~0_combout ;wire \A_SPW_TOP|tx_data|mem[56][1]~q ;wire \A_SPW_TOP|tx_data|Selector534~0_combout ;wire \A_SPW_TOP|tx_data|mem[58][1]~q ;wire \A_SPW_TOP|tx_data|Mux7~8_combout ;wire \A_SPW_TOP|tx_data|Mux7~9_combout ;wire \A_SPW_TOP|tx_data|Selector426~0_combout ;wire \A_SPW_TOP|tx_data|mem[46][1]~q ;wire \A_SPW_TOP|tx_data|Selector435~0_combout ;wire \A_SPW_TOP|tx_data|mem[47][1]~q ;wire \A_SPW_TOP|tx_data|Selector417~0_combout ;wire \A_SPW_TOP|tx_data|mem[45][1]~q ;wire \A_SPW_TOP|tx_data|Selector408~0_combout ;wire \A_SPW_TOP|tx_data|mem[44][1]~q ;wire \A_SPW_TOP|tx_data|Mux7~13_combout ;wire \A_SPW_TOP|tx_data|Selector66~0_combout ;wire \A_SPW_TOP|tx_data|mem[6][1]~q ;wire \A_SPW_TOP|tx_data|Selector57~0_combout ;wire \A_SPW_TOP|tx_data|mem[5][1]~q ;wire \A_SPW_TOP|tx_data|Selector48~0_combout ;wire \A_SPW_TOP|tx_data|mem[4][1]~q ;wire \A_SPW_TOP|tx_data|Selector75~0_combout ;wire \A_SPW_TOP|tx_data|mem[7][1]~q ;wire \A_SPW_TOP|tx_data|Mux7~10_combout ;wire \A_SPW_TOP|tx_data|Selector363~0_combout ;wire \A_SPW_TOP|tx_data|mem[39][1]~q ;wire \A_SPW_TOP|tx_data|Selector354~0_combout ;wire \A_SPW_TOP|tx_data|mem[38][1]~q ;wire \A_SPW_TOP|tx_data|Selector345~0_combout ;wire \A_SPW_TOP|tx_data|mem[37][1]~q ;wire \A_SPW_TOP|tx_data|Selector336~0_combout ;wire \A_SPW_TOP|tx_data|mem[36][1]~q ;wire \A_SPW_TOP|tx_data|Mux7~12_combout ;wire \A_SPW_TOP|tx_data|Selector138~0_combout ;wire \A_SPW_TOP|tx_data|mem[14][1]~q ;wire \A_SPW_TOP|tx_data|Selector147~0_combout ;wire \A_SPW_TOP|tx_data|mem[15][1]~q ;wire \A_SPW_TOP|tx_data|Selector120~0_combout ;wire \A_SPW_TOP|tx_data|mem[12][1]~q ;wire \A_SPW_TOP|tx_data|Mux7~11_combout ;wire \A_SPW_TOP|tx_data|Mux7~14_combout ;wire \A_SPW_TOP|tx_data|Mux7~20_combout ;wire \A_SPW_TOP|tx_data|Selector129~0_combout ;wire \A_SPW_TOP|tx_data|mem[13][1]~q ;wire \A_SPW_TOP|tx_data|Mux16~12_combout ;wire \A_SPW_TOP|tx_data|Mux16~13_combout ;wire \A_SPW_TOP|tx_data|Mux16~10_combout ;wire \A_SPW_TOP|tx_data|Mux16~11_combout ;wire \A_SPW_TOP|tx_data|Mux16~14_combout ;wire \A_SPW_TOP|tx_data|Mux16~7_combout ;wire \A_SPW_TOP|tx_data|Mux16~6_combout ;wire \A_SPW_TOP|tx_data|Mux16~8_combout ;wire \A_SPW_TOP|tx_data|Mux16~5_combout ;wire \A_SPW_TOP|tx_data|Mux16~9_combout ;wire \A_SPW_TOP|tx_data|Mux16~1_combout ;wire \A_SPW_TOP|tx_data|Mux16~0_combout ;wire \A_SPW_TOP|tx_data|Mux16~2_combout ;wire \A_SPW_TOP|tx_data|Mux16~3_combout ;wire \A_SPW_TOP|tx_data|Mux16~4_combout ;wire \A_SPW_TOP|tx_data|Mux16~18_combout ;wire \A_SPW_TOP|tx_data|Mux16~17_combout ;wire \A_SPW_TOP|tx_data|Mux16~16_combout ;wire \A_SPW_TOP|tx_data|Mux16~15_combout ;wire \A_SPW_TOP|tx_data|Mux16~19_combout ;wire \A_SPW_TOP|tx_data|Mux16~20_combout ;wire \A_SPW_TOP|SPW|TX|Selector30~3_combout ;wire \A_SPW_TOP|SPW|TX|last_type~11_combout ;wire \A_SPW_TOP|SPW|TX|Selector67~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector39~1_combout ;wire \A_SPW_TOP|SPW|TX|last_type~10_combout ;wire \A_SPW_TOP|SPW|TX|Selector67~1_combout ;wire \A_SPW_TOP|SPW|TX|LessThan5~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector67~3_combout ;wire \A_SPW_TOP|SPW|TX|Selector67~2_combout ;wire \A_SPW_TOP|SPW|TX|Selector71~0_combout ;wire \A_SPW_TOP|SPW|TX|last_type~15_combout ;wire \A_SPW_TOP|SPW|TX|Selector68~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~0_combout ;wire \u0|write_data_fifo_tx|data_out[0]~feeder_combout ;wire \A_SPW_TOP|tx_data|Selector481~0_combout ;wire \A_SPW_TOP|tx_data|mem[52][0]~q ;wire \A_SPW_TOP|tx_data|Selector301~0_combout ;wire \A_SPW_TOP|tx_data|mem[32][0]~q ;wire \A_SPW_TOP|tx_data|Selector445~0_combout ;wire \A_SPW_TOP|tx_data|mem[48][0]~q ;wire \A_SPW_TOP|tx_data|Selector337~0_combout ;wire \A_SPW_TOP|tx_data|mem[36][0]~q ;wire \A_SPW_TOP|tx_data|Mux8~10_combout ;wire \A_SPW_TOP|tx_data|Selector490~0_combout ;wire \A_SPW_TOP|tx_data|mem[53][0]~q ;wire \A_SPW_TOP|tx_data|Selector346~0_combout ;wire \A_SPW_TOP|tx_data|mem[37][0]~q ;wire \A_SPW_TOP|tx_data|Selector454~0_combout ;wire \A_SPW_TOP|tx_data|mem[49][0]~q ;wire \A_SPW_TOP|tx_data|Selector310~0_combout ;wire \A_SPW_TOP|tx_data|mem[33][0]~q ;wire \A_SPW_TOP|tx_data|Mux8~11_combout ;wire \A_SPW_TOP|tx_data|Selector499~0_combout ;wire \A_SPW_TOP|tx_data|mem[54][0]~q ;wire \A_SPW_TOP|tx_data|Selector319~0_combout ;wire \A_SPW_TOP|tx_data|mem[34][0]~q ;wire \A_SPW_TOP|tx_data|Selector355~0_combout ;wire \A_SPW_TOP|tx_data|mem[38][0]~q ;wire \A_SPW_TOP|tx_data|Selector463~0_combout ;wire \A_SPW_TOP|tx_data|mem[50][0]~q ;wire \A_SPW_TOP|tx_data|Mux8~12_combout ;wire \A_SPW_TOP|tx_data|Selector508~0_combout ;wire \A_SPW_TOP|tx_data|mem[55][0]~q ;wire \A_SPW_TOP|tx_data|Selector328~0_combout ;wire \A_SPW_TOP|tx_data|mem[35][0]~q ;wire \A_SPW_TOP|tx_data|Selector472~0_combout ;wire \A_SPW_TOP|tx_data|mem[51][0]~q ;wire \A_SPW_TOP|tx_data|Selector364~0_combout ;wire \A_SPW_TOP|tx_data|mem[39][0]~q ;wire \A_SPW_TOP|tx_data|Mux8~13_combout ;wire \A_SPW_TOP|tx_data|Mux8~14_combout ;wire \A_SPW_TOP|tx_data|Selector139~0_combout ;wire \A_SPW_TOP|tx_data|mem[14][0]~q ;wire \A_SPW_TOP|tx_data|Selector283~0_combout ;wire \A_SPW_TOP|tx_data|mem[30][0]~q ;wire \A_SPW_TOP|tx_data|Selector103~0_combout ;wire \A_SPW_TOP|tx_data|mem[10][0]~q ;wire \A_SPW_TOP|tx_data|Selector247~0_combout ;wire \A_SPW_TOP|tx_data|mem[26][0]~q ;wire \A_SPW_TOP|tx_data|Mux8~7_combout ;wire \A_SPW_TOP|tx_data|Selector256~0_combout ;wire \A_SPW_TOP|tx_data|mem[27][0]~q ;wire \A_SPW_TOP|tx_data|Selector292~0_combout ;wire \A_SPW_TOP|tx_data|mem[31][0]~q ;wire \A_SPW_TOP|tx_data|Selector112~0_combout ;wire \A_SPW_TOP|tx_data|mem[11][0]~q ;wire \A_SPW_TOP|tx_data|Selector148~0_combout ;wire \A_SPW_TOP|tx_data|mem[15][0]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[15][0]~q ;wire \A_SPW_TOP|tx_data|Mux8~8_combout ;wire \A_SPW_TOP|tx_data|Selector229~0_combout ;wire \A_SPW_TOP|tx_data|mem[24][0]~q ;wire \A_SPW_TOP|tx_data|Selector265~0_combout ;wire \A_SPW_TOP|tx_data|mem[28][0]~q ;wire \A_SPW_TOP|tx_data|Selector85~0_combout ;wire \A_SPW_TOP|tx_data|mem[8][0]~q ;wire \A_SPW_TOP|tx_data|Selector121~0_combout ;wire \A_SPW_TOP|tx_data|mem[12][0]~q ;wire \A_SPW_TOP|tx_data|Mux8~5_combout ;wire \A_SPW_TOP|tx_data|Selector94~0_combout ;wire \A_SPW_TOP|tx_data|mem[9][0]~q ;wire \A_SPW_TOP|tx_data|Selector274~0_combout ;wire \A_SPW_TOP|tx_data|mem[29][0]~q ;wire \A_SPW_TOP|tx_data|Selector238~0_combout ;wire \A_SPW_TOP|tx_data|mem[25][0]~q ;wire \A_SPW_TOP|tx_data|Selector130~0_combout ;wire \A_SPW_TOP|tx_data|mem[13][0]~q ;wire \A_SPW_TOP|tx_data|Mux8~6_combout ;wire \A_SPW_TOP|tx_data|Mux8~9_combout ;wire \A_SPW_TOP|tx_data|Selector418~0_combout ;wire \A_SPW_TOP|tx_data|mem[45][0]~q ;wire \A_SPW_TOP|tx_data|Selector436~0_combout ;wire \A_SPW_TOP|tx_data|mem[47][0]~q ;wire \A_SPW_TOP|tx_data|Selector562~0_combout ;wire \A_SPW_TOP|tx_data|mem[61][0]~q ;wire \A_SPW_TOP|tx_data|Selector580~0_combout ;wire \A_SPW_TOP|tx_data|mem[63][0]~q ;wire \A_SPW_TOP|tx_data|Mux8~18_combout ;wire \A_SPW_TOP|tx_data|Selector373~0_combout ;wire \A_SPW_TOP|tx_data|mem[40][0]~q ;wire \A_SPW_TOP|tx_data|Selector391~0_combout ;wire \A_SPW_TOP|tx_data|mem[42][0]~q ;wire \A_SPW_TOP|tx_data|Selector535~0_combout ;wire \A_SPW_TOP|tx_data|mem[58][0]~q ;wire \A_SPW_TOP|tx_data|Selector517~0_combout ;wire \A_SPW_TOP|tx_data|mem[56][0]~q ;wire \A_SPW_TOP|tx_data|Mux8~15_combout ;wire \A_SPW_TOP|tx_data|Selector526~0_combout ;wire \A_SPW_TOP|tx_data|mem[57][0]~q ;wire \A_SPW_TOP|tx_data|Selector544~0_combout ;wire \A_SPW_TOP|tx_data|mem[59][0]~q ;wire \A_SPW_TOP|tx_data|Selector382~0_combout ;wire \A_SPW_TOP|tx_data|mem[41][0]~q ;wire \A_SPW_TOP|tx_data|Selector400~0_combout ;wire \A_SPW_TOP|tx_data|mem[43][0]~q ;wire \A_SPW_TOP|tx_data|Mux8~16_combout ;wire \A_SPW_TOP|tx_data|Selector553~0_combout ;wire \A_SPW_TOP|tx_data|mem[60][0]~q ;wire \A_SPW_TOP|tx_data|Selector427~0_combout ;wire \A_SPW_TOP|tx_data|mem[46][0]~q ;wire \A_SPW_TOP|tx_data|Selector409~0_combout ;wire \A_SPW_TOP|tx_data|mem[44][0]~q ;wire \A_SPW_TOP|tx_data|Selector571~0_combout ;wire \A_SPW_TOP|tx_data|mem[62][0]~q ;wire \A_SPW_TOP|tx_data|Mux8~17_combout ;wire \A_SPW_TOP|tx_data|Mux8~19_combout ;wire \A_SPW_TOP|tx_data|Selector166~0_combout ;wire \A_SPW_TOP|tx_data|mem[17][0]~q ;wire \A_SPW_TOP|tx_data|Selector22~0_combout ;wire \A_SPW_TOP|tx_data|mem[1][0]~q ;wire \A_SPW_TOP|tx_data|Selector202~0_combout ;wire \A_SPW_TOP|tx_data|mem[21][0]~q ;wire \A_SPW_TOP|tx_data|Selector58~0_combout ;wire \A_SPW_TOP|tx_data|mem[5][0]~q ;wire \A_SPW_TOP|tx_data|Mux8~1_combout ;wire \A_SPW_TOP|tx_data|Selector49~0_combout ;wire \A_SPW_TOP|tx_data|mem[4][0]~q ;wire \A_SPW_TOP|tx_data|Selector157~0_combout ;wire \A_SPW_TOP|tx_data|mem[16][0]~q ;wire \A_SPW_TOP|tx_data|Selector193~0_combout ;wire \A_SPW_TOP|tx_data|mem[20][0]~q ;wire \A_SPW_TOP|tx_data|Selector13~0_combout ;wire \A_SPW_TOP|tx_data|mem[0][0]~q ;wire \A_SPW_TOP|tx_data|Mux8~0_combout ;wire \A_SPW_TOP|tx_data|Selector40~0_combout ;wire \A_SPW_TOP|tx_data|mem[3][0]~q ;wire \A_SPW_TOP|tx_data|Selector76~0_combout ;wire \A_SPW_TOP|tx_data|mem[7][0]~q ;wire \A_SPW_TOP|tx_data|Selector184~0_combout ;wire \A_SPW_TOP|tx_data|mem[19][0]~q ;wire \A_SPW_TOP|tx_data|Selector220~0_combout ;wire \A_SPW_TOP|tx_data|mem[23][0]~q ;wire \A_SPW_TOP|tx_data|Mux8~3_combout ;wire \A_SPW_TOP|tx_data|Selector31~0_combout ;wire \A_SPW_TOP|tx_data|mem[2][0]~q ;wire \A_SPW_TOP|tx_data|Selector175~0_combout ;wire \A_SPW_TOP|tx_data|mem[18][0]~q ;wire \A_SPW_TOP|tx_data|Selector67~0_combout ;wire \A_SPW_TOP|tx_data|mem[6][0]~q ;wire \A_SPW_TOP|tx_data|Mux8~2_combout ;wire \A_SPW_TOP|tx_data|Mux8~4_combout ;wire \A_SPW_TOP|tx_data|Mux8~20_combout ;wire \A_SPW_TOP|tx_data|Selector211~0_combout ;wire \A_SPW_TOP|tx_data|mem[22][0]~q ;wire \A_SPW_TOP|tx_data|Mux17~2_combout ;wire \A_SPW_TOP|tx_data|Mux17~1_combout ;wire \A_SPW_TOP|tx_data|Mux17~3_combout ;wire \A_SPW_TOP|tx_data|Mux17~0_combout ;wire \A_SPW_TOP|tx_data|Mux17~4_combout ;wire \A_SPW_TOP|tx_data|Mux17~12_combout ;wire \A_SPW_TOP|tx_data|Mux17~13_combout ;wire \A_SPW_TOP|tx_data|Mux17~10_combout ;wire \A_SPW_TOP|tx_data|Mux17~11_combout ;wire \A_SPW_TOP|tx_data|Mux17~14_combout ;wire \A_SPW_TOP|tx_data|Mux17~17_combout ;wire \A_SPW_TOP|tx_data|Mux17~16_combout ;wire \A_SPW_TOP|tx_data|Mux17~15_combout ;wire \A_SPW_TOP|tx_data|Mux17~18_combout ;wire \A_SPW_TOP|tx_data|Mux17~19_combout ;wire \A_SPW_TOP|tx_data|Mux17~6_combout ;wire \A_SPW_TOP|tx_data|Mux17~5_combout ;wire \A_SPW_TOP|tx_data|Mux17~8_combout ;wire \A_SPW_TOP|tx_data|Mux17~7_combout ;wire \A_SPW_TOP|tx_data|Mux17~9_combout ;wire \A_SPW_TOP|tx_data|Mux17~20_combout ;wire \A_SPW_TOP|SPW|TX|Selector31~0_combout ;wire \A_SPW_TOP|SPW|TX|last_type~12_combout ;wire \A_SPW_TOP|SPW|TX|Selector68~1_combout ;wire \A_SPW_TOP|SPW|TX|Selector40~1_combout ;wire \A_SPW_TOP|SPW|TX|last_type~13_combout ;wire \A_SPW_TOP|SPW|TX|Selector68~2_combout ;wire \A_SPW_TOP|SPW|TX|last_type~17_combout ;wire \A_SPW_TOP|SPW|TX|last_type.EOP~q ;wire \A_SPW_TOP|SPW|TX|Selector70~1_combout ;wire \A_SPW_TOP|SPW|TX|Selector70~0_combout ;wire \A_SPW_TOP|SPW|TX|last_type~14_combout ;wire \A_SPW_TOP|SPW|TX|Selector70~2_combout ;wire \A_SPW_TOP|SPW|TX|Selector70~3_combout ;wire \A_SPW_TOP|SPW|TX|last_type~16_combout ;wire \A_SPW_TOP|SPW|TX|last_type.DATA~q ;wire \A_SPW_TOP|SPW|TX|Selector69~2_combout ;wire \A_SPW_TOP|SPW|TX|Selector69~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector69~1_combout ;wire \A_SPW_TOP|SPW|TX|last_type~18_combout ;wire \A_SPW_TOP|SPW|TX|last_type.EEP~q ;wire \A_SPW_TOP|SPW|TX|last_type~24_combout ;wire \A_SPW_TOP|SPW|TX|last_type.TIMEC~q ;wire \A_SPW_TOP|SPW|TX|last_type~19_combout ;wire \A_SPW_TOP|SPW|TX|last_type~21_combout ;wire \A_SPW_TOP|SPW|TX|last_type~20_combout ;wire \A_SPW_TOP|SPW|TX|last_type~22_combout ;wire \A_SPW_TOP|SPW|TX|last_type.NULL~q ;wire \A_SPW_TOP|SPW|TX|last_type.NULL~0_combout ;wire \A_SPW_TOP|SPW|TX|last_type~23_combout ;wire \A_SPW_TOP|SPW|TX|last_type.FCT~q ;wire \A_SPW_TOP|SPW|TX|always0~11_combout ;wire \A_SPW_TOP|SPW|TX|always0~10_combout ;wire \A_SPW_TOP|SPW|TX|always0~7_combout ;wire \A_SPW_TOP|SPW|TX|always0~6_combout ;wire \A_SPW_TOP|SPW|TX|always0~8_combout ;wire \A_SPW_TOP|SPW|TX|always0~9_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~23_combout ;wire \A_SPW_TOP|SPW|TX|Equal0~2_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~21_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~16_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~2_combout ;wire \A_SPW_TOP|tx_data|Selector479~0_combout ;wire \A_SPW_TOP|tx_data|mem[52][2]~q ;wire \A_SPW_TOP|tx_data|Selector263~0_combout ;wire \A_SPW_TOP|tx_data|mem[28][2]~q ;wire \A_SPW_TOP|tx_data|Selector551~0_combout ;wire \A_SPW_TOP|tx_data|mem[60][2]~q ;wire \A_SPW_TOP|tx_data|Selector191~0_combout ;wire \A_SPW_TOP|tx_data|mem[20][2]~q ;wire \A_SPW_TOP|tx_data|Mux6~3_combout ;wire \A_SPW_TOP|tx_data|Selector83~0_combout ;wire \A_SPW_TOP|tx_data|mem[8][2]~q ;wire \A_SPW_TOP|tx_data|Selector299~0_combout ;wire \A_SPW_TOP|tx_data|mem[32][2]~q ;wire \A_SPW_TOP|tx_data|Selector11~0_combout ;wire \A_SPW_TOP|tx_data|mem[0][2]~q ;wire \A_SPW_TOP|tx_data|Selector371~0_combout ;wire \A_SPW_TOP|tx_data|mem[40][2]~q ;wire \A_SPW_TOP|tx_data|Mux6~0_combout ;wire \A_SPW_TOP|tx_data|Selector119~0_combout ;wire \A_SPW_TOP|tx_data|mem[12][2]~q ;wire \A_SPW_TOP|tx_data|Selector335~0_combout ;wire \A_SPW_TOP|tx_data|mem[36][2]~q ;wire \A_SPW_TOP|tx_data|Selector407~0_combout ;wire \A_SPW_TOP|tx_data|mem[44][2]~q ;wire \A_SPW_TOP|tx_data|Selector47~0_combout ;wire \A_SPW_TOP|tx_data|mem[4][2]~q ;wire \A_SPW_TOP|tx_data|Mux6~1_combout ;wire \A_SPW_TOP|tx_data|Selector515~0_combout ;wire \A_SPW_TOP|tx_data|mem[56][2]~q ;wire \A_SPW_TOP|tx_data|Selector155~0_combout ;wire \A_SPW_TOP|tx_data|mem[16][2]~q ;wire \A_SPW_TOP|tx_data|Selector443~0_combout ;wire \A_SPW_TOP|tx_data|mem[48][2]~q ;wire \A_SPW_TOP|tx_data|Selector227~0_combout ;wire \A_SPW_TOP|tx_data|mem[24][2]~q ;wire \A_SPW_TOP|tx_data|Mux6~2_combout ;wire \A_SPW_TOP|tx_data|Mux6~4_combout ;wire \A_SPW_TOP|tx_data|Selector128~0_combout ;wire \A_SPW_TOP|tx_data|mem[13][2]~q ;wire \A_SPW_TOP|tx_data|Selector56~0_combout ;wire \A_SPW_TOP|tx_data|mem[5][2]~q ;wire \A_SPW_TOP|tx_data|Selector344~0_combout ;wire \A_SPW_TOP|tx_data|mem[37][2]~q ;wire \A_SPW_TOP|tx_data|Selector416~0_combout ;wire \A_SPW_TOP|tx_data|mem[45][2]~q ;wire \A_SPW_TOP|tx_data|Mux6~6_combout ;wire \A_SPW_TOP|tx_data|Selector308~0_combout ;wire \A_SPW_TOP|tx_data|mem[33][2]~q ;wire \A_SPW_TOP|tx_data|Selector380~0_combout ;wire \A_SPW_TOP|tx_data|mem[41][2]~q ;wire \A_SPW_TOP|tx_data|Selector92~0_combout ;wire \A_SPW_TOP|tx_data|mem[9][2]~q ;wire \A_SPW_TOP|tx_data|Mux6~5_combout ;wire \A_SPW_TOP|tx_data|Selector272~0_combout ;wire \A_SPW_TOP|tx_data|mem[29][2]~q ;wire \A_SPW_TOP|tx_data|Selector560~0_combout ;wire \A_SPW_TOP|tx_data|mem[61][2]~q ;wire \A_SPW_TOP|tx_data|Selector200~0_combout ;wire \A_SPW_TOP|tx_data|mem[21][2]~q ;wire \A_SPW_TOP|tx_data|Selector488~0_combout ;wire \A_SPW_TOP|tx_data|mem[53][2]~q ;wire \A_SPW_TOP|tx_data|Mux6~8_combout ;wire \A_SPW_TOP|tx_data|Selector236~0_combout ;wire \A_SPW_TOP|tx_data|mem[25][2]~q ;wire \A_SPW_TOP|tx_data|Selector524~0_combout ;wire \A_SPW_TOP|tx_data|mem[57][2]~q ;wire \A_SPW_TOP|tx_data|Selector452~0_combout ;wire \A_SPW_TOP|tx_data|mem[49][2]~q ;wire \A_SPW_TOP|tx_data|Selector164~0_combout ;wire \A_SPW_TOP|tx_data|mem[17][2]~q ;wire \A_SPW_TOP|tx_data|Mux6~7_combout ;wire \A_SPW_TOP|tx_data|Mux6~9_combout ;wire \A_SPW_TOP|tx_data|Selector434~0_combout ;wire \A_SPW_TOP|tx_data|mem[47][2]~q ;wire \A_SPW_TOP|tx_data|Selector362~0_combout ;wire \A_SPW_TOP|tx_data|mem[39][2]~q ;wire \A_SPW_TOP|tx_data|Selector326~0_combout ;wire \A_SPW_TOP|tx_data|mem[35][2]~q ;wire \A_SPW_TOP|tx_data|Selector398~0_combout ;wire \A_SPW_TOP|tx_data|mem[43][2]~q ;wire \A_SPW_TOP|tx_data|Mux6~16_combout ;wire \A_SPW_TOP|tx_data|Selector290~0_combout ;wire \A_SPW_TOP|tx_data|mem[31][2]~q ;wire \A_SPW_TOP|tx_data|Selector254~0_combout ;wire \A_SPW_TOP|tx_data|mem[27][2]~q ;wire \A_SPW_TOP|tx_data|Selector218~0_combout ;wire \A_SPW_TOP|tx_data|mem[23][2]~q ;wire \A_SPW_TOP|tx_data|Selector182~0_combout ;wire \A_SPW_TOP|tx_data|mem[19][2]~q ;wire \A_SPW_TOP|tx_data|Mux6~17_combout ;wire \A_SPW_TOP|tx_data|Selector542~0_combout ;wire \A_SPW_TOP|tx_data|mem[59][2]~q ;wire \A_SPW_TOP|tx_data|Selector506~0_combout ;wire \A_SPW_TOP|tx_data|mem[55][2]~q ;wire \A_SPW_TOP|tx_data|Selector578~0_combout ;wire \A_SPW_TOP|tx_data|mem[63][2]~q ;wire \A_SPW_TOP|tx_data|Selector470~0_combout ;wire \A_SPW_TOP|tx_data|mem[51][2]~q ;wire \A_SPW_TOP|tx_data|Mux6~18_combout ;wire \A_SPW_TOP|tx_data|Selector74~0_combout ;wire \A_SPW_TOP|tx_data|mem[7][2]~q ;wire \A_SPW_TOP|tx_data|Selector146~0_combout ;wire \A_SPW_TOP|tx_data|mem[15][2]~q ;wire \A_SPW_TOP|tx_data|Selector38~0_combout ;wire \A_SPW_TOP|tx_data|mem[3][2]~q ;wire \A_SPW_TOP|tx_data|Selector110~0_combout ;wire \A_SPW_TOP|tx_data|mem[11][2]~q ;wire \A_SPW_TOP|tx_data|Mux6~15_combout ;wire \A_SPW_TOP|tx_data|Mux6~19_combout ;wire \A_SPW_TOP|tx_data|Selector353~0_combout ;wire \A_SPW_TOP|tx_data|mem[38][2]~q ;wire \A_SPW_TOP|tx_data|Selector425~0_combout ;wire \A_SPW_TOP|tx_data|mem[46][2]~q ;wire \A_SPW_TOP|tx_data|Selector65~0_combout ;wire \A_SPW_TOP|tx_data|mem[6][2]~q ;wire \A_SPW_TOP|tx_data|Selector137~0_combout ;wire \A_SPW_TOP|tx_data|mem[14][2]~q ;wire \A_SPW_TOP|tx_data|Mux6~11_combout ;wire \A_SPW_TOP|tx_data|Selector389~0_combout ;wire \A_SPW_TOP|tx_data|mem[42][2]~q ;wire \A_SPW_TOP|tx_data|Selector29~0_combout ;wire \A_SPW_TOP|tx_data|mem[2][2]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[2][2]~q ;wire \A_SPW_TOP|tx_data|Selector101~0_combout ;wire \A_SPW_TOP|tx_data|mem[10][2]~q ;wire \A_SPW_TOP|tx_data|Selector317~0_combout ;wire \A_SPW_TOP|tx_data|mem[34][2]~q ;wire \A_SPW_TOP|tx_data|Mux6~10_combout ;wire \A_SPW_TOP|tx_data|Selector461~0_combout ;wire \A_SPW_TOP|tx_data|mem[50][2]~q ;wire \A_SPW_TOP|tx_data|Selector173~0_combout ;wire \A_SPW_TOP|tx_data|mem[18][2]~q ;wire \A_SPW_TOP|tx_data|Selector533~0_combout ;wire \A_SPW_TOP|tx_data|mem[58][2]~q ;wire \A_SPW_TOP|tx_data|Selector245~0_combout ;wire \A_SPW_TOP|tx_data|mem[26][2]~q ;wire \A_SPW_TOP|tx_data|Mux6~12_combout ;wire \A_SPW_TOP|tx_data|Selector497~0_combout ;wire \A_SPW_TOP|tx_data|mem[54][2]~q ;wire \A_SPW_TOP|tx_data|Selector281~0_combout ;wire \A_SPW_TOP|tx_data|mem[30][2]~q ;wire \A_SPW_TOP|tx_data|Selector569~0_combout ;wire \A_SPW_TOP|tx_data|mem[62][2]~q ;wire \A_SPW_TOP|tx_data|Selector209~0_combout ;wire \A_SPW_TOP|tx_data|mem[22][2]~q ;wire \A_SPW_TOP|tx_data|Mux6~13_combout ;wire \A_SPW_TOP|tx_data|Mux6~14_combout ;wire \A_SPW_TOP|tx_data|Mux6~20_combout ;wire \A_SPW_TOP|tx_data|Selector20~0_combout ;wire \A_SPW_TOP|tx_data|mem[1][2]~q ;wire \A_SPW_TOP|tx_data|Mux15~10_combout ;wire \A_SPW_TOP|tx_data|Mux15~13_combout ;wire \A_SPW_TOP|tx_data|Mux15~12_combout ;wire \A_SPW_TOP|tx_data|Mux15~11_combout ;wire \A_SPW_TOP|tx_data|Mux15~14_combout ;wire \A_SPW_TOP|tx_data|Mux15~16_combout ;wire \A_SPW_TOP|tx_data|Mux15~15_combout ;wire \A_SPW_TOP|tx_data|Mux15~18_combout ;wire \A_SPW_TOP|tx_data|Mux15~17_combout ;wire \A_SPW_TOP|tx_data|Mux15~19_combout ;wire \A_SPW_TOP|tx_data|Mux15~3_combout ;wire \A_SPW_TOP|tx_data|Mux15~1_combout ;wire \A_SPW_TOP|tx_data|Mux15~0_combout ;wire \A_SPW_TOP|tx_data|Mux15~2_combout ;wire \A_SPW_TOP|tx_data|Mux15~4_combout ;wire \A_SPW_TOP|tx_data|Mux15~8_combout ;wire \A_SPW_TOP|tx_data|Mux15~5_combout ;wire \A_SPW_TOP|tx_data|Mux15~7_combout ;wire \A_SPW_TOP|tx_data|Mux15~6_combout ;wire \A_SPW_TOP|tx_data|Mux15~9_combout ;wire \A_SPW_TOP|tx_data|Mux15~20_combout ;wire \A_SPW_TOP|SPW|TX|Selector38~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~3_combout ;wire \u0|write_data_fifo_tx|data_out[3]~feeder_combout ;wire \A_SPW_TOP|tx_data|Selector451~0_combout ;wire \A_SPW_TOP|tx_data|mem[49][3]~q ;wire \A_SPW_TOP|tx_data|Selector487~0_combout ;wire \A_SPW_TOP|tx_data|mem[53][3]~q ;wire \A_SPW_TOP|tx_data|Selector307~0_combout ;wire \A_SPW_TOP|tx_data|mem[33][3]~q ;wire \A_SPW_TOP|tx_data|Selector343~0_combout ;wire \A_SPW_TOP|tx_data|mem[37][3]~q ;wire \A_SPW_TOP|tx_data|Mux5~11_combout ;wire \A_SPW_TOP|tx_data|Selector316~0_combout ;wire \A_SPW_TOP|tx_data|mem[34][3]~q ;wire \A_SPW_TOP|tx_data|Selector460~0_combout ;wire \A_SPW_TOP|tx_data|mem[50][3]~q ;wire \A_SPW_TOP|tx_data|Selector496~0_combout ;wire \A_SPW_TOP|tx_data|mem[54][3]~q ;wire \A_SPW_TOP|tx_data|Selector352~0_combout ;wire \A_SPW_TOP|tx_data|mem[38][3]~q ;wire \A_SPW_TOP|tx_data|Mux5~12_combout ;wire \A_SPW_TOP|tx_data|Selector334~0_combout ;wire \A_SPW_TOP|tx_data|mem[36][3]~q ;wire \A_SPW_TOP|tx_data|Selector478~0_combout ;wire \A_SPW_TOP|tx_data|mem[52][3]~q ;wire \A_SPW_TOP|tx_data|Selector442~0_combout ;wire \A_SPW_TOP|tx_data|mem[48][3]~q ;wire \A_SPW_TOP|tx_data|Selector298~0_combout ;wire \A_SPW_TOP|tx_data|mem[32][3]~q ;wire \A_SPW_TOP|tx_data|Mux5~10_combout ;wire \A_SPW_TOP|tx_data|Selector361~0_combout ;wire \A_SPW_TOP|tx_data|mem[39][3]~q ;wire \A_SPW_TOP|tx_data|Selector469~0_combout ;wire \A_SPW_TOP|tx_data|mem[51][3]~q ;wire \A_SPW_TOP|tx_data|Selector505~0_combout ;wire \A_SPW_TOP|tx_data|mem[55][3]~q ;wire \A_SPW_TOP|tx_data|Selector325~0_combout ;wire \A_SPW_TOP|tx_data|mem[35][3]~q ;wire \A_SPW_TOP|tx_data|Mux5~13_combout ;wire \A_SPW_TOP|tx_data|Mux5~14_combout ;wire \A_SPW_TOP|tx_data|Selector190~0_combout ;wire \A_SPW_TOP|tx_data|mem[20][3]~q ;wire \A_SPW_TOP|tx_data|Selector154~0_combout ;wire \A_SPW_TOP|tx_data|mem[16][3]~q ;wire \A_SPW_TOP|tx_data|Selector46~0_combout ;wire \A_SPW_TOP|tx_data|mem[4][3]~q ;wire \A_SPW_TOP|tx_data|Selector10~0_combout ;wire \A_SPW_TOP|tx_data|mem[0][3]~q ;wire \A_SPW_TOP|tx_data|Mux5~0_combout ;wire \A_SPW_TOP|tx_data|Selector64~0_combout ;wire \A_SPW_TOP|tx_data|mem[6][3]~q ;wire \A_SPW_TOP|tx_data|Selector28~0_combout ;wire \A_SPW_TOP|tx_data|mem[2][3]~q ;wire \A_SPW_TOP|tx_data|Selector208~0_combout ;wire \A_SPW_TOP|tx_data|mem[22][3]~q ;wire \A_SPW_TOP|tx_data|Selector172~0_combout ;wire \A_SPW_TOP|tx_data|mem[18][3]~q ;wire \A_SPW_TOP|tx_data|Mux5~2_combout ;wire \A_SPW_TOP|tx_data|Selector19~0_combout ;wire \A_SPW_TOP|tx_data|mem[1][3]~q ;wire \A_SPW_TOP|tx_data|Selector55~0_combout ;wire \A_SPW_TOP|tx_data|mem[5][3]~q ;wire \A_SPW_TOP|tx_data|Selector163~0_combout ;wire \A_SPW_TOP|tx_data|mem[17][3]~q ;wire \A_SPW_TOP|tx_data|Selector199~0_combout ;wire \A_SPW_TOP|tx_data|mem[21][3]~q ;wire \A_SPW_TOP|tx_data|Mux5~1_combout ;wire \A_SPW_TOP|tx_data|Selector181~0_combout ;wire \A_SPW_TOP|tx_data|mem[19][3]~q ;wire \A_SPW_TOP|tx_data|Selector73~0_combout ;wire \A_SPW_TOP|tx_data|mem[7][3]~q ;wire \A_SPW_TOP|tx_data|Selector217~0_combout ;wire \A_SPW_TOP|tx_data|mem[23][3]~q ;wire \A_SPW_TOP|tx_data|Selector37~0_combout ;wire \A_SPW_TOP|tx_data|mem[3][3]~q ;wire \A_SPW_TOP|tx_data|Mux5~3_combout ;wire \A_SPW_TOP|tx_data|Mux5~4_combout ;wire \A_SPW_TOP|tx_data|Selector271~0_combout ;wire \A_SPW_TOP|tx_data|mem[29][3]~q ;wire \A_SPW_TOP|tx_data|Selector235~0_combout ;wire \A_SPW_TOP|tx_data|mem[25][3]~q ;wire \A_SPW_TOP|tx_data|Selector127~0_combout ;wire \A_SPW_TOP|tx_data|mem[13][3]~q ;wire \A_SPW_TOP|tx_data|Selector91~0_combout ;wire \A_SPW_TOP|tx_data|mem[9][3]~q ;wire \A_SPW_TOP|tx_data|Mux5~6_combout ;wire \A_SPW_TOP|tx_data|Selector253~0_combout ;wire \A_SPW_TOP|tx_data|mem[27][3]~q ;wire \A_SPW_TOP|tx_data|Selector109~0_combout ;wire \A_SPW_TOP|tx_data|mem[11][3]~q ;wire \A_SPW_TOP|tx_data|Selector145~0_combout ;wire \A_SPW_TOP|tx_data|mem[15][3]~q ;wire \A_SPW_TOP|tx_data|Mux5~8_combout ;wire \A_SPW_TOP|tx_data|Selector118~0_combout ;wire \A_SPW_TOP|tx_data|mem[12][3]~q ;wire \A_SPW_TOP|tx_data|Selector226~0_combout ;wire \A_SPW_TOP|tx_data|mem[24][3]~q ;wire \A_SPW_TOP|tx_data|Selector82~0_combout ;wire \A_SPW_TOP|tx_data|mem[8][3]~q ;wire \A_SPW_TOP|tx_data|Selector262~0_combout ;wire \A_SPW_TOP|tx_data|mem[28][3]~q ;wire \A_SPW_TOP|tx_data|Mux5~5_combout ;wire \A_SPW_TOP|tx_data|Selector280~0_combout ;wire \A_SPW_TOP|tx_data|mem[30][3]~q ;wire \A_SPW_TOP|tx_data|Selector100~0_combout ;wire \A_SPW_TOP|tx_data|mem[10][3]~q ;wire \A_SPW_TOP|tx_data|Selector136~0_combout ;wire \A_SPW_TOP|tx_data|mem[14][3]~q ;wire \A_SPW_TOP|tx_data|Selector244~0_combout ;wire \A_SPW_TOP|tx_data|mem[26][3]~q ;wire \A_SPW_TOP|tx_data|Mux5~7_combout ;wire \A_SPW_TOP|tx_data|Mux5~9_combout ;wire \A_SPW_TOP|tx_data|Selector388~0_combout ;wire \A_SPW_TOP|tx_data|mem[42][3]~q ;wire \A_SPW_TOP|tx_data|Selector370~0_combout ;wire \A_SPW_TOP|tx_data|mem[40][3]~q ;wire \A_SPW_TOP|tx_data|Selector532~0_combout ;wire \A_SPW_TOP|tx_data|mem[58][3]~q ;wire \A_SPW_TOP|tx_data|Selector514~0_combout ;wire \A_SPW_TOP|tx_data|mem[56][3]~q ;wire \A_SPW_TOP|tx_data|Mux5~15_combout ;wire \A_SPW_TOP|tx_data|Selector415~0_combout ;wire \A_SPW_TOP|tx_data|mem[45][3]~q ;wire \A_SPW_TOP|tx_data|Selector577~0_combout ;wire \A_SPW_TOP|tx_data|mem[63][3]~q ;wire \A_SPW_TOP|tx_data|Selector559~0_combout ;wire \A_SPW_TOP|tx_data|mem[61][3]~q ;wire \A_SPW_TOP|tx_data|Selector433~0_combout ;wire \A_SPW_TOP|tx_data|mem[47][3]~q ;wire \A_SPW_TOP|tx_data|Mux5~18_combout ;wire \A_SPW_TOP|tx_data|Selector406~0_combout ;wire \A_SPW_TOP|tx_data|mem[44][3]~q ;wire \A_SPW_TOP|tx_data|Selector550~0_combout ;wire \A_SPW_TOP|tx_data|mem[60][3]~q ;wire \A_SPW_TOP|tx_data|Selector568~0_combout ;wire \A_SPW_TOP|tx_data|mem[62][3]~q ;wire \A_SPW_TOP|tx_data|Selector424~0_combout ;wire \A_SPW_TOP|tx_data|mem[46][3]~q ;wire \A_SPW_TOP|tx_data|Mux5~17_combout ;wire \A_SPW_TOP|tx_data|Selector523~0_combout ;wire \A_SPW_TOP|tx_data|mem[57][3]~q ;wire \A_SPW_TOP|tx_data|Selector397~0_combout ;wire \A_SPW_TOP|tx_data|mem[43][3]~q ;wire \A_SPW_TOP|tx_data|Selector541~0_combout ;wire \A_SPW_TOP|tx_data|mem[59][3]~q ;wire \A_SPW_TOP|tx_data|Selector379~0_combout ;wire \A_SPW_TOP|tx_data|mem[41][3]~q ;wire \A_SPW_TOP|tx_data|Mux5~16_combout ;wire \A_SPW_TOP|tx_data|Mux5~19_combout ;wire \A_SPW_TOP|tx_data|Mux5~20_combout ;wire \A_SPW_TOP|tx_data|Selector289~0_combout ;wire \A_SPW_TOP|tx_data|mem[31][3]~q ;wire \A_SPW_TOP|tx_data|Mux14~8_combout ;wire \A_SPW_TOP|tx_data|Mux14~7_combout ;wire \A_SPW_TOP|tx_data|Mux14~6_combout ;wire \A_SPW_TOP|tx_data|Mux14~5_combout ;wire \A_SPW_TOP|tx_data|Mux14~9_combout ;wire \A_SPW_TOP|tx_data|Mux14~15_combout ;wire \A_SPW_TOP|tx_data|Mux14~16_combout ;wire \A_SPW_TOP|tx_data|Mux14~17_combout ;wire \A_SPW_TOP|tx_data|Mux14~18_combout ;wire \A_SPW_TOP|tx_data|Mux14~19_combout ;wire \A_SPW_TOP|tx_data|Mux14~2_combout ;wire \A_SPW_TOP|tx_data|Mux14~1_combout ;wire \A_SPW_TOP|tx_data|Mux14~3_combout ;wire \A_SPW_TOP|tx_data|Mux14~0_combout ;wire \A_SPW_TOP|tx_data|Mux14~4_combout ;wire \A_SPW_TOP|tx_data|Mux14~12_combout ;wire \A_SPW_TOP|tx_data|Mux14~13_combout ;wire \A_SPW_TOP|tx_data|Mux14~10_combout ;wire \A_SPW_TOP|tx_data|Mux14~11_combout ;wire \A_SPW_TOP|tx_data|Mux14~14_combout ;wire \A_SPW_TOP|tx_data|Mux14~20_combout ;wire \A_SPW_TOP|SPW|TX|Selector37~0_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~39_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~19_combout ;wire \A_SPW_TOP|SPW|TX|LessThan6~0_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~15_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~18_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~7_combout ;wire \A_SPW_TOP|tx_data|Selector231~0_combout ;wire \A_SPW_TOP|tx_data|mem[25][7]~q ;wire \A_SPW_TOP|tx_data|Selector240~0_combout ;wire \A_SPW_TOP|tx_data|mem[26][7]~q ;wire \A_SPW_TOP|tx_data|Selector222~0_combout ;wire \A_SPW_TOP|tx_data|mem[24][7]~q ;wire \A_SPW_TOP|tx_data|Selector249~0_combout ;wire \A_SPW_TOP|tx_data|mem[27][7]~q ;wire \A_SPW_TOP|tx_data|Mux1~6_combout ;wire \A_SPW_TOP|tx_data|Selector456~0_combout ;wire \A_SPW_TOP|tx_data|mem[50][7]~q ;wire \A_SPW_TOP|tx_data|Selector438~0_combout ;wire \A_SPW_TOP|tx_data|mem[48][7]~q ;wire \A_SPW_TOP|tx_data|Selector465~0_combout ;wire \A_SPW_TOP|tx_data|mem[51][7]~q ;wire \A_SPW_TOP|tx_data|Selector447~0_combout ;wire \A_SPW_TOP|tx_data|mem[49][7]~q ;wire \A_SPW_TOP|tx_data|Mux1~7_combout ;wire \A_SPW_TOP|tx_data|Selector168~0_combout ;wire \A_SPW_TOP|tx_data|mem[18][7]~q ;wire \A_SPW_TOP|tx_data|Selector159~0_combout ;wire \A_SPW_TOP|tx_data|mem[17][7]~q ;wire \A_SPW_TOP|tx_data|Selector177~0_combout ;wire \A_SPW_TOP|tx_data|mem[19][7]~q ;wire \A_SPW_TOP|tx_data|Selector150~0_combout ;wire \A_SPW_TOP|tx_data|mem[16][7]~q ;wire \A_SPW_TOP|tx_data|Mux1~5_combout ;wire \A_SPW_TOP|tx_data|Selector537~0_combout ;wire \A_SPW_TOP|tx_data|mem[59][7]~q ;wire \A_SPW_TOP|tx_data|Selector528~0_combout ;wire \A_SPW_TOP|tx_data|mem[58][7]~q ;wire \A_SPW_TOP|tx_data|Selector519~0_combout ;wire \A_SPW_TOP|tx_data|mem[57][7]~q ;wire \A_SPW_TOP|tx_data|Selector510~0_combout ;wire \A_SPW_TOP|tx_data|mem[56][7]~q ;wire \A_SPW_TOP|tx_data|Mux1~8_combout ;wire \A_SPW_TOP|tx_data|Mux1~9_combout ;wire \A_SPW_TOP|tx_data|Selector195~0_combout ;wire \A_SPW_TOP|tx_data|mem[21][7]~q ;wire \A_SPW_TOP|tx_data|Selector213~0_combout ;wire \A_SPW_TOP|tx_data|mem[23][7]~q ;wire \A_SPW_TOP|tx_data|Selector501~0_combout ;wire \A_SPW_TOP|tx_data|mem[55][7]~q ;wire \A_SPW_TOP|tx_data|Selector483~0_combout ;wire \A_SPW_TOP|tx_data|mem[53][7]~q ;wire \A_SPW_TOP|tx_data|Mux1~17_combout ;wire \A_SPW_TOP|tx_data|Selector186~0_combout ;wire \A_SPW_TOP|tx_data|mem[20][7]~q ;wire \A_SPW_TOP|tx_data|Selector204~0_combout ;wire \A_SPW_TOP|tx_data|mem[22][7]~q ;wire \A_SPW_TOP|tx_data|Selector492~0_combout ;wire \A_SPW_TOP|tx_data|mem[54][7]~q ;wire \A_SPW_TOP|tx_data|Selector474~0_combout ;wire \A_SPW_TOP|tx_data|mem[52][7]~q ;wire \A_SPW_TOP|tx_data|Mux1~15_combout ;wire \A_SPW_TOP|tx_data|Selector258~0_combout ;wire \A_SPW_TOP|tx_data|mem[28][7]~q ;wire \A_SPW_TOP|tx_data|Selector564~0_combout ;wire \A_SPW_TOP|tx_data|mem[62][7]~q ;wire \A_SPW_TOP|tx_data|Selector276~0_combout ;wire \A_SPW_TOP|tx_data|mem[30][7]~q ;wire \A_SPW_TOP|tx_data|Selector546~0_combout ;wire \A_SPW_TOP|tx_data|mem[60][7]~q ;wire \A_SPW_TOP|tx_data|Mux1~16_combout ;wire \A_SPW_TOP|tx_data|Selector285~0_combout ;wire \A_SPW_TOP|tx_data|mem[31][7]~q ;wire \A_SPW_TOP|tx_data|Selector555~0_combout ;wire \A_SPW_TOP|tx_data|mem[61][7]~q ;wire \A_SPW_TOP|tx_data|Selector573~0_combout ;wire \A_SPW_TOP|tx_data|mem[63][7]~q ;wire \A_SPW_TOP|tx_data|Selector267~0_combout ;wire \A_SPW_TOP|tx_data|mem[29][7]~q ;wire \A_SPW_TOP|tx_data|Mux1~18_combout ;wire \A_SPW_TOP|tx_data|Mux1~19_combout ;wire \A_SPW_TOP|tx_data|Selector114~0_combout ;wire \A_SPW_TOP|tx_data|mem[12][7]~q ;wire \A_SPW_TOP|tx_data|Selector132~0_combout ;wire \A_SPW_TOP|tx_data|mem[14][7]~q ;wire \A_SPW_TOP|tx_data|Selector123~0_combout ;wire \A_SPW_TOP|tx_data|mem[13][7]~q ;wire \A_SPW_TOP|tx_data|Selector141~0_combout ;wire \A_SPW_TOP|tx_data|mem[15][7]~q ;wire \A_SPW_TOP|tx_data|Mux1~11_combout ;wire \A_SPW_TOP|tx_data|Selector69~0_combout ;wire \A_SPW_TOP|tx_data|mem[7][7]~q ;wire \A_SPW_TOP|tx_data|Selector60~0_combout ;wire \A_SPW_TOP|tx_data|mem[6][7]~q ;wire \A_SPW_TOP|tx_data|Selector51~0_combout ;wire \A_SPW_TOP|tx_data|mem[5][7]~q ;wire \A_SPW_TOP|tx_data|Selector42~0_combout ;wire \A_SPW_TOP|tx_data|mem[4][7]~q ;wire \A_SPW_TOP|tx_data|Mux1~10_combout ;wire \A_SPW_TOP|tx_data|Selector348~0_combout ;wire \A_SPW_TOP|tx_data|mem[38][7]~q ;wire \A_SPW_TOP|tx_data|Selector330~0_combout ;wire \A_SPW_TOP|tx_data|mem[36][7]~q ;wire \A_SPW_TOP|tx_data|Selector357~0_combout ;wire \A_SPW_TOP|tx_data|mem[39][7]~q ;wire \A_SPW_TOP|tx_data|Selector339~0_combout ;wire \A_SPW_TOP|tx_data|mem[37][7]~q ;wire \A_SPW_TOP|tx_data|Mux1~12_combout ;wire \A_SPW_TOP|tx_data|Selector402~0_combout ;wire \A_SPW_TOP|tx_data|mem[44][7]~q ;wire \A_SPW_TOP|tx_data|Selector420~0_combout ;wire \A_SPW_TOP|tx_data|mem[46][7]~q ;wire \A_SPW_TOP|tx_data|Selector429~0_combout ;wire \A_SPW_TOP|tx_data|mem[47][7]~q ;wire \A_SPW_TOP|tx_data|Selector411~0_combout ;wire \A_SPW_TOP|tx_data|mem[45][7]~q ;wire \A_SPW_TOP|tx_data|Mux1~13_combout ;wire \A_SPW_TOP|tx_data|Mux1~14_combout ;wire \A_SPW_TOP|tx_data|Selector24~0_combout ;wire \A_SPW_TOP|tx_data|mem[2][7]~q ;wire \A_SPW_TOP|tx_data|Selector33~0_combout ;wire \A_SPW_TOP|tx_data|mem[3][7]~q ;wire \A_SPW_TOP|tx_data|Selector15~0_combout ;wire \A_SPW_TOP|tx_data|mem[1][7]~q ;wire \A_SPW_TOP|tx_data|Mux1~0_combout ;wire \A_SPW_TOP|tx_data|Selector384~0_combout ;wire \A_SPW_TOP|tx_data|mem[42][7]~q ;wire \A_SPW_TOP|tx_data|Selector366~0_combout ;wire \A_SPW_TOP|tx_data|mem[40][7]~q ;wire \A_SPW_TOP|tx_data|Selector375~0_combout ;wire \A_SPW_TOP|tx_data|mem[41][7]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[41][7]~q ;wire \A_SPW_TOP|tx_data|Selector393~0_combout ;wire \A_SPW_TOP|tx_data|mem[43][7]~q ;wire \A_SPW_TOP|tx_data|Mux1~3_combout ;wire \A_SPW_TOP|tx_data|Selector78~0_combout ;wire \A_SPW_TOP|tx_data|mem[8][7]~q ;wire \A_SPW_TOP|tx_data|Selector105~0_combout ;wire \A_SPW_TOP|tx_data|mem[11][7]~q ;wire \A_SPW_TOP|tx_data|Selector87~0_combout ;wire \A_SPW_TOP|tx_data|mem[9][7]~q ;wire \A_SPW_TOP|tx_data|Selector96~0_combout ;wire \A_SPW_TOP|tx_data|mem[10][7]~q ;wire \A_SPW_TOP|tx_data|Mux1~1_combout ;wire \A_SPW_TOP|tx_data|Selector294~0_combout ;wire \A_SPW_TOP|tx_data|mem[32][7]~q ;wire \A_SPW_TOP|tx_data|Selector303~0_combout ;wire \A_SPW_TOP|tx_data|mem[33][7]~q ;wire \A_SPW_TOP|tx_data|Selector321~0_combout ;wire \A_SPW_TOP|tx_data|mem[35][7]~q ;wire \A_SPW_TOP|tx_data|Selector312~0_combout ;wire \A_SPW_TOP|tx_data|mem[34][7]~q ;wire \A_SPW_TOP|tx_data|Mux1~2_combout ;wire \A_SPW_TOP|tx_data|Mux1~4_combout ;wire \A_SPW_TOP|tx_data|Mux1~20_combout ;wire \A_SPW_TOP|tx_data|Selector6~0_combout ;wire \A_SPW_TOP|tx_data|mem[0][7]~q ;wire \A_SPW_TOP|tx_data|Mux10~0_combout ;wire \A_SPW_TOP|tx_data|Mux10~3_combout ;wire \A_SPW_TOP|tx_data|Mux10~2_combout ;wire \A_SPW_TOP|tx_data|Mux10~1_combout ;wire \A_SPW_TOP|tx_data|Mux10~4_combout ;wire \A_SPW_TOP|tx_data|Mux10~18_combout ;wire \A_SPW_TOP|tx_data|Mux10~17_combout ;wire \A_SPW_TOP|tx_data|Mux10~15_combout ;wire \A_SPW_TOP|tx_data|Mux10~16_combout ;wire \A_SPW_TOP|tx_data|Mux10~19_combout ;wire \A_SPW_TOP|tx_data|Mux10~6_combout ;wire \A_SPW_TOP|tx_data|Mux10~8_combout ;wire \A_SPW_TOP|tx_data|Mux10~5_combout ;wire \A_SPW_TOP|tx_data|Mux10~7_combout ;wire \A_SPW_TOP|tx_data|Mux10~9_combout ;wire \A_SPW_TOP|tx_data|Mux10~13_combout ;wire \A_SPW_TOP|tx_data|Mux10~12_combout ;wire \A_SPW_TOP|tx_data|Mux10~10_combout ;wire \A_SPW_TOP|tx_data|Mux10~11_combout ;wire \A_SPW_TOP|tx_data|Mux10~14_combout ;wire \A_SPW_TOP|tx_data|Mux10~20_combout ;wire \A_SPW_TOP|SPW|TX|Selector33~0_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~38_combout ;wire \A_SPW_TOP|tx_data|Selector520~0_combout ;wire \A_SPW_TOP|tx_data|mem[57][6]~q ;wire \A_SPW_TOP|tx_data|Selector376~0_combout ;wire \A_SPW_TOP|tx_data|mem[41][6]~q ;wire \A_SPW_TOP|tx_data|Selector394~0_combout ;wire \A_SPW_TOP|tx_data|mem[43][6]~q ;wire \A_SPW_TOP|tx_data|Selector538~0_combout ;wire \A_SPW_TOP|tx_data|mem[59][6]~q ;wire \A_SPW_TOP|tx_data|Mux2~16_combout ;wire \A_SPW_TOP|tx_data|Selector547~0_combout ;wire \A_SPW_TOP|tx_data|mem[60][6]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[60][6]~q ;wire \A_SPW_TOP|tx_data|Selector403~0_combout ;wire \A_SPW_TOP|tx_data|mem[44][6]~q ;wire \A_SPW_TOP|tx_data|Selector421~0_combout ;wire \A_SPW_TOP|tx_data|mem[46][6]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[46][6]~q ;wire \A_SPW_TOP|tx_data|Selector565~0_combout ;wire \A_SPW_TOP|tx_data|mem[62][6]~q ;wire \A_SPW_TOP|tx_data|Mux2~17_combout ;wire \A_SPW_TOP|tx_data|Selector385~0_combout ;wire \A_SPW_TOP|tx_data|mem[42][6]~q ;wire \A_SPW_TOP|tx_data|Selector367~0_combout ;wire \A_SPW_TOP|tx_data|mem[40][6]~q ;wire \A_SPW_TOP|tx_data|Selector529~0_combout ;wire \A_SPW_TOP|tx_data|mem[58][6]~q ;wire \A_SPW_TOP|tx_data|Selector511~0_combout ;wire \A_SPW_TOP|tx_data|mem[56][6]~q ;wire \A_SPW_TOP|tx_data|Mux2~15_combout ;wire \A_SPW_TOP|tx_data|Selector430~0_combout ;wire \A_SPW_TOP|tx_data|mem[47][6]~q ;wire \A_SPW_TOP|tx_data|Selector556~0_combout ;wire \A_SPW_TOP|tx_data|mem[61][6]~q ;wire \A_SPW_TOP|tx_data|Selector412~0_combout ;wire \A_SPW_TOP|tx_data|mem[45][6]~q ;wire \A_SPW_TOP|tx_data|Selector574~0_combout ;wire \A_SPW_TOP|tx_data|mem[63][6]~q ;wire \A_SPW_TOP|tx_data|Mux2~18_combout ;wire \A_SPW_TOP|tx_data|Mux2~19_combout ;wire \A_SPW_TOP|tx_data|Selector448~0_combout ;wire \A_SPW_TOP|tx_data|mem[49][6]~q ;wire \A_SPW_TOP|tx_data|Selector304~0_combout ;wire \A_SPW_TOP|tx_data|mem[33][6]~q ;wire \A_SPW_TOP|tx_data|Selector340~0_combout ;wire \A_SPW_TOP|tx_data|mem[37][6]~q ;wire \A_SPW_TOP|tx_data|Selector484~0_combout ;wire \A_SPW_TOP|tx_data|mem[53][6]~q ;wire \A_SPW_TOP|tx_data|Mux2~11_combout ;wire \A_SPW_TOP|tx_data|Selector322~0_combout ;wire \A_SPW_TOP|tx_data|mem[35][6]~q ;wire \A_SPW_TOP|tx_data|Selector358~0_combout ;wire \A_SPW_TOP|tx_data|mem[39][6]~q ;wire \A_SPW_TOP|tx_data|Selector466~0_combout ;wire \A_SPW_TOP|tx_data|mem[51][6]~q ;wire \A_SPW_TOP|tx_data|Selector502~0_combout ;wire \A_SPW_TOP|tx_data|mem[55][6]~q ;wire \A_SPW_TOP|tx_data|Mux2~13_combout ;wire \A_SPW_TOP|tx_data|Selector457~0_combout ;wire \A_SPW_TOP|tx_data|mem[50][6]~q ;wire \A_SPW_TOP|tx_data|Selector313~0_combout ;wire \A_SPW_TOP|tx_data|mem[34][6]~q ;wire \A_SPW_TOP|tx_data|Selector349~0_combout ;wire \A_SPW_TOP|tx_data|mem[38][6]~q ;wire \A_SPW_TOP|tx_data|Selector493~0_combout ;wire \A_SPW_TOP|tx_data|mem[54][6]~q ;wire \A_SPW_TOP|tx_data|Mux2~12_combout ;wire \A_SPW_TOP|tx_data|Selector295~0_combout ;wire \A_SPW_TOP|tx_data|mem[32][6]~q ;wire \A_SPW_TOP|tx_data|Selector439~0_combout ;wire \A_SPW_TOP|tx_data|mem[48][6]~q ;wire \A_SPW_TOP|tx_data|Selector331~0_combout ;wire \A_SPW_TOP|tx_data|mem[36][6]~q ;wire \A_SPW_TOP|tx_data|Selector475~0_combout ;wire \A_SPW_TOP|tx_data|mem[52][6]~q ;wire \A_SPW_TOP|tx_data|Mux2~10_combout ;wire \A_SPW_TOP|tx_data|Mux2~14_combout ;wire \A_SPW_TOP|tx_data|Selector196~0_combout ;wire \A_SPW_TOP|tx_data|mem[21][6]~q ;wire \A_SPW_TOP|tx_data|Selector52~0_combout ;wire \A_SPW_TOP|tx_data|mem[5][6]~q ;wire \A_SPW_TOP|tx_data|Selector160~0_combout ;wire \A_SPW_TOP|tx_data|mem[17][6]~q ;wire \A_SPW_TOP|tx_data|Selector16~0_combout ;wire \A_SPW_TOP|tx_data|mem[1][6]~q ;wire \A_SPW_TOP|tx_data|Mux2~1_combout ;wire \A_SPW_TOP|tx_data|Selector205~0_combout ;wire \A_SPW_TOP|tx_data|mem[22][6]~q ;wire \A_SPW_TOP|tx_data|Selector25~0_combout ;wire \A_SPW_TOP|tx_data|mem[2][6]~q ;wire \A_SPW_TOP|tx_data|Selector169~0_combout ;wire \A_SPW_TOP|tx_data|mem[18][6]~q ;wire \A_SPW_TOP|tx_data|Mux2~2_combout ;wire \A_SPW_TOP|tx_data|Selector34~0_combout ;wire \A_SPW_TOP|tx_data|mem[3][6]~q ;wire \A_SPW_TOP|tx_data|Selector70~0_combout ;wire \A_SPW_TOP|tx_data|mem[7][6]~q ;wire \A_SPW_TOP|tx_data|Selector214~0_combout ;wire \A_SPW_TOP|tx_data|mem[23][6]~q ;wire \A_SPW_TOP|tx_data|Selector178~0_combout ;wire \A_SPW_TOP|tx_data|mem[19][6]~q ;wire \A_SPW_TOP|tx_data|Mux2~3_combout ;wire \A_SPW_TOP|tx_data|Selector43~0_combout ;wire \A_SPW_TOP|tx_data|mem[4][6]~q ;wire \A_SPW_TOP|tx_data|Selector187~0_combout ;wire \A_SPW_TOP|tx_data|mem[20][6]~q ;wire \A_SPW_TOP|tx_data|Selector151~0_combout ;wire \A_SPW_TOP|tx_data|mem[16][6]~q ;wire \A_SPW_TOP|tx_data|Selector7~0_combout ;wire \A_SPW_TOP|tx_data|mem[0][6]~q ;wire \A_SPW_TOP|tx_data|Mux2~0_combout ;wire \A_SPW_TOP|tx_data|Mux2~4_combout ;wire \A_SPW_TOP|tx_data|Selector106~0_combout ;wire \A_SPW_TOP|tx_data|mem[11][6]~q ;wire \A_SPW_TOP|tx_data|Selector97~0_combout ;wire \A_SPW_TOP|tx_data|mem[10][6]~q ;wire \A_SPW_TOP|tx_data|Selector142~0_combout ;wire \A_SPW_TOP|tx_data|mem[15][6]~q ;wire \A_SPW_TOP|tx_data|Selector133~0_combout ;wire \A_SPW_TOP|tx_data|mem[14][6]~q ;wire \A_SPW_TOP|tx_data|Mux2~7_combout ;wire \A_SPW_TOP|tx_data|Selector88~0_combout ;wire \A_SPW_TOP|tx_data|mem[9][6]~q ;wire \A_SPW_TOP|tx_data|Selector115~0_combout ;wire \A_SPW_TOP|tx_data|mem[12][6]~q ;wire \A_SPW_TOP|tx_data|Selector79~0_combout ;wire \A_SPW_TOP|tx_data|mem[8][6]~q ;wire \A_SPW_TOP|tx_data|Selector124~0_combout ;wire \A_SPW_TOP|tx_data|mem[13][6]~q ;wire \A_SPW_TOP|tx_data|Mux2~5_combout ;wire \A_SPW_TOP|tx_data|Selector277~0_combout ;wire \A_SPW_TOP|tx_data|mem[30][6]~q ;wire \A_SPW_TOP|tx_data|Selector250~0_combout ;wire \A_SPW_TOP|tx_data|mem[27][6]~q ;wire \A_SPW_TOP|tx_data|Selector286~0_combout ;wire \A_SPW_TOP|tx_data|mem[31][6]~q ;wire \A_SPW_TOP|tx_data|Selector241~0_combout ;wire \A_SPW_TOP|tx_data|mem[26][6]~q ;wire \A_SPW_TOP|tx_data|Mux2~8_combout ;wire \A_SPW_TOP|tx_data|Selector232~0_combout ;wire \A_SPW_TOP|tx_data|mem[25][6]~q ;wire \A_SPW_TOP|tx_data|Selector259~0_combout ;wire \A_SPW_TOP|tx_data|mem[28][6]~q ;wire \A_SPW_TOP|tx_data|Selector268~0_combout ;wire \A_SPW_TOP|tx_data|mem[29][6]~q ;wire \A_SPW_TOP|tx_data|Selector223~0_combout ;wire \A_SPW_TOP|tx_data|mem[24][6]~q ;wire \A_SPW_TOP|tx_data|Mux2~6_combout ;wire \A_SPW_TOP|tx_data|Mux2~9_combout ;wire \A_SPW_TOP|tx_data|Mux2~20_combout ;wire \A_SPW_TOP|tx_data|Selector61~0_combout ;wire \A_SPW_TOP|tx_data|mem[6][6]~q ;wire \A_SPW_TOP|tx_data|Mux11~0_combout ;wire \A_SPW_TOP|tx_data|Mux11~1_combout ;wire \A_SPW_TOP|tx_data|Mux11~3_combout ;wire \A_SPW_TOP|tx_data|Mux11~2_combout ;wire \A_SPW_TOP|tx_data|Mux11~4_combout ;wire \A_SPW_TOP|tx_data|Mux11~6_combout ;wire \A_SPW_TOP|tx_data|Mux11~8_combout ;wire \A_SPW_TOP|tx_data|Mux11~7_combout ;wire \A_SPW_TOP|tx_data|Mux11~5_combout ;wire \A_SPW_TOP|tx_data|Mux11~9_combout ;wire \A_SPW_TOP|tx_data|Mux11~11_combout ;wire \A_SPW_TOP|tx_data|Mux11~13_combout ;wire \A_SPW_TOP|tx_data|Mux11~12_combout ;wire \A_SPW_TOP|tx_data|Mux11~10_combout ;wire \A_SPW_TOP|tx_data|Mux11~14_combout ;wire \A_SPW_TOP|tx_data|Mux11~17_combout ;wire \A_SPW_TOP|tx_data|Mux11~18_combout ;wire \A_SPW_TOP|tx_data|Mux11~15_combout ;wire \A_SPW_TOP|tx_data|Mux11~16_combout ;wire \A_SPW_TOP|tx_data|Mux11~19_combout ;wire \A_SPW_TOP|tx_data|Mux11~20_combout ;wire \A_SPW_TOP|SPW|TX|Selector34~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~5_combout ;wire \A_SPW_TOP|tx_data|Selector242~0_combout ;wire \A_SPW_TOP|tx_data|mem[26][5]~q ;wire \A_SPW_TOP|tx_data|Selector170~0_combout ;wire \A_SPW_TOP|tx_data|mem[18][5]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[18][5]~q ;wire \A_SPW_TOP|tx_data|Selector458~0_combout ;wire \A_SPW_TOP|tx_data|mem[50][5]~q ;wire \A_SPW_TOP|tx_data|Selector530~0_combout ;wire \A_SPW_TOP|tx_data|mem[58][5]~q ;wire \A_SPW_TOP|tx_data|Mux3~12_combout ;wire \A_SPW_TOP|tx_data|Selector26~0_combout ;wire \A_SPW_TOP|tx_data|mem[2][5]~q ;wire \A_SPW_TOP|tx_data|Selector314~0_combout ;wire \A_SPW_TOP|tx_data|mem[34][5]~q ;wire \A_SPW_TOP|tx_data|Selector386~0_combout ;wire \A_SPW_TOP|tx_data|mem[42][5]~q ;wire \A_SPW_TOP|tx_data|Selector98~0_combout ;wire \A_SPW_TOP|tx_data|mem[10][5]~q ;wire \A_SPW_TOP|tx_data|Mux3~10_combout ;wire \A_SPW_TOP|tx_data|Selector278~0_combout ;wire \A_SPW_TOP|tx_data|mem[30][5]~q ;wire \A_SPW_TOP|tx_data|Selector566~0_combout ;wire \A_SPW_TOP|tx_data|mem[62][5]~q ;wire \A_SPW_TOP|tx_data|Selector494~0_combout ;wire \A_SPW_TOP|tx_data|mem[54][5]~q ;wire \A_SPW_TOP|tx_data|Selector206~0_combout ;wire \A_SPW_TOP|tx_data|mem[22][5]~q ;wire \A_SPW_TOP|tx_data|Mux3~13_combout ;wire \A_SPW_TOP|tx_data|Selector350~0_combout ;wire \A_SPW_TOP|tx_data|mem[38][5]~q ;wire \A_SPW_TOP|tx_data|Selector62~0_combout ;wire \A_SPW_TOP|tx_data|mem[6][5]~q ;wire \A_SPW_TOP|tx_data|Selector422~0_combout ;wire \A_SPW_TOP|tx_data|mem[46][5]~q ;wire \A_SPW_TOP|tx_data|Selector134~0_combout ;wire \A_SPW_TOP|tx_data|mem[14][5]~q ;wire \A_SPW_TOP|tx_data|Mux3~11_combout ;wire \A_SPW_TOP|tx_data|Mux3~14_combout ;wire \A_SPW_TOP|tx_data|Selector8~0_combout ;wire \A_SPW_TOP|tx_data|mem[0][5]~q ;wire \A_SPW_TOP|tx_data|Selector296~0_combout ;wire \A_SPW_TOP|tx_data|mem[32][5]~q ;wire \A_SPW_TOP|tx_data|Selector80~0_combout ;wire \A_SPW_TOP|tx_data|mem[8][5]~q ;wire \A_SPW_TOP|tx_data|Selector368~0_combout ;wire \A_SPW_TOP|tx_data|mem[40][5]~q ;wire \A_SPW_TOP|tx_data|Mux3~0_combout ;wire \A_SPW_TOP|tx_data|Selector116~0_combout ;wire \A_SPW_TOP|tx_data|mem[12][5]~q ;wire \A_SPW_TOP|tx_data|Selector404~0_combout ;wire \A_SPW_TOP|tx_data|mem[44][5]~q ;wire \A_SPW_TOP|tx_data|Selector44~0_combout ;wire \A_SPW_TOP|tx_data|mem[4][5]~q ;wire \A_SPW_TOP|tx_data|Selector332~0_combout ;wire \A_SPW_TOP|tx_data|mem[36][5]~q ;wire \A_SPW_TOP|tx_data|Mux3~1_combout ;wire \A_SPW_TOP|tx_data|Selector440~0_combout ;wire \A_SPW_TOP|tx_data|mem[48][5]~q ;wire \A_SPW_TOP|tx_data|Selector224~0_combout ;wire \A_SPW_TOP|tx_data|mem[24][5]~q ;wire \A_SPW_TOP|tx_data|Selector152~0_combout ;wire \A_SPW_TOP|tx_data|mem[16][5]~q ;wire \A_SPW_TOP|tx_data|Selector512~0_combout ;wire \A_SPW_TOP|tx_data|mem[56][5]~q ;wire \A_SPW_TOP|tx_data|Mux3~2_combout ;wire \A_SPW_TOP|tx_data|Selector476~0_combout ;wire \A_SPW_TOP|tx_data|mem[52][5]~q ;wire \A_SPW_TOP|tx_data|Selector260~0_combout ;wire \A_SPW_TOP|tx_data|mem[28][5]~q ;wire \A_SPW_TOP|tx_data|Selector188~0_combout ;wire \A_SPW_TOP|tx_data|mem[20][5]~q ;wire \A_SPW_TOP|tx_data|Mux3~3_combout ;wire \A_SPW_TOP|tx_data|Mux3~4_combout ;wire \A_SPW_TOP|tx_data|Selector449~0_combout ;wire \A_SPW_TOP|tx_data|mem[49][5]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[49][5]~q ;wire \A_SPW_TOP|tx_data|Selector521~0_combout ;wire \A_SPW_TOP|tx_data|mem[57][5]~q ;wire \A_SPW_TOP|tx_data|Selector161~0_combout ;wire \A_SPW_TOP|tx_data|mem[17][5]~q ;wire \A_SPW_TOP|tx_data|Selector233~0_combout ;wire \A_SPW_TOP|tx_data|mem[25][5]~q ;wire \A_SPW_TOP|tx_data|Mux3~7_combout ;wire \A_SPW_TOP|tx_data|Selector53~0_combout ;wire \A_SPW_TOP|tx_data|mem[5][5]~q ;wire \A_SPW_TOP|tx_data|Selector125~0_combout ;wire \A_SPW_TOP|tx_data|mem[13][5]~q ;wire \A_SPW_TOP|tx_data|Selector413~0_combout ;wire \A_SPW_TOP|tx_data|mem[45][5]~q ;wire \A_SPW_TOP|tx_data|Selector341~0_combout ;wire \A_SPW_TOP|tx_data|mem[37][5]~q ;wire \A_SPW_TOP|tx_data|Mux3~6_combout ;wire \A_SPW_TOP|tx_data|Selector305~0_combout ;wire \A_SPW_TOP|tx_data|mem[33][5]~q ;wire \A_SPW_TOP|tx_data|Selector89~0_combout ;wire \A_SPW_TOP|tx_data|mem[9][5]~q ;wire \A_SPW_TOP|tx_data|Selector377~0_combout ;wire \A_SPW_TOP|tx_data|mem[41][5]~q ;wire \A_SPW_TOP|tx_data|Selector17~0_combout ;wire \A_SPW_TOP|tx_data|mem[1][5]~q ;wire \A_SPW_TOP|tx_data|Mux3~5_combout ;wire \A_SPW_TOP|tx_data|Selector197~0_combout ;wire \A_SPW_TOP|tx_data|mem[21][5]~q ;wire \A_SPW_TOP|tx_data|Selector269~0_combout ;wire \A_SPW_TOP|tx_data|mem[29][5]~q ;wire \A_SPW_TOP|tx_data|Selector485~0_combout ;wire \A_SPW_TOP|tx_data|mem[53][5]~q ;wire \A_SPW_TOP|tx_data|Selector557~0_combout ;wire \A_SPW_TOP|tx_data|mem[61][5]~q ;wire \A_SPW_TOP|tx_data|Mux3~8_combout ;wire \A_SPW_TOP|tx_data|Mux3~9_combout ;wire \A_SPW_TOP|tx_data|Selector575~0_combout ;wire \A_SPW_TOP|tx_data|mem[63][5]~q ;wire \A_SPW_TOP|tx_data|Selector539~0_combout ;wire \A_SPW_TOP|tx_data|mem[59][5]~q ;wire \A_SPW_TOP|tx_data|Selector467~0_combout ;wire \A_SPW_TOP|tx_data|mem[51][5]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[51][5]~q ;wire \A_SPW_TOP|tx_data|Selector503~0_combout ;wire \A_SPW_TOP|tx_data|mem[55][5]~q ;wire \A_SPW_TOP|tx_data|Mux3~18_combout ;wire \A_SPW_TOP|tx_data|Selector431~0_combout ;wire \A_SPW_TOP|tx_data|mem[47][5]~q ;wire \A_SPW_TOP|tx_data|Selector359~0_combout ;wire \A_SPW_TOP|tx_data|mem[39][5]~q ;wire \A_SPW_TOP|tx_data|Selector323~0_combout ;wire \A_SPW_TOP|tx_data|mem[35][5]~q ;wire \A_SPW_TOP|tx_data|Selector395~0_combout ;wire \A_SPW_TOP|tx_data|mem[43][5]~q ;wire \A_SPW_TOP|tx_data|Mux3~16_combout ;wire \A_SPW_TOP|tx_data|Selector35~0_combout ;wire \A_SPW_TOP|tx_data|mem[3][5]~q ;wire \A_SPW_TOP|tx_data|Selector107~0_combout ;wire \A_SPW_TOP|tx_data|mem[11][5]~q ;wire \A_SPW_TOP|tx_data|Selector143~0_combout ;wire \A_SPW_TOP|tx_data|mem[15][5]~q ;wire \A_SPW_TOP|tx_data|Selector71~0_combout ;wire \A_SPW_TOP|tx_data|mem[7][5]~q ;wire \A_SPW_TOP|tx_data|Mux3~15_combout ;wire \A_SPW_TOP|tx_data|Selector215~0_combout ;wire \A_SPW_TOP|tx_data|mem[23][5]~q ;wire \A_SPW_TOP|tx_data|Selector251~0_combout ;wire \A_SPW_TOP|tx_data|mem[27][5]~q ;wire \A_SPW_TOP|tx_data|Selector287~0_combout ;wire \A_SPW_TOP|tx_data|mem[31][5]~q ;wire \A_SPW_TOP|tx_data|Selector179~0_combout ;wire \A_SPW_TOP|tx_data|mem[19][5]~q ;wire \A_SPW_TOP|tx_data|Mux3~17_combout ;wire \A_SPW_TOP|tx_data|Mux3~19_combout ;wire \A_SPW_TOP|tx_data|Mux3~20_combout ;wire \A_SPW_TOP|tx_data|Selector548~0_combout ;wire \A_SPW_TOP|tx_data|mem[60][5]~q ;wire \A_SPW_TOP|tx_data|Mux12~6_combout ;wire \A_SPW_TOP|tx_data|Mux12~7_combout ;wire \A_SPW_TOP|tx_data|Mux12~5_combout ;wire \A_SPW_TOP|tx_data|Mux12~8_combout ;wire \A_SPW_TOP|tx_data|Mux12~9_combout ;wire \A_SPW_TOP|tx_data|Mux12~17_combout ;wire \A_SPW_TOP|tx_data|Mux12~16_combout ;wire \A_SPW_TOP|tx_data|Mux12~18_combout ;wire \A_SPW_TOP|tx_data|Mux12~15_combout ;wire \A_SPW_TOP|tx_data|Mux12~19_combout ;wire \A_SPW_TOP|tx_data|Mux12~13_combout ;wire \A_SPW_TOP|tx_data|Mux12~11_combout ;wire \A_SPW_TOP|tx_data|Mux12~12_combout ;wire \A_SPW_TOP|tx_data|Mux12~10_combout ;wire \A_SPW_TOP|tx_data|Mux12~14_combout ;wire \A_SPW_TOP|tx_data|Mux12~2_combout ;wire \A_SPW_TOP|tx_data|Mux12~3_combout ;wire \A_SPW_TOP|tx_data|Mux12~1_combout ;wire \A_SPW_TOP|tx_data|Mux12~0_combout ;wire \A_SPW_TOP|tx_data|Mux12~4_combout ;wire \A_SPW_TOP|tx_data|Mux12~20_combout ;wire \A_SPW_TOP|SPW|TX|Selector35~0_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~17_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~4_combout ;wire \u0|write_data_fifo_tx|data_out[4]~feeder_combout ;wire \A_SPW_TOP|tx_data|Selector306~0_combout ;wire \A_SPW_TOP|tx_data|mem[33][4]~q ;wire \A_SPW_TOP|tx_data|Selector315~0_combout ;wire \A_SPW_TOP|tx_data|mem[34][4]~q ;wire \A_SPW_TOP|tx_data|Selector324~0_combout ;wire \A_SPW_TOP|tx_data|mem[35][4]~q ;wire \A_SPW_TOP|tx_data|Selector297~0_combout ;wire \A_SPW_TOP|tx_data|mem[32][4]~q ;wire \A_SPW_TOP|tx_data|Mux4~2_combout ;wire \A_SPW_TOP|tx_data|Selector90~0_combout ;wire \A_SPW_TOP|tx_data|mem[9][4]~q ;wire \A_SPW_TOP|tx_data|Selector81~0_combout ;wire \A_SPW_TOP|tx_data|mem[8][4]~q ;wire \A_SPW_TOP|tx_data|Selector108~0_combout ;wire \A_SPW_TOP|tx_data|mem[11][4]~q ;wire \A_SPW_TOP|tx_data|Selector99~0_combout ;wire \A_SPW_TOP|tx_data|mem[10][4]~q ;wire \A_SPW_TOP|tx_data|Mux4~1_combout ;wire \A_SPW_TOP|tx_data|Selector27~0_combout ;wire \A_SPW_TOP|tx_data|mem[2][4]~q ;wire \A_SPW_TOP|tx_data|Selector18~0_combout ;wire \A_SPW_TOP|tx_data|mem[1][4]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[1][4]~q ;wire \A_SPW_TOP|tx_data|Selector36~0_combout ;wire \A_SPW_TOP|tx_data|mem[3][4]~q ;wire \A_SPW_TOP|tx_data|Mux4~0_combout ;wire \A_SPW_TOP|tx_data|Selector387~0_combout ;wire \A_SPW_TOP|tx_data|mem[42][4]~q ;wire \A_SPW_TOP|tx_data|Selector369~0_combout ;wire \A_SPW_TOP|tx_data|mem[40][4]~q ;wire \A_SPW_TOP|tx_data|Selector378~0_combout ;wire \A_SPW_TOP|tx_data|mem[41][4]~q ;wire \A_SPW_TOP|tx_data|Selector396~0_combout ;wire \A_SPW_TOP|tx_data|mem[43][4]~q ;wire \A_SPW_TOP|tx_data|Mux4~3_combout ;wire \A_SPW_TOP|tx_data|Mux4~4_combout ;wire \A_SPW_TOP|tx_data|Selector360~0_combout ;wire \A_SPW_TOP|tx_data|mem[39][4]~q ;wire \A_SPW_TOP|tx_data|Selector351~0_combout ;wire \A_SPW_TOP|tx_data|mem[38][4]~q ;wire \A_SPW_TOP|tx_data|Selector333~0_combout ;wire \A_SPW_TOP|tx_data|mem[36][4]~q ;wire \A_SPW_TOP|tx_data|Selector342~0_combout ;wire \A_SPW_TOP|tx_data|mem[37][4]~q ;wire \A_SPW_TOP|tx_data|Mux4~12_combout ;wire \A_SPW_TOP|tx_data|Selector63~0_combout ;wire \A_SPW_TOP|tx_data|mem[6][4]~q ;wire \A_SPW_TOP|tx_data|Selector45~0_combout ;wire \A_SPW_TOP|tx_data|mem[4][4]~q ;wire \A_SPW_TOP|tx_data|Selector72~0_combout ;wire \A_SPW_TOP|tx_data|mem[7][4]~q ;wire \A_SPW_TOP|tx_data|Selector54~0_combout ;wire \A_SPW_TOP|tx_data|mem[5][4]~q ;wire \A_SPW_TOP|tx_data|Mux4~10_combout ;wire \A_SPW_TOP|tx_data|Selector405~0_combout ;wire \A_SPW_TOP|tx_data|mem[44][4]~q ;wire \A_SPW_TOP|tx_data|Selector414~0_combout ;wire \A_SPW_TOP|tx_data|mem[45][4]~q ;wire \A_SPW_TOP|tx_data|Selector432~0_combout ;wire \A_SPW_TOP|tx_data|mem[47][4]~q ;wire \A_SPW_TOP|tx_data|Selector423~0_combout ;wire \A_SPW_TOP|tx_data|mem[46][4]~q ;wire \A_SPW_TOP|tx_data|Mux4~13_combout ;wire \A_SPW_TOP|tx_data|Selector144~0_combout ;wire \A_SPW_TOP|tx_data|mem[15][4]~q ;wire \A_SPW_TOP|tx_data|Selector117~0_combout ;wire \A_SPW_TOP|tx_data|mem[12][4]~q ;wire \A_SPW_TOP|tx_data|Selector135~0_combout ;wire \A_SPW_TOP|tx_data|mem[14][4]~q ;wire \A_SPW_TOP|tx_data|Selector126~0_combout ;wire \A_SPW_TOP|tx_data|mem[13][4]~q ;wire \A_SPW_TOP|tx_data|Mux4~11_combout ;wire \A_SPW_TOP|tx_data|Mux4~14_combout ;wire \A_SPW_TOP|tx_data|Selector171~0_combout ;wire \A_SPW_TOP|tx_data|mem[18][4]~q ;wire \A_SPW_TOP|tx_data|Selector162~0_combout ;wire \A_SPW_TOP|tx_data|mem[17][4]~q ;wire \A_SPW_TOP|tx_data|Selector180~0_combout ;wire \A_SPW_TOP|tx_data|mem[19][4]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[19][4]~q ;wire \A_SPW_TOP|tx_data|Selector153~0_combout ;wire \A_SPW_TOP|tx_data|mem[16][4]~q ;wire \A_SPW_TOP|tx_data|Mux4~5_combout ;wire \A_SPW_TOP|tx_data|Selector234~0_combout ;wire \A_SPW_TOP|tx_data|mem[25][4]~q ;wire \A_SPW_TOP|tx_data|Selector252~0_combout ;wire \A_SPW_TOP|tx_data|mem[27][4]~q ;wire \A_SPW_TOP|tx_data|Selector243~0_combout ;wire \A_SPW_TOP|tx_data|mem[26][4]~q ;wire \A_SPW_TOP|tx_data|Selector225~0_combout ;wire \A_SPW_TOP|tx_data|mem[24][4]~q ;wire \A_SPW_TOP|tx_data|Mux4~6_combout ;wire \A_SPW_TOP|tx_data|Selector459~0_combout ;wire \A_SPW_TOP|tx_data|mem[50][4]~q ;wire \A_SPW_TOP|tx_data|Selector468~0_combout ;wire \A_SPW_TOP|tx_data|mem[51][4]~q ;wire \A_SPW_TOP|tx_data|Selector441~0_combout ;wire \A_SPW_TOP|tx_data|mem[48][4]~q ;wire \A_SPW_TOP|tx_data|Selector450~0_combout ;wire \A_SPW_TOP|tx_data|mem[49][4]~q ;wire \A_SPW_TOP|tx_data|Mux4~7_combout ;wire \A_SPW_TOP|tx_data|Selector531~0_combout ;wire \A_SPW_TOP|tx_data|mem[58][4]~q ;wire \A_SPW_TOP|tx_data|Selector522~0_combout ;wire \A_SPW_TOP|tx_data|mem[57][4]~q ;wire \A_SPW_TOP|tx_data|Selector540~0_combout ;wire \A_SPW_TOP|tx_data|mem[59][4]~q ;wire \A_SPW_TOP|tx_data|Selector513~0_combout ;wire \A_SPW_TOP|tx_data|mem[56][4]~q ;wire \A_SPW_TOP|tx_data|Mux4~8_combout ;wire \A_SPW_TOP|tx_data|Mux4~9_combout ;wire \A_SPW_TOP|tx_data|Selector189~0_combout ;wire \A_SPW_TOP|tx_data|mem[20][4]~q ;wire \A_SPW_TOP|tx_data|Selector486~0_combout ;wire \A_SPW_TOP|tx_data|mem[53][4]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[53][4]~q ;wire \A_SPW_TOP|tx_data|Selector477~0_combout ;wire \A_SPW_TOP|tx_data|mem[52][4]~q ;wire \A_SPW_TOP|tx_data|Selector198~0_combout ;wire \A_SPW_TOP|tx_data|mem[21][4]~q ;wire \A_SPW_TOP|tx_data|Mux4~15_combout ;wire \A_SPW_TOP|tx_data|Selector216~0_combout ;wire \A_SPW_TOP|tx_data|mem[23][4]~q ;wire \A_SPW_TOP|tx_data|Selector495~0_combout ;wire \A_SPW_TOP|tx_data|mem[54][4]~q ;wire \A_SPW_TOP|tx_data|Selector504~0_combout ;wire \A_SPW_TOP|tx_data|mem[55][4]~q ;wire \A_SPW_TOP|tx_data|Selector207~0_combout ;wire \A_SPW_TOP|tx_data|mem[22][4]~q ;wire \A_SPW_TOP|tx_data|Mux4~17_combout ;wire \A_SPW_TOP|tx_data|Selector558~0_combout ;wire \A_SPW_TOP|tx_data|mem[61][4]~q ;wire \A_SPW_TOP|tx_data|Selector549~0_combout ;wire \A_SPW_TOP|tx_data|mem[60][4]~q ;wire \A_SPW_TOP|tx_data|Selector270~0_combout ;wire \A_SPW_TOP|tx_data|mem[29][4]~q ;wire \A_SPW_TOP|tx_data|Selector261~0_combout ;wire \A_SPW_TOP|tx_data|mem[28][4]~q ;wire \A_SPW_TOP|tx_data|Mux4~16_combout ;wire \A_SPW_TOP|tx_data|Selector576~0_combout ;wire \A_SPW_TOP|tx_data|mem[63][4]~q ;wire \A_SPW_TOP|tx_data|Selector288~0_combout ;wire \A_SPW_TOP|tx_data|mem[31][4]~q ;wire \A_SPW_TOP|tx_data|Selector279~0_combout ;wire \A_SPW_TOP|tx_data|mem[30][4]~q ;wire \A_SPW_TOP|tx_data|Selector567~0_combout ;wire \A_SPW_TOP|tx_data|mem[62][4]~q ;wire \A_SPW_TOP|tx_data|Mux4~18_combout ;wire \A_SPW_TOP|tx_data|Mux4~19_combout ;wire \A_SPW_TOP|tx_data|Mux4~20_combout ;wire \A_SPW_TOP|tx_data|Selector9~0_combout ;wire \A_SPW_TOP|tx_data|mem[0][4]~q ;wire \A_SPW_TOP|tx_data|Mux13~0_combout ;wire \A_SPW_TOP|tx_data|Mux13~3_combout ;wire \A_SPW_TOP|tx_data|Mux13~2_combout ;wire \A_SPW_TOP|tx_data|Mux13~1_combout ;wire \A_SPW_TOP|tx_data|Mux13~4_combout ;wire \A_SPW_TOP|tx_data|Mux13~10_combout ;wire \A_SPW_TOP|tx_data|Mux13~13_combout ;wire \A_SPW_TOP|tx_data|Mux13~12_combout ;wire \A_SPW_TOP|tx_data|Mux13~11_combout ;wire \A_SPW_TOP|tx_data|Mux13~14_combout ;wire \A_SPW_TOP|tx_data|Mux13~18_combout ;wire \A_SPW_TOP|tx_data|Mux13~17_combout ;wire \A_SPW_TOP|tx_data|Mux13~15_combout ;wire \A_SPW_TOP|tx_data|Mux13~16_combout ;wire \A_SPW_TOP|tx_data|Mux13~19_combout ;wire \A_SPW_TOP|tx_data|Mux13~5_combout ;wire \A_SPW_TOP|tx_data|Mux13~7_combout ;wire \A_SPW_TOP|tx_data|Mux13~8_combout ;wire \A_SPW_TOP|tx_data|Mux13~6_combout ;wire \A_SPW_TOP|tx_data|Mux13~9_combout ;wire \A_SPW_TOP|tx_data|Mux13~20_combout ;wire \A_SPW_TOP|SPW|TX|Selector36~0_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~14_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~20_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~6_combout ;wire \A_SPW_TOP|SPW|TX|Selector74~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector25~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector75~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector26~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector76~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector27~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector77~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector24~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector74~1_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~4_combout ;wire \A_SPW_TOP|SPW|TX|Selector28~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector78~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector29~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector79~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector81~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector80~0_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~5_combout ;wire \A_SPW_TOP|SPW|TX|Selector50~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|timecode_tx_data|always0~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector49~0_combout ;wire \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~3_combout ;wire \A_SPW_TOP|SPW|TX|Selector47~0_combout ;wire \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~2_combout ;wire \A_SPW_TOP|SPW|TX|Selector48~0_combout ;wire \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector50~2_combout ;wire \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~3_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~7_combout ;wire \A_SPW_TOP|SPW|TX|Selector43~0_combout ;wire \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~4_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~6_combout ;wire \A_SPW_TOP|SPW|TX|Selector44~0_combout ;wire \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~5_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~5_combout ;wire \A_SPW_TOP|SPW|TX|Selector45~0_combout ;wire \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~6_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~4_combout ;wire \A_SPW_TOP|SPW|TX|Selector46~0_combout ;wire \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~7_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~7_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~8_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~22_combout ;wire \A_SPW_TOP|SPW|TX|Selector0~2_combout ;wire \A_SPW_TOP|SPW|TX|Selector0~3_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~24_combout ;wire \A_SPW_TOP|SPW|TX|Selector0~4_combout ;wire \A_SPW_TOP|SPW|TX|Selector0~1_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~25_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~26_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~27_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~28_combout ;wire \A_SPW_TOP|SPW|TX|Selector0~5_combout ;wire \A_SPW_TOP|SPW|TX|timecode_s~2_combout ;wire \A_SPW_TOP|SPW|TX|timecode_s~1_combout ;wire \A_SPW_TOP|SPW|TX|timecode_s~0_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~10_combout ;wire \A_SPW_TOP|SPW|TX|timecode_s~8_combout ;wire \A_SPW_TOP|SPW|TX|timecode_s~7_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~12_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~9_combout ;wire \A_SPW_TOP|SPW|TX|timecode_s~5_combout ;wire \A_SPW_TOP|SPW|TX|timecode_s~3_combout ;wire \A_SPW_TOP|SPW|TX|timecode_s~6_combout ;wire \A_SPW_TOP|SPW|TX|timecode_s~4_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~11_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~13_combout ;wire \A_SPW_TOP|SPW|TX|Selector0~0_combout ;wire \A_SPW_TOP|SPW|TX|always0~12_combout ;wire \A_SPW_TOP|SPW|TX|always0~13_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~36_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~35_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~32_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~41_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~42_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~30_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~29_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~33_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~40_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~31_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~34_combout ;wire \A_SPW_TOP|SPW|TX|Selector0~9_combout ;wire \A_SPW_TOP|SPW|TX|Selector0~11_combout ;wire \A_SPW_TOP|SPW|TX|Selector0~10_combout ;wire \A_SPW_TOP|SPW|TX|Selector0~12_combout ;wire \A_SPW_TOP|SPW|TX|Selector0~7_combout ;wire \A_SPW_TOP|SPW|TX|Selector0~8_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~37_combout ;wire \A_SPW_TOP|SPW|TX|Selector0~13_combout ;wire \A_SPW_TOP|SPW|TX|Selector0~6_combout ;wire \A_SPW_TOP|SPW|TX|Selector0~14_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~q ;wire \A_SPW_TOP|SPW|TX|tx_dout_e~q ;wire \m_x|always3~0_combout ;wire \m_x|control_r[0]~feeder_combout ;wire \m_x|control~0_combout ;wire \m_x|control_l_r~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][10]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][10]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~30_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~12_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][9]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~29_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~10 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~6 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~1_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][8]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][8]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][8]~q ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~15_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~16_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~14_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~17_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~18_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~13_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~12_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \A_SPW_TOP|SPW|RX|dta_timec_p[8]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|rx_data_flag~8_combout ;wire \A_SPW_TOP|rx_data|wr_ptr[0]~0_combout ;wire \A_SPW_TOP|rx_data|Add1~2_combout ;wire \A_SPW_TOP|rx_data|Add1~1_combout ;wire \A_SPW_TOP|rx_data|Add1~3_combout ;wire \A_SPW_TOP|rx_data|Add1~0_combout ;wire \A_SPW_TOP|rx_data|Add1~4_combout ;wire \A_SPW_TOP|rx_data|Decoder0~52_combout ;wire \A_SPW_TOP|rx_data|Selector244~0_combout ;wire \A_SPW_TOP|rx_data|Decoder0~44_combout ;wire \A_SPW_TOP|rx_data|Selector145~0_combout ;wire \A_SPW_TOP|rx_data|Selector145~1_combout ;wire \A_SPW_TOP|rx_data|mem[14][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~51_combout ;wire \A_SPW_TOP|rx_data|Selector289~0_combout ;wire \A_SPW_TOP|rx_data|Selector289~1_combout ;wire \A_SPW_TOP|rx_data|mem[30][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~28_combout ;wire \A_SPW_TOP|rx_data|Selector217~0_combout ;wire \A_SPW_TOP|rx_data|Selector217~1_combout ;wire \A_SPW_TOP|rx_data|mem[22][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~12_combout ;wire \A_SPW_TOP|rx_data|Selector73~0_combout ;wire \A_SPW_TOP|rx_data|Selector73~1_combout ;wire \A_SPW_TOP|rx_data|mem[6][8]~q ;wire \A_SPW_TOP|rx_data|Mux0~7_combout ;wire \A_SPW_TOP|rx_data|Decoder0~49_combout ;wire \A_SPW_TOP|rx_data|Selector253~0_combout ;wire \A_SPW_TOP|rx_data|Selector253~1_combout ;wire \A_SPW_TOP|rx_data|mem[26][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~24_combout ;wire \A_SPW_TOP|rx_data|Selector181~0_combout ;wire \A_SPW_TOP|rx_data|Selector181~1_combout ;wire \A_SPW_TOP|rx_data|mem[18][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~40_combout ;wire \A_SPW_TOP|rx_data|Selector109~0_combout ;wire \A_SPW_TOP|rx_data|Selector109~1_combout ;wire \A_SPW_TOP|rx_data|mem[10][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~8_combout ;wire \A_SPW_TOP|rx_data|Selector37~0_combout ;wire \A_SPW_TOP|rx_data|Selector37~1_combout ;wire \A_SPW_TOP|rx_data|mem[2][8]~q ;wire \A_SPW_TOP|rx_data|Mux0~5_combout ;wire \A_SPW_TOP|rx_data|Decoder0~10_combout ;wire \A_SPW_TOP|rx_data|Selector325~0_combout ;wire \A_SPW_TOP|rx_data|Selector325~1_combout ;wire \A_SPW_TOP|rx_data|mem[34][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~42_combout ;wire \A_SPW_TOP|rx_data|Selector397~0_combout ;wire \A_SPW_TOP|rx_data|Selector397~1_combout ;wire \A_SPW_TOP|rx_data|mem[42][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~26_combout ;wire \A_SPW_TOP|rx_data|Selector469~0_combout ;wire \A_SPW_TOP|rx_data|Selector469~1_combout ;wire \A_SPW_TOP|rx_data|mem[50][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~57_combout ;wire \A_SPW_TOP|rx_data|Selector541~0_combout ;wire \A_SPW_TOP|rx_data|Selector541~1_combout ;wire \A_SPW_TOP|rx_data|mem[58][8]~q ;wire \A_SPW_TOP|rx_data|Mux0~6_combout ;wire \A_SPW_TOP|rx_data|Decoder0~46_combout ;wire \A_SPW_TOP|rx_data|Selector433~0_combout ;wire \A_SPW_TOP|rx_data|Selector433~1_combout ;wire \A_SPW_TOP|rx_data|mem[46][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~14_combout ;wire \A_SPW_TOP|rx_data|Selector361~0_combout ;wire \A_SPW_TOP|rx_data|Selector361~1_combout ;wire \A_SPW_TOP|rx_data|mem[38][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~30_combout ;wire \A_SPW_TOP|rx_data|Selector505~0_combout ;wire \A_SPW_TOP|rx_data|Selector505~1_combout ;wire \A_SPW_TOP|rx_data|mem[54][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~59_combout ;wire \A_SPW_TOP|rx_data|Selector577~0_combout ;wire \A_SPW_TOP|rx_data|Selector577~1_combout ;wire \A_SPW_TOP|rx_data|mem[62][8]~q ;wire \A_SPW_TOP|rx_data|Mux0~8_combout ;wire \A_SPW_TOP|rx_data|Mux0~9_combout ;wire \A_SPW_TOP|rx_data|Decoder0~19_combout ;wire \A_SPW_TOP|rx_data|Selector460~0_combout ;wire \A_SPW_TOP|rx_data|Selector460~1_combout ;wire \A_SPW_TOP|rx_data|mem[49][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~21_combout ;wire \A_SPW_TOP|rx_data|Selector208~0_combout ;wire \A_SPW_TOP|rx_data|Selector208~1_combout ;wire \A_SPW_TOP|rx_data|mem[21][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~23_combout ;wire \A_SPW_TOP|rx_data|Selector496~0_combout ;wire \A_SPW_TOP|rx_data|Selector496~1_combout ;wire \A_SPW_TOP|rx_data|mem[53][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~17_combout ;wire \A_SPW_TOP|rx_data|Selector172~0_combout ;wire \A_SPW_TOP|rx_data|Selector172~1_combout ;wire \A_SPW_TOP|rx_data|mem[17][8]~q ;wire \A_SPW_TOP|rx_data|Mux0~12_combout ;wire \A_SPW_TOP|rx_data|Decoder0~60_combout ;wire \A_SPW_TOP|rx_data|Selector532~0_combout ;wire \A_SPW_TOP|rx_data|Selector532~1_combout ;wire \A_SPW_TOP|rx_data|mem[57][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~62_combout ;wire \A_SPW_TOP|rx_data|Selector568~0_combout ;wire \A_SPW_TOP|rx_data|Selector568~1_combout ;wire \A_SPW_TOP|rx_data|mem[61][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~54_combout ;wire \A_SPW_TOP|rx_data|Selector280~0_combout ;wire \A_SPW_TOP|rx_data|Selector280~1_combout ;wire \A_SPW_TOP|rx_data|mem[29][8]~q ;wire \A_SPW_TOP|rx_data|Mux0~13_combout ;wire \A_SPW_TOP|rx_data|Decoder0~37_combout ;wire \A_SPW_TOP|rx_data|Selector136~0_combout ;wire \A_SPW_TOP|rx_data|Selector136~1_combout ;wire \A_SPW_TOP|rx_data|mem[13][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~39_combout ;wire \A_SPW_TOP|rx_data|Selector424~0_combout ;wire \A_SPW_TOP|rx_data|Selector424~1_combout ;wire \A_SPW_TOP|rx_data|mem[45][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~33_combout ;wire \A_SPW_TOP|rx_data|Selector100~0_combout ;wire \A_SPW_TOP|rx_data|Selector100~1_combout ;wire \A_SPW_TOP|rx_data|mem[9][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~35_combout ;wire \A_SPW_TOP|rx_data|Selector388~0_combout ;wire \A_SPW_TOP|rx_data|Selector388~1_combout ;wire \A_SPW_TOP|rx_data|mem[41][8]~q ;wire \A_SPW_TOP|rx_data|Mux0~11_combout ;wire \A_SPW_TOP|rx_data|Decoder0~1_combout ;wire \A_SPW_TOP|rx_data|Selector28~0_combout ;wire \A_SPW_TOP|rx_data|Selector28~1_combout ;wire \A_SPW_TOP|rx_data|mem[1][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~3_combout ;wire \A_SPW_TOP|rx_data|Selector316~0_combout ;wire \A_SPW_TOP|rx_data|Selector316~1_combout ;wire \A_SPW_TOP|rx_data|mem[33][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~7_combout ;wire \A_SPW_TOP|rx_data|Selector352~0_combout ;wire \A_SPW_TOP|rx_data|Selector352~1_combout ;wire \A_SPW_TOP|rx_data|mem[37][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~5_combout ;wire \A_SPW_TOP|rx_data|Selector64~0_combout ;wire \A_SPW_TOP|rx_data|Selector64~1_combout ;wire \A_SPW_TOP|rx_data|mem[5][8]~q ;wire \A_SPW_TOP|rx_data|Mux0~10_combout ;wire \A_SPW_TOP|rx_data|Mux0~14_combout ;wire \A_SPW_TOP|rx_data|Decoder0~56_combout ;wire \A_SPW_TOP|rx_data|Selector523~0_combout ;wire \A_SPW_TOP|rx_data|Selector523~1_combout ;wire \A_SPW_TOP|rx_data|mem[56][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~50_combout ;wire \A_SPW_TOP|rx_data|Selector271~0_combout ;wire \A_SPW_TOP|rx_data|Selector271~1_combout ;wire \A_SPW_TOP|rx_data|mem[28][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~48_combout ;wire \A_SPW_TOP|rx_data|Selector235~0_combout ;wire \A_SPW_TOP|rx_data|Selector235~1_combout ;wire \A_SPW_TOP|rx_data|mem[24][8]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[24][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~58_combout ;wire \A_SPW_TOP|rx_data|Selector559~0_combout ;wire \A_SPW_TOP|rx_data|Selector559~1_combout ;wire \A_SPW_TOP|rx_data|mem[60][8]~q ;wire \A_SPW_TOP|rx_data|Mux0~3_combout ;wire \A_SPW_TOP|rx_data|Decoder0~20_combout ;wire \A_SPW_TOP|rx_data|Selector199~0_combout ;wire \A_SPW_TOP|rx_data|Selector199~1_combout ;wire \A_SPW_TOP|rx_data|mem[20][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~18_combout ;wire \A_SPW_TOP|rx_data|Selector451~0_combout ;wire \A_SPW_TOP|rx_data|Selector451~1_combout ;wire \A_SPW_TOP|rx_data|mem[48][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~16_combout ;wire \A_SPW_TOP|rx_data|Selector163~0_combout ;wire \A_SPW_TOP|rx_data|Selector163~1_combout ;wire \A_SPW_TOP|rx_data|mem[16][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~22_combout ;wire \A_SPW_TOP|rx_data|Selector487~0_combout ;wire \A_SPW_TOP|rx_data|Selector487~1_combout ;wire \A_SPW_TOP|rx_data|mem[52][8]~q ;wire \A_SPW_TOP|rx_data|Mux0~2_combout ;wire \A_SPW_TOP|rx_data|Decoder0~0_combout ;wire \A_SPW_TOP|rx_data|Selector19~0_combout ;wire \A_SPW_TOP|rx_data|Selector19~1_combout ;wire \A_SPW_TOP|rx_data|mem[0][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~6_combout ;wire \A_SPW_TOP|rx_data|Selector343~0_combout ;wire \A_SPW_TOP|rx_data|Selector343~1_combout ;wire \A_SPW_TOP|rx_data|mem[36][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~4_combout ;wire \A_SPW_TOP|rx_data|Selector55~0_combout ;wire \A_SPW_TOP|rx_data|Selector55~1_combout ;wire \A_SPW_TOP|rx_data|mem[4][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~2_combout ;wire \A_SPW_TOP|rx_data|Selector307~0_combout ;wire \A_SPW_TOP|rx_data|Selector307~1_combout ;wire \A_SPW_TOP|rx_data|mem[32][8]~q ;wire \A_SPW_TOP|rx_data|Mux0~0_combout ;wire \A_SPW_TOP|rx_data|Decoder0~32_combout ;wire \A_SPW_TOP|rx_data|Selector91~0_combout ;wire \A_SPW_TOP|rx_data|Selector91~1_combout ;wire \A_SPW_TOP|rx_data|mem[8][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~34_combout ;wire \A_SPW_TOP|rx_data|Selector379~0_combout ;wire \A_SPW_TOP|rx_data|Selector379~1_combout ;wire \A_SPW_TOP|rx_data|mem[40][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~36_combout ;wire \A_SPW_TOP|rx_data|Selector127~0_combout ;wire \A_SPW_TOP|rx_data|Selector127~1_combout ;wire \A_SPW_TOP|rx_data|mem[12][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~38_combout ;wire \A_SPW_TOP|rx_data|Selector415~0_combout ;wire \A_SPW_TOP|rx_data|Selector415~1_combout ;wire \A_SPW_TOP|rx_data|mem[44][8]~q ;wire \A_SPW_TOP|rx_data|Mux0~1_combout ;wire \A_SPW_TOP|rx_data|Mux0~4_combout ;wire \A_SPW_TOP|rx_data|Decoder0~47_combout ;wire \A_SPW_TOP|rx_data|Selector442~0_combout ;wire \A_SPW_TOP|rx_data|Selector442~1_combout ;wire \A_SPW_TOP|rx_data|mem[47][8]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[47][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~63_combout ;wire \A_SPW_TOP|rx_data|Selector586~0_combout ;wire \A_SPW_TOP|rx_data|Selector586~1_combout ;wire \A_SPW_TOP|rx_data|mem[63][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~31_combout ;wire \A_SPW_TOP|rx_data|Selector514~0_combout ;wire \A_SPW_TOP|rx_data|Selector514~1_combout ;wire \A_SPW_TOP|rx_data|mem[55][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~15_combout ;wire \A_SPW_TOP|rx_data|Selector370~0_combout ;wire \A_SPW_TOP|rx_data|Selector370~1_combout ;wire \A_SPW_TOP|rx_data|mem[39][8]~q ;wire \A_SPW_TOP|rx_data|Mux0~18_combout ;wire \A_SPW_TOP|rx_data|Decoder0~29_combout ;wire \A_SPW_TOP|rx_data|Selector226~0_combout ;wire \A_SPW_TOP|rx_data|Selector226~1_combout ;wire \A_SPW_TOP|rx_data|mem[23][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~55_combout ;wire \A_SPW_TOP|rx_data|Selector298~0_combout ;wire \A_SPW_TOP|rx_data|Selector298~1_combout ;wire \A_SPW_TOP|rx_data|mem[31][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~45_combout ;wire \A_SPW_TOP|rx_data|Selector154~0_combout ;wire \A_SPW_TOP|rx_data|Selector154~1_combout ;wire \A_SPW_TOP|rx_data|mem[15][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~13_combout ;wire \A_SPW_TOP|rx_data|Selector82~0_combout ;wire \A_SPW_TOP|rx_data|Selector82~1_combout ;wire \A_SPW_TOP|rx_data|mem[7][8]~q ;wire \A_SPW_TOP|rx_data|Mux0~17_combout ;wire \A_SPW_TOP|rx_data|Decoder0~9_combout ;wire \A_SPW_TOP|rx_data|Selector46~0_combout ;wire \A_SPW_TOP|rx_data|Selector46~1_combout ;wire \A_SPW_TOP|rx_data|mem[3][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~41_combout ;wire \A_SPW_TOP|rx_data|Selector118~0_combout ;wire \A_SPW_TOP|rx_data|Selector118~1_combout ;wire \A_SPW_TOP|rx_data|mem[11][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~53_combout ;wire \A_SPW_TOP|rx_data|Selector262~0_combout ;wire \A_SPW_TOP|rx_data|Selector262~1_combout ;wire \A_SPW_TOP|rx_data|mem[27][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~25_combout ;wire \A_SPW_TOP|rx_data|Selector190~0_combout ;wire \A_SPW_TOP|rx_data|Selector190~1_combout ;wire \A_SPW_TOP|rx_data|mem[19][8]~q ;wire \A_SPW_TOP|rx_data|Mux0~15_combout ;wire \A_SPW_TOP|rx_data|Decoder0~27_combout ;wire \A_SPW_TOP|rx_data|Selector478~0_combout ;wire \A_SPW_TOP|rx_data|Selector478~1_combout ;wire \A_SPW_TOP|rx_data|mem[51][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~61_combout ;wire \A_SPW_TOP|rx_data|Selector550~0_combout ;wire \A_SPW_TOP|rx_data|Selector550~1_combout ;wire \A_SPW_TOP|rx_data|mem[59][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~43_combout ;wire \A_SPW_TOP|rx_data|Selector406~0_combout ;wire \A_SPW_TOP|rx_data|Selector406~1_combout ;wire \A_SPW_TOP|rx_data|mem[43][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~11_combout ;wire \A_SPW_TOP|rx_data|Selector334~0_combout ;wire \A_SPW_TOP|rx_data|Selector334~1_combout ;wire \A_SPW_TOP|rx_data|mem[35][8]~q ;wire \A_SPW_TOP|rx_data|Mux0~16_combout ;wire \A_SPW_TOP|rx_data|Mux0~19_combout ;wire \A_SPW_TOP|rx_data|Mux0~20_combout ;wire \A_SPW_TOP|rx_data|Selector244~1_combout ;wire \A_SPW_TOP|rx_data|mem[25][8]~q ;wire \A_SPW_TOP|rx_data|Add9~10 ;wire \A_SPW_TOP|rx_data|Add9~21_sumout ;wire \A_SPW_TOP|rx_data|rd_ptr[3]~feeder_combout ;wire \A_SPW_TOP|rx_data|Add9~22 ;wire \A_SPW_TOP|rx_data|Add9~17_sumout ;wire \A_SPW_TOP|rx_data|Mux9~1_combout ;wire \A_SPW_TOP|rx_data|Mux9~3_combout ;wire \A_SPW_TOP|rx_data|Mux9~0_combout ;wire \A_SPW_TOP|rx_data|Add9~18 ;wire \A_SPW_TOP|rx_data|Add9~5_sumout ;wire \A_SPW_TOP|rx_data|rd_ptr[5]~feeder_combout ;wire \A_SPW_TOP|rx_data|Mux9~2_combout ;wire \A_SPW_TOP|rx_data|Mux9~4_combout ;wire \A_SPW_TOP|rx_data|Mux9~16_combout ;wire \A_SPW_TOP|rx_data|Mux9~17_combout ;wire \A_SPW_TOP|rx_data|Mux9~15_combout ;wire \A_SPW_TOP|rx_data|Mux9~18_combout ;wire \A_SPW_TOP|rx_data|Mux9~19_combout ;wire \A_SPW_TOP|rx_data|Mux9~11_combout ;wire \A_SPW_TOP|rx_data|Mux9~12_combout ;wire \A_SPW_TOP|rx_data|Mux9~13_combout ;wire \A_SPW_TOP|rx_data|Mux9~10_combout ;wire \A_SPW_TOP|rx_data|Mux9~14_combout ;wire \A_SPW_TOP|rx_data|Mux9~7_combout ;wire \A_SPW_TOP|rx_data|Mux9~5_combout ;wire \A_SPW_TOP|rx_data|Mux9~6_combout ;wire \A_SPW_TOP|rx_data|Mux9~8_combout ;wire \A_SPW_TOP|rx_data|Mux9~9_combout ;wire \A_SPW_TOP|rx_data|Mux9~20_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][8]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][8]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][8]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~83_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~84_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~85_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|LessThan18~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~5_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][7]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][7]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~79_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][7]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][7]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~80_combout ;wire \A_SPW_TOP|SPW|RX|rx_data_flag~0_combout ;wire \A_SPW_TOP|SPW|RX|rx_data_flag~7_combout ;wire \A_SPW_TOP|rx_data|Selector371~0_combout ;wire \A_SPW_TOP|rx_data|mem[39][7]~q ;wire \A_SPW_TOP|rx_data|Selector344~0_combout ;wire \A_SPW_TOP|rx_data|mem[36][7]~q ;wire \A_SPW_TOP|rx_data|Selector362~0_combout ;wire \A_SPW_TOP|rx_data|mem[38][7]~q ;wire \A_SPW_TOP|rx_data|Selector353~0_combout ;wire \A_SPW_TOP|rx_data|mem[37][7]~q ;wire \A_SPW_TOP|rx_data|Mux1~12_combout ;wire \A_SPW_TOP|rx_data|Selector65~0_combout ;wire \A_SPW_TOP|rx_data|mem[5][7]~q ;wire \A_SPW_TOP|rx_data|Selector56~0_combout ;wire \A_SPW_TOP|rx_data|mem[4][7]~q ;wire \A_SPW_TOP|rx_data|Selector83~0_combout ;wire \A_SPW_TOP|rx_data|mem[7][7]~q ;wire \A_SPW_TOP|rx_data|Selector74~0_combout ;wire \A_SPW_TOP|rx_data|mem[6][7]~q ;wire \A_SPW_TOP|rx_data|Mux1~10_combout ;wire \A_SPW_TOP|rx_data|Selector416~0_combout ;wire \A_SPW_TOP|rx_data|mem[44][7]~q ;wire \A_SPW_TOP|rx_data|Selector425~0_combout ;wire \A_SPW_TOP|rx_data|mem[45][7]~q ;wire \A_SPW_TOP|rx_data|Selector434~0_combout ;wire \A_SPW_TOP|rx_data|mem[46][7]~q ;wire \A_SPW_TOP|rx_data|Selector443~0_combout ;wire \A_SPW_TOP|rx_data|mem[47][7]~q ;wire \A_SPW_TOP|rx_data|Mux1~13_combout ;wire \A_SPW_TOP|rx_data|Selector146~0_combout ;wire \A_SPW_TOP|rx_data|mem[14][7]~q ;wire \A_SPW_TOP|rx_data|Selector137~0_combout ;wire \A_SPW_TOP|rx_data|mem[13][7]~q ;wire \A_SPW_TOP|rx_data|Selector128~0_combout ;wire \A_SPW_TOP|rx_data|mem[12][7]~q ;wire \A_SPW_TOP|rx_data|Selector155~0_combout ;wire \A_SPW_TOP|rx_data|mem[15][7]~q ;wire \A_SPW_TOP|rx_data|Mux1~11_combout ;wire \A_SPW_TOP|rx_data|Mux1~14_combout ;wire \A_SPW_TOP|rx_data|Selector533~0_combout ;wire \A_SPW_TOP|rx_data|mem[57][7]~q ;wire \A_SPW_TOP|rx_data|Selector551~0_combout ;wire \A_SPW_TOP|rx_data|mem[59][7]~q ;wire \A_SPW_TOP|rx_data|Selector542~0_combout ;wire \A_SPW_TOP|rx_data|mem[58][7]~q ;wire \A_SPW_TOP|rx_data|Selector524~0_combout ;wire \A_SPW_TOP|rx_data|mem[56][7]~q ;wire \A_SPW_TOP|rx_data|Mux1~8_combout ;wire \A_SPW_TOP|rx_data|Selector236~0_combout ;wire \A_SPW_TOP|rx_data|mem[24][7]~q ;wire \A_SPW_TOP|rx_data|Selector254~0_combout ;wire \A_SPW_TOP|rx_data|mem[26][7]~q ;wire \A_SPW_TOP|rx_data|Selector245~0_combout ;wire \A_SPW_TOP|rx_data|mem[25][7]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[25][7]~q ;wire \A_SPW_TOP|rx_data|Selector263~0_combout ;wire \A_SPW_TOP|rx_data|mem[27][7]~q ;wire \A_SPW_TOP|rx_data|Mux1~6_combout ;wire \A_SPW_TOP|rx_data|Selector164~0_combout ;wire \A_SPW_TOP|rx_data|mem[16][7]~q ;wire \A_SPW_TOP|rx_data|Selector182~0_combout ;wire \A_SPW_TOP|rx_data|mem[18][7]~q ;wire \A_SPW_TOP|rx_data|Selector173~0_combout ;wire \A_SPW_TOP|rx_data|mem[17][7]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[17][7]~q ;wire \A_SPW_TOP|rx_data|Selector191~0_combout ;wire \A_SPW_TOP|rx_data|mem[19][7]~q ;wire \A_SPW_TOP|rx_data|Mux1~5_combout ;wire \A_SPW_TOP|rx_data|Selector461~0_combout ;wire \A_SPW_TOP|rx_data|mem[49][7]~q ;wire \A_SPW_TOP|rx_data|Selector470~0_combout ;wire \A_SPW_TOP|rx_data|mem[50][7]~q ;wire \A_SPW_TOP|rx_data|Selector452~0_combout ;wire \A_SPW_TOP|rx_data|mem[48][7]~q ;wire \A_SPW_TOP|rx_data|Selector479~0_combout ;wire \A_SPW_TOP|rx_data|mem[51][7]~q ;wire \A_SPW_TOP|rx_data|Mux1~7_combout ;wire \A_SPW_TOP|rx_data|Mux1~9_combout ;wire \A_SPW_TOP|rx_data|Selector281~0_combout ;wire \A_SPW_TOP|rx_data|mem[29][7]~q ;wire \A_SPW_TOP|rx_data|Selector569~0_combout ;wire \A_SPW_TOP|rx_data|mem[61][7]~q ;wire \A_SPW_TOP|rx_data|Selector299~0_combout ;wire \A_SPW_TOP|rx_data|mem[31][7]~q ;wire \A_SPW_TOP|rx_data|Selector587~0_combout ;wire \A_SPW_TOP|rx_data|mem[63][7]~q ;wire \A_SPW_TOP|rx_data|Mux1~18_combout ;wire \A_SPW_TOP|rx_data|Selector209~0_combout ;wire \A_SPW_TOP|rx_data|mem[21][7]~q ;wire \A_SPW_TOP|rx_data|Selector227~0_combout ;wire \A_SPW_TOP|rx_data|mem[23][7]~q ;wire \A_SPW_TOP|rx_data|Selector497~0_combout ;wire \A_SPW_TOP|rx_data|mem[53][7]~q ;wire \A_SPW_TOP|rx_data|Mux1~17_combout ;wire \A_SPW_TOP|rx_data|Selector488~0_combout ;wire \A_SPW_TOP|rx_data|mem[52][7]~q ;wire \A_SPW_TOP|rx_data|Selector506~0_combout ;wire \A_SPW_TOP|rx_data|mem[54][7]~q ;wire \A_SPW_TOP|rx_data|Selector200~0_combout ;wire \A_SPW_TOP|rx_data|mem[20][7]~q ;wire \A_SPW_TOP|rx_data|Selector218~0_combout ;wire \A_SPW_TOP|rx_data|mem[22][7]~q ;wire \A_SPW_TOP|rx_data|Mux1~15_combout ;wire \A_SPW_TOP|rx_data|Selector578~0_combout ;wire \A_SPW_TOP|rx_data|mem[62][7]~q ;wire \A_SPW_TOP|rx_data|Selector272~0_combout ;wire \A_SPW_TOP|rx_data|mem[28][7]~q ;wire \A_SPW_TOP|rx_data|Selector290~0_combout ;wire \A_SPW_TOP|rx_data|mem[30][7]~q ;wire \A_SPW_TOP|rx_data|Selector560~0_combout ;wire \A_SPW_TOP|rx_data|mem[60][7]~q ;wire \A_SPW_TOP|rx_data|Mux1~16_combout ;wire \A_SPW_TOP|rx_data|Mux1~19_combout ;wire \A_SPW_TOP|rx_data|Selector398~0_combout ;wire \A_SPW_TOP|rx_data|mem[42][7]~q ;wire \A_SPW_TOP|rx_data|Selector380~0_combout ;wire \A_SPW_TOP|rx_data|mem[40][7]~q ;wire \A_SPW_TOP|rx_data|Selector407~0_combout ;wire \A_SPW_TOP|rx_data|mem[43][7]~q ;wire \A_SPW_TOP|rx_data|Selector389~0_combout ;wire \A_SPW_TOP|rx_data|mem[41][7]~q ;wire \A_SPW_TOP|rx_data|Mux1~3_combout ;wire \A_SPW_TOP|rx_data|Selector110~0_combout ;wire \A_SPW_TOP|rx_data|mem[10][7]~q ;wire \A_SPW_TOP|rx_data|Selector92~0_combout ;wire \A_SPW_TOP|rx_data|mem[8][7]~q ;wire \A_SPW_TOP|rx_data|Selector119~0_combout ;wire \A_SPW_TOP|rx_data|mem[11][7]~q ;wire \A_SPW_TOP|rx_data|Selector101~0_combout ;wire \A_SPW_TOP|rx_data|mem[9][7]~q ;wire \A_SPW_TOP|rx_data|Mux1~1_combout ;wire \A_SPW_TOP|rx_data|Selector47~0_combout ;wire \A_SPW_TOP|rx_data|mem[3][7]~q ;wire \A_SPW_TOP|rx_data|Selector38~0_combout ;wire \A_SPW_TOP|rx_data|mem[2][7]~q ;wire \A_SPW_TOP|rx_data|Selector20~0_combout ;wire \A_SPW_TOP|rx_data|mem[0][7]~q ;wire \A_SPW_TOP|rx_data|Selector29~0_combout ;wire \A_SPW_TOP|rx_data|mem[1][7]~q ;wire \A_SPW_TOP|rx_data|Mux1~0_combout ;wire \A_SPW_TOP|rx_data|Selector335~0_combout ;wire \A_SPW_TOP|rx_data|mem[35][7]~q ;wire \A_SPW_TOP|rx_data|Selector308~0_combout ;wire \A_SPW_TOP|rx_data|mem[32][7]~q ;wire \A_SPW_TOP|rx_data|Selector326~0_combout ;wire \A_SPW_TOP|rx_data|mem[34][7]~q ;wire \A_SPW_TOP|rx_data|Selector317~0_combout ;wire \A_SPW_TOP|rx_data|mem[33][7]~q ;wire \A_SPW_TOP|rx_data|Mux1~2_combout ;wire \A_SPW_TOP|rx_data|Mux1~4_combout ;wire \A_SPW_TOP|rx_data|Mux1~20_combout ;wire \A_SPW_TOP|rx_data|Selector515~0_combout ;wire \A_SPW_TOP|rx_data|mem[55][7]~q ;wire \A_SPW_TOP|rx_data|Mux10~16_combout ;wire \A_SPW_TOP|rx_data|Mux10~15_combout ;wire \A_SPW_TOP|rx_data|Mux10~17_combout ;wire \A_SPW_TOP|rx_data|Mux10~18_combout ;wire \A_SPW_TOP|rx_data|Mux10~19_combout ;wire \A_SPW_TOP|rx_data|Mux10~3_combout ;wire \A_SPW_TOP|rx_data|Mux10~2_combout ;wire \A_SPW_TOP|rx_data|Mux10~0_combout ;wire \A_SPW_TOP|rx_data|Mux10~1_combout ;wire \A_SPW_TOP|rx_data|Mux10~4_combout ;wire \A_SPW_TOP|rx_data|Mux10~8_combout ;wire \A_SPW_TOP|rx_data|Mux10~5_combout ;wire \A_SPW_TOP|rx_data|Mux10~7_combout ;wire \A_SPW_TOP|rx_data|Mux10~6_combout ;wire \A_SPW_TOP|rx_data|Mux10~9_combout ;wire \A_SPW_TOP|rx_data|Mux10~11_combout ;wire \A_SPW_TOP|rx_data|Mux10~12_combout ;wire \A_SPW_TOP|rx_data|Mux10~10_combout ;wire \A_SPW_TOP|rx_data|Mux10~13_combout ;wire \A_SPW_TOP|rx_data|Mux10~14_combout ;wire \A_SPW_TOP|rx_data|Mux10~20_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][7]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][7]~q ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~12_combout ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~14_combout ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~15_combout ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~16_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~13_combout ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~17_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~18_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \A_SPW_TOP|SPW|RX|timecode~0_combout ;wire \A_SPW_TOP|SPW|RX|timecode~8_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][7]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][7]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~81_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~82_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][7]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][7]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~206_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~6_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][6]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~75_combout ;wire \A_SPW_TOP|SPW|RX|rx_data_flag~6_combout ;wire \A_SPW_TOP|rx_data|Selector507~0_combout ;wire \A_SPW_TOP|rx_data|mem[54][6]~q ;wire \A_SPW_TOP|rx_data|Selector363~0_combout ;wire \A_SPW_TOP|rx_data|mem[38][6]~q ;wire \A_SPW_TOP|rx_data|Selector471~0_combout ;wire \A_SPW_TOP|rx_data|mem[50][6]~q ;wire \A_SPW_TOP|rx_data|Selector327~0_combout ;wire \A_SPW_TOP|rx_data|mem[34][6]~q ;wire \A_SPW_TOP|rx_data|Mux2~12_combout ;wire \A_SPW_TOP|rx_data|Selector309~0_combout ;wire \A_SPW_TOP|rx_data|mem[32][6]~q ;wire \A_SPW_TOP|rx_data|Selector345~0_combout ;wire \A_SPW_TOP|rx_data|mem[36][6]~q ;wire \A_SPW_TOP|rx_data|Selector489~0_combout ;wire \A_SPW_TOP|rx_data|mem[52][6]~q ;wire \A_SPW_TOP|rx_data|Selector453~0_combout ;wire \A_SPW_TOP|rx_data|mem[48][6]~q ;wire \A_SPW_TOP|rx_data|Mux2~10_combout ;wire \A_SPW_TOP|rx_data|Selector462~0_combout ;wire \A_SPW_TOP|rx_data|mem[49][6]~q ;wire \A_SPW_TOP|rx_data|Selector318~0_combout ;wire \A_SPW_TOP|rx_data|mem[33][6]~q ;wire \A_SPW_TOP|rx_data|Selector498~0_combout ;wire \A_SPW_TOP|rx_data|mem[53][6]~q ;wire \A_SPW_TOP|rx_data|Selector354~0_combout ;wire \A_SPW_TOP|rx_data|mem[37][6]~q ;wire \A_SPW_TOP|rx_data|Mux2~11_combout ;wire \A_SPW_TOP|rx_data|Selector336~0_combout ;wire \A_SPW_TOP|rx_data|mem[35][6]~q ;wire \A_SPW_TOP|rx_data|Selector480~0_combout ;wire \A_SPW_TOP|rx_data|mem[51][6]~q ;wire \A_SPW_TOP|rx_data|Selector372~0_combout ;wire \A_SPW_TOP|rx_data|mem[39][6]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[39][6]~q ;wire \A_SPW_TOP|rx_data|Selector516~0_combout ;wire \A_SPW_TOP|rx_data|mem[55][6]~q ;wire \A_SPW_TOP|rx_data|Mux2~13_combout ;wire \A_SPW_TOP|rx_data|Mux2~14_combout ;wire \A_SPW_TOP|rx_data|Selector111~0_combout ;wire \A_SPW_TOP|rx_data|mem[10][6]~q ;wire \A_SPW_TOP|rx_data|Selector156~0_combout ;wire \A_SPW_TOP|rx_data|mem[15][6]~q ;wire \A_SPW_TOP|rx_data|Selector120~0_combout ;wire \A_SPW_TOP|rx_data|mem[11][6]~q ;wire \A_SPW_TOP|rx_data|Selector147~0_combout ;wire \A_SPW_TOP|rx_data|mem[14][6]~q ;wire \A_SPW_TOP|rx_data|Mux2~7_combout ;wire \A_SPW_TOP|rx_data|Selector300~0_combout ;wire \A_SPW_TOP|rx_data|mem[31][6]~q ;wire \A_SPW_TOP|rx_data|Selector264~0_combout ;wire \A_SPW_TOP|rx_data|mem[27][6]~q ;wire \A_SPW_TOP|rx_data|Selector255~0_combout ;wire \A_SPW_TOP|rx_data|mem[26][6]~q ;wire \A_SPW_TOP|rx_data|Selector291~0_combout ;wire \A_SPW_TOP|rx_data|mem[30][6]~q ;wire \A_SPW_TOP|rx_data|Mux2~8_combout ;wire \A_SPW_TOP|rx_data|Selector273~0_combout ;wire \A_SPW_TOP|rx_data|mem[28][6]~q ;wire \A_SPW_TOP|rx_data|Selector237~0_combout ;wire \A_SPW_TOP|rx_data|mem[24][6]~q ;wire \A_SPW_TOP|rx_data|Selector246~0_combout ;wire \A_SPW_TOP|rx_data|mem[25][6]~q ;wire \A_SPW_TOP|rx_data|Mux2~6_combout ;wire \A_SPW_TOP|rx_data|Selector138~0_combout ;wire \A_SPW_TOP|rx_data|mem[13][6]~q ;wire \A_SPW_TOP|rx_data|Selector129~0_combout ;wire \A_SPW_TOP|rx_data|mem[12][6]~q ;wire \A_SPW_TOP|rx_data|Selector93~0_combout ;wire \A_SPW_TOP|rx_data|mem[8][6]~q ;wire \A_SPW_TOP|rx_data|Selector102~0_combout ;wire \A_SPW_TOP|rx_data|mem[9][6]~q ;wire \A_SPW_TOP|rx_data|Mux2~5_combout ;wire \A_SPW_TOP|rx_data|Mux2~9_combout ;wire \A_SPW_TOP|rx_data|Selector48~0_combout ;wire \A_SPW_TOP|rx_data|mem[3][6]~q ;wire \A_SPW_TOP|rx_data|Selector228~0_combout ;wire \A_SPW_TOP|rx_data|mem[23][6]~q ;wire \A_SPW_TOP|rx_data|Selector192~0_combout ;wire \A_SPW_TOP|rx_data|mem[19][6]~q ;wire \A_SPW_TOP|rx_data|Selector84~0_combout ;wire \A_SPW_TOP|rx_data|mem[7][6]~q ;wire \A_SPW_TOP|rx_data|Mux2~3_combout ;wire \A_SPW_TOP|rx_data|Selector66~0_combout ;wire \A_SPW_TOP|rx_data|mem[5][6]~q ;wire \A_SPW_TOP|rx_data|Selector30~0_combout ;wire \A_SPW_TOP|rx_data|mem[1][6]~q ;wire \A_SPW_TOP|rx_data|Selector210~0_combout ;wire \A_SPW_TOP|rx_data|mem[21][6]~q ;wire \A_SPW_TOP|rx_data|Selector174~0_combout ;wire \A_SPW_TOP|rx_data|mem[17][6]~q ;wire \A_SPW_TOP|rx_data|Mux2~1_combout ;wire \A_SPW_TOP|rx_data|Selector21~0_combout ;wire \A_SPW_TOP|rx_data|mem[0][6]~q ;wire \A_SPW_TOP|rx_data|Selector201~0_combout ;wire \A_SPW_TOP|rx_data|mem[20][6]~q ;wire \A_SPW_TOP|rx_data|Selector57~0_combout ;wire \A_SPW_TOP|rx_data|mem[4][6]~q ;wire \A_SPW_TOP|rx_data|Selector165~0_combout ;wire \A_SPW_TOP|rx_data|mem[16][6]~q ;wire \A_SPW_TOP|rx_data|Mux2~0_combout ;wire \A_SPW_TOP|rx_data|Selector75~0_combout ;wire \A_SPW_TOP|rx_data|mem[6][6]~q ;wire \A_SPW_TOP|rx_data|Selector219~0_combout ;wire \A_SPW_TOP|rx_data|mem[22][6]~q ;wire \A_SPW_TOP|rx_data|Selector39~0_combout ;wire \A_SPW_TOP|rx_data|mem[2][6]~q ;wire \A_SPW_TOP|rx_data|Selector183~0_combout ;wire \A_SPW_TOP|rx_data|mem[18][6]~q ;wire \A_SPW_TOP|rx_data|Mux2~2_combout ;wire \A_SPW_TOP|rx_data|Mux2~4_combout ;wire \A_SPW_TOP|rx_data|Selector525~0_combout ;wire \A_SPW_TOP|rx_data|mem[56][6]~q ;wire \A_SPW_TOP|rx_data|Selector381~0_combout ;wire \A_SPW_TOP|rx_data|mem[40][6]~q ;wire \A_SPW_TOP|rx_data|Selector399~0_combout ;wire \A_SPW_TOP|rx_data|mem[42][6]~q ;wire \A_SPW_TOP|rx_data|Selector543~0_combout ;wire \A_SPW_TOP|rx_data|mem[58][6]~q ;wire \A_SPW_TOP|rx_data|Mux2~15_combout ;wire \A_SPW_TOP|rx_data|Selector570~0_combout ;wire \A_SPW_TOP|rx_data|mem[61][6]~q ;wire \A_SPW_TOP|rx_data|Selector426~0_combout ;wire \A_SPW_TOP|rx_data|mem[45][6]~q ;wire \A_SPW_TOP|rx_data|Selector444~0_combout ;wire \A_SPW_TOP|rx_data|mem[47][6]~q ;wire \A_SPW_TOP|rx_data|Selector588~0_combout ;wire \A_SPW_TOP|rx_data|mem[63][6]~q ;wire \A_SPW_TOP|rx_data|Mux2~18_combout ;wire \A_SPW_TOP|rx_data|Selector390~0_combout ;wire \A_SPW_TOP|rx_data|mem[41][6]~q ;wire \A_SPW_TOP|rx_data|Selector408~0_combout ;wire \A_SPW_TOP|rx_data|mem[43][6]~q ;wire \A_SPW_TOP|rx_data|Selector534~0_combout ;wire \A_SPW_TOP|rx_data|mem[57][6]~q ;wire \A_SPW_TOP|rx_data|Selector552~0_combout ;wire \A_SPW_TOP|rx_data|mem[59][6]~q ;wire \A_SPW_TOP|rx_data|Mux2~16_combout ;wire \A_SPW_TOP|rx_data|Selector561~0_combout ;wire \A_SPW_TOP|rx_data|mem[60][6]~q ;wire \A_SPW_TOP|rx_data|Selector435~0_combout ;wire \A_SPW_TOP|rx_data|mem[46][6]~q ;wire \A_SPW_TOP|rx_data|Selector579~0_combout ;wire \A_SPW_TOP|rx_data|mem[62][6]~q ;wire \A_SPW_TOP|rx_data|Selector417~0_combout ;wire \A_SPW_TOP|rx_data|mem[44][6]~q ;wire \A_SPW_TOP|rx_data|Mux2~17_combout ;wire \A_SPW_TOP|rx_data|Mux2~19_combout ;wire \A_SPW_TOP|rx_data|Mux2~20_combout ;wire \A_SPW_TOP|rx_data|Selector282~0_combout ;wire \A_SPW_TOP|rx_data|mem[29][6]~q ;wire \A_SPW_TOP|rx_data|Mux11~15_combout ;wire \A_SPW_TOP|rx_data|Mux11~17_combout ;wire \A_SPW_TOP|rx_data|Mux11~16_combout ;wire \A_SPW_TOP|rx_data|Mux11~18_combout ;wire \A_SPW_TOP|rx_data|Mux11~19_combout ;wire \A_SPW_TOP|rx_data|Mux11~2_combout ;wire \A_SPW_TOP|rx_data|Mux11~3_combout ;wire \A_SPW_TOP|rx_data|Mux11~1_combout ;wire \A_SPW_TOP|rx_data|Mux11~0_combout ;wire \A_SPW_TOP|rx_data|Mux11~4_combout ;wire \A_SPW_TOP|rx_data|Mux11~10_combout ;wire \A_SPW_TOP|rx_data|Mux11~12_combout ;wire \A_SPW_TOP|rx_data|Mux11~11_combout ;wire \A_SPW_TOP|rx_data|Mux11~13_combout ;wire \A_SPW_TOP|rx_data|Mux11~14_combout ;wire \A_SPW_TOP|rx_data|Mux11~8_combout ;wire \A_SPW_TOP|rx_data|Mux11~6_combout ;wire \A_SPW_TOP|rx_data|Mux11~7_combout ;wire \A_SPW_TOP|rx_data|Mux11~5_combout ;wire \A_SPW_TOP|rx_data|Mux11~9_combout ;wire \A_SPW_TOP|rx_data|Mux11~20_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][6]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][6]~q ;wire \A_SPW_TOP|SPW|RX|timecode~7_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[6]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][6]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][6]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~77_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~78_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][6]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][6]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~76_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][6]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][6]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~210_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|src_valid~0_combout ;wire \u0|mm_interconnect_0|router_001|Equal16~0_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src10_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][5]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~66_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~12_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~14_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~15_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~16_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~13_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~17_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~18_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|counter_rx_fifo|read_mux_out[5]~5_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][5]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][5]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~68_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][5]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][5]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~67_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][5]~q ;wire \A_SPW_TOP|SPW|RX|timecode~6_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][5]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~69_combout ;wire \A_SPW_TOP|SPW|RX|rx_data_flag~5_combout ;wire \A_SPW_TOP|rx_data|Selector481~0_combout ;wire \A_SPW_TOP|rx_data|mem[51][5]~q ;wire \A_SPW_TOP|rx_data|Selector517~0_combout ;wire \A_SPW_TOP|rx_data|mem[55][5]~q ;wire \A_SPW_TOP|rx_data|Selector553~0_combout ;wire \A_SPW_TOP|rx_data|mem[59][5]~q ;wire \A_SPW_TOP|rx_data|Selector589~0_combout ;wire \A_SPW_TOP|rx_data|mem[63][5]~q ;wire \A_SPW_TOP|rx_data|Mux3~18_combout ;wire \A_SPW_TOP|rx_data|Selector337~0_combout ;wire \A_SPW_TOP|rx_data|mem[35][5]~q ;wire \A_SPW_TOP|rx_data|Selector445~0_combout ;wire \A_SPW_TOP|rx_data|mem[47][5]~q ;wire \A_SPW_TOP|rx_data|Selector409~0_combout ;wire \A_SPW_TOP|rx_data|mem[43][5]~q ;wire \A_SPW_TOP|rx_data|Selector373~0_combout ;wire \A_SPW_TOP|rx_data|mem[39][5]~q ;wire \A_SPW_TOP|rx_data|Mux3~16_combout ;wire \A_SPW_TOP|rx_data|Selector265~0_combout ;wire \A_SPW_TOP|rx_data|mem[27][5]~q ;wire \A_SPW_TOP|rx_data|Selector193~0_combout ;wire \A_SPW_TOP|rx_data|mem[19][5]~q ;wire \A_SPW_TOP|rx_data|Selector301~0_combout ;wire \A_SPW_TOP|rx_data|mem[31][5]~q ;wire \A_SPW_TOP|rx_data|Selector229~0_combout ;wire \A_SPW_TOP|rx_data|mem[23][5]~q ;wire \A_SPW_TOP|rx_data|Mux3~17_combout ;wire \A_SPW_TOP|rx_data|Selector121~0_combout ;wire \A_SPW_TOP|rx_data|mem[11][5]~q ;wire \A_SPW_TOP|rx_data|Selector85~0_combout ;wire \A_SPW_TOP|rx_data|mem[7][5]~q ;wire \A_SPW_TOP|rx_data|Selector157~0_combout ;wire \A_SPW_TOP|rx_data|mem[15][5]~q ;wire \A_SPW_TOP|rx_data|Selector49~0_combout ;wire \A_SPW_TOP|rx_data|mem[3][5]~q ;wire \A_SPW_TOP|rx_data|Mux3~15_combout ;wire \A_SPW_TOP|rx_data|Mux3~19_combout ;wire \A_SPW_TOP|rx_data|Selector58~0_combout ;wire \A_SPW_TOP|rx_data|mem[4][5]~q ;wire \A_SPW_TOP|rx_data|Selector346~0_combout ;wire \A_SPW_TOP|rx_data|mem[36][5]~q ;wire \A_SPW_TOP|rx_data|Selector130~0_combout ;wire \A_SPW_TOP|rx_data|mem[12][5]~q ;wire \A_SPW_TOP|rx_data|Selector418~0_combout ;wire \A_SPW_TOP|rx_data|mem[44][5]~q ;wire \A_SPW_TOP|rx_data|Mux3~1_combout ;wire \A_SPW_TOP|rx_data|Selector274~0_combout ;wire \A_SPW_TOP|rx_data|mem[28][5]~q ;wire \A_SPW_TOP|rx_data|Selector202~0_combout ;wire \A_SPW_TOP|rx_data|mem[20][5]~q ;wire \A_SPW_TOP|rx_data|Selector562~0_combout ;wire \A_SPW_TOP|rx_data|mem[60][5]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[60][5]~q ;wire \A_SPW_TOP|rx_data|Selector490~0_combout ;wire \A_SPW_TOP|rx_data|mem[52][5]~q ;wire \A_SPW_TOP|rx_data|Mux3~3_combout ;wire \A_SPW_TOP|rx_data|Selector454~0_combout ;wire \A_SPW_TOP|rx_data|mem[48][5]~q ;wire \A_SPW_TOP|rx_data|Selector526~0_combout ;wire \A_SPW_TOP|rx_data|mem[56][5]~q ;wire \A_SPW_TOP|rx_data|Selector238~0_combout ;wire \A_SPW_TOP|rx_data|mem[24][5]~q ;wire \A_SPW_TOP|rx_data|Selector166~0_combout ;wire \A_SPW_TOP|rx_data|mem[16][5]~q ;wire \A_SPW_TOP|rx_data|Mux3~2_combout ;wire \A_SPW_TOP|rx_data|Selector310~0_combout ;wire \A_SPW_TOP|rx_data|mem[32][5]~q ;wire \A_SPW_TOP|rx_data|Selector382~0_combout ;wire \A_SPW_TOP|rx_data|mem[40][5]~q ;wire \A_SPW_TOP|rx_data|Selector94~0_combout ;wire \A_SPW_TOP|rx_data|mem[8][5]~q ;wire \A_SPW_TOP|rx_data|Selector22~0_combout ;wire \A_SPW_TOP|rx_data|mem[0][5]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[0][5]~q ;wire \A_SPW_TOP|rx_data|Mux3~0_combout ;wire \A_SPW_TOP|rx_data|Mux3~4_combout ;wire \A_SPW_TOP|rx_data|Selector436~0_combout ;wire \A_SPW_TOP|rx_data|mem[46][5]~q ;wire \A_SPW_TOP|rx_data|Selector76~0_combout ;wire \A_SPW_TOP|rx_data|mem[6][5]~q ;wire \A_SPW_TOP|rx_data|Selector148~0_combout ;wire \A_SPW_TOP|rx_data|mem[14][5]~q ;wire \A_SPW_TOP|rx_data|Selector364~0_combout ;wire \A_SPW_TOP|rx_data|mem[38][5]~q ;wire \A_SPW_TOP|rx_data|Mux3~11_combout ;wire \A_SPW_TOP|rx_data|Selector184~0_combout ;wire \A_SPW_TOP|rx_data|mem[18][5]~q ;wire \A_SPW_TOP|rx_data|Selector256~0_combout ;wire \A_SPW_TOP|rx_data|mem[26][5]~q ;wire \A_SPW_TOP|rx_data|Selector472~0_combout ;wire \A_SPW_TOP|rx_data|mem[50][5]~q ;wire \A_SPW_TOP|rx_data|Selector544~0_combout ;wire \A_SPW_TOP|rx_data|mem[58][5]~q ;wire \A_SPW_TOP|rx_data|Mux3~12_combout ;wire \A_SPW_TOP|rx_data|Selector220~0_combout ;wire \A_SPW_TOP|rx_data|mem[22][5]~q ;wire \A_SPW_TOP|rx_data|Selector292~0_combout ;wire \A_SPW_TOP|rx_data|mem[30][5]~q ;wire \A_SPW_TOP|rx_data|Selector508~0_combout ;wire \A_SPW_TOP|rx_data|mem[54][5]~q ;wire \A_SPW_TOP|rx_data|Selector580~0_combout ;wire \A_SPW_TOP|rx_data|mem[62][5]~q ;wire \A_SPW_TOP|rx_data|Mux3~13_combout ;wire \A_SPW_TOP|rx_data|Selector40~0_combout ;wire \A_SPW_TOP|rx_data|mem[2][5]~q ;wire \A_SPW_TOP|rx_data|Selector328~0_combout ;wire \A_SPW_TOP|rx_data|mem[34][5]~q ;wire \A_SPW_TOP|rx_data|Selector400~0_combout ;wire \A_SPW_TOP|rx_data|mem[42][5]~q ;wire \A_SPW_TOP|rx_data|Selector112~0_combout ;wire \A_SPW_TOP|rx_data|mem[10][5]~q ;wire \A_SPW_TOP|rx_data|Mux3~10_combout ;wire \A_SPW_TOP|rx_data|Mux3~14_combout ;wire \A_SPW_TOP|rx_data|Selector319~0_combout ;wire \A_SPW_TOP|rx_data|mem[33][5]~q ;wire \A_SPW_TOP|rx_data|Selector31~0_combout ;wire \A_SPW_TOP|rx_data|mem[1][5]~q ;wire \A_SPW_TOP|rx_data|Selector391~0_combout ;wire \A_SPW_TOP|rx_data|mem[41][5]~q ;wire \A_SPW_TOP|rx_data|Mux3~5_combout ;wire \A_SPW_TOP|rx_data|Selector283~0_combout ;wire \A_SPW_TOP|rx_data|mem[29][5]~q ;wire \A_SPW_TOP|rx_data|Selector571~0_combout ;wire \A_SPW_TOP|rx_data|mem[61][5]~q ;wire \A_SPW_TOP|rx_data|Selector499~0_combout ;wire \A_SPW_TOP|rx_data|mem[53][5]~q ;wire \A_SPW_TOP|rx_data|Selector211~0_combout ;wire \A_SPW_TOP|rx_data|mem[21][5]~q ;wire \A_SPW_TOP|rx_data|Mux3~8_combout ;wire \A_SPW_TOP|rx_data|Selector67~0_combout ;wire \A_SPW_TOP|rx_data|mem[5][5]~q ;wire \A_SPW_TOP|rx_data|Selector139~0_combout ;wire \A_SPW_TOP|rx_data|mem[13][5]~q ;wire \A_SPW_TOP|rx_data|Selector355~0_combout ;wire \A_SPW_TOP|rx_data|mem[37][5]~q ;wire \A_SPW_TOP|rx_data|Selector427~0_combout ;wire \A_SPW_TOP|rx_data|mem[45][5]~q ;wire \A_SPW_TOP|rx_data|Mux3~6_combout ;wire \A_SPW_TOP|rx_data|Selector175~0_combout ;wire \A_SPW_TOP|rx_data|mem[17][5]~q ;wire \A_SPW_TOP|rx_data|Selector247~0_combout ;wire \A_SPW_TOP|rx_data|mem[25][5]~q ;wire \A_SPW_TOP|rx_data|Selector463~0_combout ;wire \A_SPW_TOP|rx_data|mem[49][5]~q ;wire \A_SPW_TOP|rx_data|Selector535~0_combout ;wire \A_SPW_TOP|rx_data|mem[57][5]~q ;wire \A_SPW_TOP|rx_data|Mux3~7_combout ;wire \A_SPW_TOP|rx_data|Mux3~9_combout ;wire \A_SPW_TOP|rx_data|Mux3~20_combout ;wire \A_SPW_TOP|rx_data|Selector103~0_combout ;wire \A_SPW_TOP|rx_data|mem[9][5]~q ;wire \A_SPW_TOP|rx_data|Mux12~1_combout ;wire \A_SPW_TOP|rx_data|Mux12~3_combout ;wire \A_SPW_TOP|rx_data|Mux12~2_combout ;wire \A_SPW_TOP|rx_data|Mux12~0_combout ;wire \A_SPW_TOP|rx_data|Mux12~4_combout ;wire \A_SPW_TOP|rx_data|Mux12~17_combout ;wire \A_SPW_TOP|rx_data|Mux12~18_combout ;wire \A_SPW_TOP|rx_data|Mux12~16_combout ;wire \A_SPW_TOP|rx_data|Mux12~15_combout ;wire \A_SPW_TOP|rx_data|Mux12~19_combout ;wire \A_SPW_TOP|rx_data|Mux12~11_combout ;wire \A_SPW_TOP|rx_data|Mux12~10_combout ;wire \A_SPW_TOP|rx_data|Mux12~12_combout ;wire \A_SPW_TOP|rx_data|Mux12~13_combout ;wire \A_SPW_TOP|rx_data|Mux12~14_combout ;wire \A_SPW_TOP|rx_data|Mux12~8_combout ;wire \A_SPW_TOP|rx_data|Mux12~6_combout ;wire \A_SPW_TOP|rx_data|Mux12~5_combout ;wire \A_SPW_TOP|rx_data|Mux12~7_combout ;wire \A_SPW_TOP|rx_data|Mux12~9_combout ;wire \A_SPW_TOP|rx_data|Mux12~20_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][5]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][5]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~70_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~13_combout ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~14_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0]~feeder_combout ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~15_combout ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~16_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~18_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~17_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~12_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|counter_tx_fifo|read_mux_out[5]~5_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][5]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][5]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~72_combout ;wire \m_x|bit_d_0~q ;wire \m_x|bit_d_2~q ;wire \m_x|bit_d_4~q ;wire \m_x|bit_d_6~q ;wire \m_x|bit_d_8~q ;wire \m_x|bit_d_1~feeder_combout ;wire \m_x|bit_d_1~q ;wire \m_x|bit_d_3~feeder_combout ;wire \m_x|bit_d_3~q ;wire \m_x|bit_d_5~feeder_combout ;wire \m_x|bit_d_5~q ;wire \m_x|bit_d_7~feeder_combout ;wire \m_x|bit_d_7~q ;wire \m_x|bit_d_9~feeder_combout ;wire \m_x|bit_d_9~q ;wire \m_x|parity_rec_d~q ;wire \m_x|always16~0_combout ;wire \m_x|rx_got_time_code~0_combout ;wire \m_x|last_is_data~0_combout ;wire \m_x|last_is_data~q ;wire \m_x|last_is_control~0_combout ;wire \m_x|last_is_control~q ;wire \m_x|rx_error_d~1_combout ;wire \m_x|dta_timec[0]~feeder_combout ;wire \m_x|dta_timec_p[0]~feeder_combout ;wire \m_x|data~0_combout ;wire \m_x|data~8_combout ;wire \m_x|data[0]~feeder_combout ;wire \m_x|data~7_combout ;wire \m_x|always17~1_combout ;wire \m_x|rx_error_d~0_combout ;wire \m_x|data~1_combout ;wire \m_x|dta_timec[4]~feeder_combout ;wire \m_x|data~4_combout ;wire \m_x|dta_timec_p[5]~feeder_combout ;wire \m_x|data~3_combout ;wire \m_x|dta_timec[3]~feeder_combout ;wire \m_x|dta_timec_p[3]~feeder_combout ;wire \m_x|data~5_combout ;wire \m_x|dta_timec[2]~feeder_combout ;wire \m_x|dta_timec_p[2]~feeder_combout ;wire \m_x|data~6_combout ;wire \m_x|dta_timec[6]~feeder_combout ;wire \m_x|data~2_combout ;wire \m_x|always17~0_combout ;wire \m_x|rx_error_d~2_combout ;wire \m_x|rx_error_d~feeder_combout ;wire \m_x|rx_error_d~q ;wire \m_x|parity_rec_c~q ;wire \m_x|always17~2_combout ;wire \m_x|rx_error_c~0_combout ;wire \m_x|rx_error_c~1_combout ;wire \m_x|rx_error_c~feeder_combout ;wire \m_x|rx_error_c~q ;wire \m_x|rx_error~combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][5]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][5]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~71_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~73_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~74_combout ;wire \u0|mm_interconnect_0|router_001|Equal2~0_combout ;wire \u0|mm_interconnect_0|router_001|Equal10~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_020|update_grant~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|counter_tx_fifo|read_mux_out[4]~4_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][4]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][4]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~64_combout ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~12_combout ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~14_combout ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~16_combout ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~15_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~13_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~17_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~18_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder_combout ;wire \u0|fsm_info|read_mux_out[4]~4_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][4]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][4]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~63_combout ;wire \u0|counter_rx_fifo|read_mux_out[4]~4_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][4]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][4]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~65_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][4]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][4]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~218_combout ;wire \m_x|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][4]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][4]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~58_combout ;wire \u0|mm_interconnect_0|rsp_demux|src1_valid~combout ;wire \A_SPW_TOP|SPW|RX|timecode~5_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][4]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][4]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~60_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;wire \u0|mm_interconnect_0|cmd_mux|src_payload~4_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|led_pio_test|always0~0_combout ;wire \u0|led_pio_test|data_out[4]~_Duplicate_1_q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][4]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][4]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~59_combout ;wire \A_SPW_TOP|SPW|RX|rx_data_flag~4_combout ;wire \A_SPW_TOP|rx_data|Selector230~0_combout ;wire \A_SPW_TOP|rx_data|mem[23][4]~q ;wire \A_SPW_TOP|rx_data|Selector509~0_combout ;wire \A_SPW_TOP|rx_data|mem[54][4]~q ;wire \A_SPW_TOP|rx_data|Selector221~0_combout ;wire \A_SPW_TOP|rx_data|mem[22][4]~q ;wire \A_SPW_TOP|rx_data|Selector518~0_combout ;wire \A_SPW_TOP|rx_data|mem[55][4]~q ;wire \A_SPW_TOP|rx_data|Mux4~17_combout ;wire \A_SPW_TOP|rx_data|Selector581~0_combout ;wire \A_SPW_TOP|rx_data|mem[62][4]~q ;wire \A_SPW_TOP|rx_data|Selector302~0_combout ;wire \A_SPW_TOP|rx_data|mem[31][4]~q ;wire \A_SPW_TOP|rx_data|Selector293~0_combout ;wire \A_SPW_TOP|rx_data|mem[30][4]~q ;wire \A_SPW_TOP|rx_data|Selector590~0_combout ;wire \A_SPW_TOP|rx_data|mem[63][4]~q ;wire \A_SPW_TOP|rx_data|Mux4~18_combout ;wire \A_SPW_TOP|rx_data|Selector212~0_combout ;wire \A_SPW_TOP|rx_data|mem[21][4]~q ;wire \A_SPW_TOP|rx_data|Selector500~0_combout ;wire \A_SPW_TOP|rx_data|mem[53][4]~q ;wire \A_SPW_TOP|rx_data|Selector203~0_combout ;wire \A_SPW_TOP|rx_data|mem[20][4]~q ;wire \A_SPW_TOP|rx_data|Selector491~0_combout ;wire \A_SPW_TOP|rx_data|mem[52][4]~q ;wire \A_SPW_TOP|rx_data|Mux4~15_combout ;wire \A_SPW_TOP|rx_data|Selector275~0_combout ;wire \A_SPW_TOP|rx_data|mem[28][4]~q ;wire \A_SPW_TOP|rx_data|Selector563~0_combout ;wire \A_SPW_TOP|rx_data|mem[60][4]~q ;wire \A_SPW_TOP|rx_data|Selector284~0_combout ;wire \A_SPW_TOP|rx_data|mem[29][4]~q ;wire \A_SPW_TOP|rx_data|Mux4~16_combout ;wire \A_SPW_TOP|rx_data|Mux4~19_combout ;wire \A_SPW_TOP|rx_data|Selector455~0_combout ;wire \A_SPW_TOP|rx_data|mem[48][4]~q ;wire \A_SPW_TOP|rx_data|Selector482~0_combout ;wire \A_SPW_TOP|rx_data|mem[51][4]~q ;wire \A_SPW_TOP|rx_data|Selector464~0_combout ;wire \A_SPW_TOP|rx_data|mem[49][4]~q ;wire \A_SPW_TOP|rx_data|Selector473~0_combout ;wire \A_SPW_TOP|rx_data|mem[50][4]~q ;wire \A_SPW_TOP|rx_data|Mux4~7_combout ;wire \A_SPW_TOP|rx_data|Selector545~0_combout ;wire \A_SPW_TOP|rx_data|mem[58][4]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[58][4]~q ;wire \A_SPW_TOP|rx_data|Selector527~0_combout ;wire \A_SPW_TOP|rx_data|mem[56][4]~q ;wire \A_SPW_TOP|rx_data|Selector536~0_combout ;wire \A_SPW_TOP|rx_data|mem[57][4]~q ;wire \A_SPW_TOP|rx_data|Selector554~0_combout ;wire \A_SPW_TOP|rx_data|mem[59][4]~q ;wire \A_SPW_TOP|rx_data|Mux4~8_combout ;wire \A_SPW_TOP|rx_data|Selector176~0_combout ;wire \A_SPW_TOP|rx_data|mem[17][4]~q ;wire \A_SPW_TOP|rx_data|Selector167~0_combout ;wire \A_SPW_TOP|rx_data|mem[16][4]~q ;wire \A_SPW_TOP|rx_data|Selector185~0_combout ;wire \A_SPW_TOP|rx_data|mem[18][4]~q ;wire \A_SPW_TOP|rx_data|Selector194~0_combout ;wire \A_SPW_TOP|rx_data|mem[19][4]~q ;wire \A_SPW_TOP|rx_data|Mux4~5_combout ;wire \A_SPW_TOP|rx_data|Selector248~0_combout ;wire \A_SPW_TOP|rx_data|mem[25][4]~q ;wire \A_SPW_TOP|rx_data|Selector239~0_combout ;wire \A_SPW_TOP|rx_data|mem[24][4]~q ;wire \A_SPW_TOP|rx_data|Selector257~0_combout ;wire \A_SPW_TOP|rx_data|mem[26][4]~q ;wire \A_SPW_TOP|rx_data|Selector266~0_combout ;wire \A_SPW_TOP|rx_data|mem[27][4]~q ;wire \A_SPW_TOP|rx_data|Mux4~6_combout ;wire \A_SPW_TOP|rx_data|Mux4~9_combout ;wire \A_SPW_TOP|rx_data|Selector113~0_combout ;wire \A_SPW_TOP|rx_data|mem[10][4]~q ;wire \A_SPW_TOP|rx_data|Selector104~0_combout ;wire \A_SPW_TOP|rx_data|mem[9][4]~q ;wire \A_SPW_TOP|rx_data|Selector122~0_combout ;wire \A_SPW_TOP|rx_data|mem[11][4]~q ;wire \A_SPW_TOP|rx_data|Selector95~0_combout ;wire \A_SPW_TOP|rx_data|mem[8][4]~q ;wire \A_SPW_TOP|rx_data|Mux4~1_combout ;wire \A_SPW_TOP|rx_data|Selector338~0_combout ;wire \A_SPW_TOP|rx_data|mem[35][4]~q ;wire \A_SPW_TOP|rx_data|Selector311~0_combout ;wire \A_SPW_TOP|rx_data|mem[32][4]~q ;wire \A_SPW_TOP|rx_data|Selector320~0_combout ;wire \A_SPW_TOP|rx_data|mem[33][4]~q ;wire \A_SPW_TOP|rx_data|Selector329~0_combout ;wire \A_SPW_TOP|rx_data|mem[34][4]~q ;wire \A_SPW_TOP|rx_data|Mux4~2_combout ;wire \A_SPW_TOP|rx_data|Selector50~0_combout ;wire \A_SPW_TOP|rx_data|mem[3][4]~q ;wire \A_SPW_TOP|rx_data|Selector23~0_combout ;wire \A_SPW_TOP|rx_data|mem[0][4]~q ;wire \A_SPW_TOP|rx_data|Selector32~0_combout ;wire \A_SPW_TOP|rx_data|mem[1][4]~q ;wire \A_SPW_TOP|rx_data|Selector41~0_combout ;wire \A_SPW_TOP|rx_data|mem[2][4]~q ;wire \A_SPW_TOP|rx_data|Mux4~0_combout ;wire \A_SPW_TOP|rx_data|Selector392~0_combout ;wire \A_SPW_TOP|rx_data|mem[41][4]~q ;wire \A_SPW_TOP|rx_data|Selector401~0_combout ;wire \A_SPW_TOP|rx_data|mem[42][4]~q ;wire \A_SPW_TOP|rx_data|Selector410~0_combout ;wire \A_SPW_TOP|rx_data|mem[43][4]~q ;wire \A_SPW_TOP|rx_data|Selector383~0_combout ;wire \A_SPW_TOP|rx_data|mem[40][4]~q ;wire \A_SPW_TOP|rx_data|Mux4~3_combout ;wire \A_SPW_TOP|rx_data|Mux4~4_combout ;wire \A_SPW_TOP|rx_data|Selector356~0_combout ;wire \A_SPW_TOP|rx_data|mem[37][4]~q ;wire \A_SPW_TOP|rx_data|Selector347~0_combout ;wire \A_SPW_TOP|rx_data|mem[36][4]~q ;wire \A_SPW_TOP|rx_data|Selector374~0_combout ;wire \A_SPW_TOP|rx_data|mem[39][4]~q ;wire \A_SPW_TOP|rx_data|Selector365~0_combout ;wire \A_SPW_TOP|rx_data|mem[38][4]~q ;wire \A_SPW_TOP|rx_data|Mux4~12_combout ;wire \A_SPW_TOP|rx_data|Selector437~0_combout ;wire \A_SPW_TOP|rx_data|mem[46][4]~q ;wire \A_SPW_TOP|rx_data|Selector419~0_combout ;wire \A_SPW_TOP|rx_data|mem[44][4]~q ;wire \A_SPW_TOP|rx_data|Selector428~0_combout ;wire \A_SPW_TOP|rx_data|mem[45][4]~q ;wire \A_SPW_TOP|rx_data|Selector446~0_combout ;wire \A_SPW_TOP|rx_data|mem[47][4]~q ;wire \A_SPW_TOP|rx_data|Mux4~13_combout ;wire \A_SPW_TOP|rx_data|Selector140~0_combout ;wire \A_SPW_TOP|rx_data|mem[13][4]~q ;wire \A_SPW_TOP|rx_data|Selector149~0_combout ;wire \A_SPW_TOP|rx_data|mem[14][4]~q ;wire \A_SPW_TOP|rx_data|Selector158~0_combout ;wire \A_SPW_TOP|rx_data|mem[15][4]~q ;wire \A_SPW_TOP|rx_data|Selector131~0_combout ;wire \A_SPW_TOP|rx_data|mem[12][4]~q ;wire \A_SPW_TOP|rx_data|Mux4~11_combout ;wire \A_SPW_TOP|rx_data|Selector86~0_combout ;wire \A_SPW_TOP|rx_data|mem[7][4]~q ;wire \A_SPW_TOP|rx_data|Selector77~0_combout ;wire \A_SPW_TOP|rx_data|mem[6][4]~q ;wire \A_SPW_TOP|rx_data|Selector59~0_combout ;wire \A_SPW_TOP|rx_data|mem[4][4]~q ;wire \A_SPW_TOP|rx_data|Selector68~0_combout ;wire \A_SPW_TOP|rx_data|mem[5][4]~q ;wire \A_SPW_TOP|rx_data|Mux4~10_combout ;wire \A_SPW_TOP|rx_data|Mux4~14_combout ;wire \A_SPW_TOP|rx_data|Mux4~20_combout ;wire \A_SPW_TOP|rx_data|Selector572~0_combout ;wire \A_SPW_TOP|rx_data|mem[61][4]~q ;wire \A_SPW_TOP|rx_data|Mux13~17_combout ;wire \A_SPW_TOP|rx_data|Mux13~15_combout ;wire \A_SPW_TOP|rx_data|Mux13~18_combout ;wire \A_SPW_TOP|rx_data|Mux13~16_combout ;wire \A_SPW_TOP|rx_data|Mux13~19_combout ;wire \A_SPW_TOP|rx_data|Mux13~13_combout ;wire \A_SPW_TOP|rx_data|Mux13~11_combout ;wire \A_SPW_TOP|rx_data|Mux13~12_combout ;wire \A_SPW_TOP|rx_data|Mux13~10_combout ;wire \A_SPW_TOP|rx_data|Mux13~14_combout ;wire \A_SPW_TOP|rx_data|Mux13~3_combout ;wire \A_SPW_TOP|rx_data|Mux13~1_combout ;wire \A_SPW_TOP|rx_data|Mux13~2_combout ;wire \A_SPW_TOP|rx_data|Mux13~0_combout ;wire \A_SPW_TOP|rx_data|Mux13~4_combout ;wire \A_SPW_TOP|rx_data|Mux13~6_combout ;wire \A_SPW_TOP|rx_data|Mux13~7_combout ;wire \A_SPW_TOP|rx_data|Mux13~8_combout ;wire \A_SPW_TOP|rx_data|Mux13~5_combout ;wire \A_SPW_TOP|rx_data|Mux13~9_combout ;wire \A_SPW_TOP|rx_data|Mux13~20_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][4]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][4]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~61_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~62_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][4]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][4]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~214_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ;wire \u0|mm_interconnect_0|cmd_demux|src14_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|arb|grant[0]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][3]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][3]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~50_combout ;wire \A_SPW_TOP|SPW|RX|rx_data_flag~3_combout ;wire \A_SPW_TOP|rx_data|Selector429~0_combout ;wire \A_SPW_TOP|rx_data|mem[45][3]~q ;wire \A_SPW_TOP|rx_data|Selector591~0_combout ;wire \A_SPW_TOP|rx_data|mem[63][3]~q ;wire \A_SPW_TOP|rx_data|Selector447~0_combout ;wire \A_SPW_TOP|rx_data|mem[47][3]~q ;wire \A_SPW_TOP|rx_data|Selector573~0_combout ;wire \A_SPW_TOP|rx_data|mem[61][3]~q ;wire \A_SPW_TOP|rx_data|Mux5~18_combout ;wire \A_SPW_TOP|rx_data|Selector582~0_combout ;wire \A_SPW_TOP|rx_data|mem[62][3]~q ;wire \A_SPW_TOP|rx_data|Selector564~0_combout ;wire \A_SPW_TOP|rx_data|mem[60][3]~q ;wire \A_SPW_TOP|rx_data|Selector420~0_combout ;wire \A_SPW_TOP|rx_data|mem[44][3]~q ;wire \A_SPW_TOP|rx_data|Mux5~17_combout ;wire \A_SPW_TOP|rx_data|Selector411~0_combout ;wire \A_SPW_TOP|rx_data|mem[43][3]~q ;wire \A_SPW_TOP|rx_data|Selector393~0_combout ;wire \A_SPW_TOP|rx_data|mem[41][3]~q ;wire \A_SPW_TOP|rx_data|Selector555~0_combout ;wire \A_SPW_TOP|rx_data|mem[59][3]~q ;wire \A_SPW_TOP|rx_data|Selector537~0_combout ;wire \A_SPW_TOP|rx_data|mem[57][3]~q ;wire \A_SPW_TOP|rx_data|Mux5~16_combout ;wire \A_SPW_TOP|rx_data|Selector384~0_combout ;wire \A_SPW_TOP|rx_data|mem[40][3]~q ;wire \A_SPW_TOP|rx_data|Selector546~0_combout ;wire \A_SPW_TOP|rx_data|mem[58][3]~q ;wire \A_SPW_TOP|rx_data|Selector528~0_combout ;wire \A_SPW_TOP|rx_data|mem[56][3]~q ;wire \A_SPW_TOP|rx_data|Selector402~0_combout ;wire \A_SPW_TOP|rx_data|mem[42][3]~q ;wire \A_SPW_TOP|rx_data|Mux5~15_combout ;wire \A_SPW_TOP|rx_data|Mux5~19_combout ;wire \A_SPW_TOP|rx_data|Selector303~0_combout ;wire \A_SPW_TOP|rx_data|mem[31][3]~q ;wire \A_SPW_TOP|rx_data|Selector123~0_combout ;wire \A_SPW_TOP|rx_data|mem[11][3]~q ;wire \A_SPW_TOP|rx_data|Selector159~0_combout ;wire \A_SPW_TOP|rx_data|mem[15][3]~q ;wire \A_SPW_TOP|rx_data|Selector267~0_combout ;wire \A_SPW_TOP|rx_data|mem[27][3]~q ;wire \A_SPW_TOP|rx_data|Mux5~8_combout ;wire \A_SPW_TOP|rx_data|Selector141~0_combout ;wire \A_SPW_TOP|rx_data|mem[13][3]~q ;wire \A_SPW_TOP|rx_data|Selector105~0_combout ;wire \A_SPW_TOP|rx_data|mem[9][3]~q ;wire \A_SPW_TOP|rx_data|Selector285~0_combout ;wire \A_SPW_TOP|rx_data|mem[29][3]~q ;wire \A_SPW_TOP|rx_data|Selector249~0_combout ;wire \A_SPW_TOP|rx_data|mem[25][3]~q ;wire \A_SPW_TOP|rx_data|Mux5~6_combout ;wire \A_SPW_TOP|rx_data|Selector258~0_combout ;wire \A_SPW_TOP|rx_data|mem[26][3]~q ;wire \A_SPW_TOP|rx_data|Selector114~0_combout ;wire \A_SPW_TOP|rx_data|mem[10][3]~q ;wire \A_SPW_TOP|rx_data|Selector294~0_combout ;wire \A_SPW_TOP|rx_data|mem[30][3]~q ;wire \A_SPW_TOP|rx_data|Selector150~0_combout ;wire \A_SPW_TOP|rx_data|mem[14][3]~q ;wire \A_SPW_TOP|rx_data|Mux5~7_combout ;wire \A_SPW_TOP|rx_data|Selector276~0_combout ;wire \A_SPW_TOP|rx_data|mem[28][3]~q ;wire \A_SPW_TOP|rx_data|Selector240~0_combout ;wire \A_SPW_TOP|rx_data|mem[24][3]~q ;wire \A_SPW_TOP|rx_data|Selector96~0_combout ;wire \A_SPW_TOP|rx_data|mem[8][3]~q ;wire \A_SPW_TOP|rx_data|Selector132~0_combout ;wire \A_SPW_TOP|rx_data|mem[12][3]~q ;wire \A_SPW_TOP|rx_data|Mux5~5_combout ;wire \A_SPW_TOP|rx_data|Mux5~9_combout ;wire \A_SPW_TOP|rx_data|Selector69~0_combout ;wire \A_SPW_TOP|rx_data|mem[5][3]~q ;wire \A_SPW_TOP|rx_data|Selector177~0_combout ;wire \A_SPW_TOP|rx_data|mem[17][3]~q ;wire \A_SPW_TOP|rx_data|Selector213~0_combout ;wire \A_SPW_TOP|rx_data|mem[21][3]~q ;wire \A_SPW_TOP|rx_data|Selector33~0_combout ;wire \A_SPW_TOP|rx_data|mem[1][3]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[1][3]~q ;wire \A_SPW_TOP|rx_data|Mux5~1_combout ;wire \A_SPW_TOP|rx_data|Selector78~0_combout ;wire \A_SPW_TOP|rx_data|mem[6][3]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[6][3]~q ;wire \A_SPW_TOP|rx_data|Selector186~0_combout ;wire \A_SPW_TOP|rx_data|mem[18][3]~q ;wire \A_SPW_TOP|rx_data|Selector222~0_combout ;wire \A_SPW_TOP|rx_data|mem[22][3]~q ;wire \A_SPW_TOP|rx_data|Selector42~0_combout ;wire \A_SPW_TOP|rx_data|mem[2][3]~q ;wire \A_SPW_TOP|rx_data|Mux5~2_combout ;wire \A_SPW_TOP|rx_data|Selector204~0_combout ;wire \A_SPW_TOP|rx_data|mem[20][3]~q ;wire \A_SPW_TOP|rx_data|Selector60~0_combout ;wire \A_SPW_TOP|rx_data|mem[4][3]~q ;wire \A_SPW_TOP|rx_data|Selector168~0_combout ;wire \A_SPW_TOP|rx_data|mem[16][3]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[16][3]~q ;wire \A_SPW_TOP|rx_data|Selector24~0_combout ;wire \A_SPW_TOP|rx_data|mem[0][3]~q ;wire \A_SPW_TOP|rx_data|Mux5~0_combout ;wire \A_SPW_TOP|rx_data|Selector87~0_combout ;wire \A_SPW_TOP|rx_data|mem[7][3]~q ;wire \A_SPW_TOP|rx_data|Selector195~0_combout ;wire \A_SPW_TOP|rx_data|mem[19][3]~q ;wire \A_SPW_TOP|rx_data|Selector231~0_combout ;wire \A_SPW_TOP|rx_data|mem[23][3]~q ;wire \A_SPW_TOP|rx_data|Selector51~0_combout ;wire \A_SPW_TOP|rx_data|mem[3][3]~q ;wire \A_SPW_TOP|rx_data|Mux5~3_combout ;wire \A_SPW_TOP|rx_data|Mux5~4_combout ;wire \A_SPW_TOP|rx_data|Selector321~0_combout ;wire \A_SPW_TOP|rx_data|mem[33][3]~q ;wire \A_SPW_TOP|rx_data|Selector357~0_combout ;wire \A_SPW_TOP|rx_data|mem[37][3]~q ;wire \A_SPW_TOP|rx_data|Selector501~0_combout ;wire \A_SPW_TOP|rx_data|mem[53][3]~q ;wire \A_SPW_TOP|rx_data|Selector465~0_combout ;wire \A_SPW_TOP|rx_data|mem[49][3]~q ;wire \A_SPW_TOP|rx_data|Mux5~11_combout ;wire \A_SPW_TOP|rx_data|Selector474~0_combout ;wire \A_SPW_TOP|rx_data|mem[50][3]~q ;wire \A_SPW_TOP|rx_data|Selector366~0_combout ;wire \A_SPW_TOP|rx_data|mem[38][3]~q ;wire \A_SPW_TOP|rx_data|Selector330~0_combout ;wire \A_SPW_TOP|rx_data|mem[34][3]~q ;wire \A_SPW_TOP|rx_data|Selector510~0_combout ;wire \A_SPW_TOP|rx_data|mem[54][3]~q ;wire \A_SPW_TOP|rx_data|Mux5~12_combout ;wire \A_SPW_TOP|rx_data|Selector492~0_combout ;wire \A_SPW_TOP|rx_data|mem[52][3]~q ;wire \A_SPW_TOP|rx_data|Selector312~0_combout ;wire \A_SPW_TOP|rx_data|mem[32][3]~q ;wire \A_SPW_TOP|rx_data|Selector456~0_combout ;wire \A_SPW_TOP|rx_data|mem[48][3]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[48][3]~q ;wire \A_SPW_TOP|rx_data|Selector348~0_combout ;wire \A_SPW_TOP|rx_data|mem[36][3]~q ;wire \A_SPW_TOP|rx_data|Mux5~10_combout ;wire \A_SPW_TOP|rx_data|Selector519~0_combout ;wire \A_SPW_TOP|rx_data|mem[55][3]~q ;wire \A_SPW_TOP|rx_data|Selector339~0_combout ;wire \A_SPW_TOP|rx_data|mem[35][3]~q ;wire \A_SPW_TOP|rx_data|Selector483~0_combout ;wire \A_SPW_TOP|rx_data|mem[51][3]~q ;wire \A_SPW_TOP|rx_data|Selector375~0_combout ;wire \A_SPW_TOP|rx_data|mem[39][3]~q ;wire \A_SPW_TOP|rx_data|Mux5~13_combout ;wire \A_SPW_TOP|rx_data|Mux5~14_combout ;wire \A_SPW_TOP|rx_data|Mux5~20_combout ;wire \A_SPW_TOP|rx_data|Selector438~0_combout ;wire \A_SPW_TOP|rx_data|mem[46][3]~q ;wire \A_SPW_TOP|rx_data|Mux14~13_combout ;wire \A_SPW_TOP|rx_data|Mux14~12_combout ;wire \A_SPW_TOP|rx_data|Mux14~11_combout ;wire \A_SPW_TOP|rx_data|Mux14~10_combout ;wire \A_SPW_TOP|rx_data|Mux14~14_combout ;wire \A_SPW_TOP|rx_data|Mux14~1_combout ;wire \A_SPW_TOP|rx_data|Mux14~0_combout ;wire \A_SPW_TOP|rx_data|Mux14~2_combout ;wire \A_SPW_TOP|rx_data|Mux14~3_combout ;wire \A_SPW_TOP|rx_data|Mux14~4_combout ;wire \A_SPW_TOP|rx_data|Mux14~17_combout ;wire \A_SPW_TOP|rx_data|Mux14~16_combout ;wire \A_SPW_TOP|rx_data|Mux14~15_combout ;wire \A_SPW_TOP|rx_data|Mux14~18_combout ;wire \A_SPW_TOP|rx_data|Mux14~19_combout ;wire \A_SPW_TOP|rx_data|Mux14~8_combout ;wire \A_SPW_TOP|rx_data|Mux14~5_combout ;wire \A_SPW_TOP|rx_data|Mux14~6_combout ;wire \A_SPW_TOP|rx_data|Mux14~7_combout ;wire \A_SPW_TOP|rx_data|Mux14~9_combout ;wire \A_SPW_TOP|rx_data|Mux14~20_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][3]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][3]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~53_combout ;wire \u0|mm_interconnect_0|cmd_mux|src_payload~3_combout ;wire \u0|led_pio_test|data_out[3]~_Duplicate_1_q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][3]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][3]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~51_combout ;wire \A_SPW_TOP|SPW|RX|timecode~4_combout ;wire \A_SPW_TOP|SPW|RX|timecode[3]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][3]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][3]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~52_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~54_combout ;wire \m_x|always10~0_combout ;wire \m_x|always10~1_combout ;wire \m_x|rx_got_null~0_combout ;wire \m_x|rx_got_null~q ;wire \u0|fsm_info|read_mux_out[3]~3_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][3]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][3]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~55_combout ;wire \u0|counter_tx_fifo|read_mux_out[3]~3_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][3]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][3]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~56_combout ;wire \u0|counter_rx_fifo|read_mux_out[3]~3_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][3]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][3]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~57_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][3]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][3]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~226_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][3]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][3]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~222_combout ;wire \u0|mm_interconnect_0|router_001|Equal1~1_combout ;wire \u0|mm_interconnect_0|router_001|Equal4~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_017|update_grant~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][2]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][2]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~47_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][69]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][69]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][68]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][68]~q ;wire \u0|mm_interconnect_0|rsp_demux_018|WideOr0~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_018|src_payload~2_combout ;wire \u0|clock_sel|data_out[2]~feeder_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|m0_write~combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|clock_sel|always0~0_combout ;wire \u0|clock_sel|readdata[2]~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][2]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][2]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~48_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~49_combout ;wire \m_x|rx_got_nchar~0_combout ;wire \m_x|rx_got_nchar~q ;wire \u0|counter_rx_fifo|read_mux_out[2]~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][2]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][2]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~46_combout ;wire \u0|counter_tx_fifo|read_mux_out[2]~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][2]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][2]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~45_combout ;wire \u0|fsm_info|read_mux_out[2]~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][2]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][2]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~44_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][2]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][2]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~234_combout ;wire \A_SPW_TOP|SPW|RX|timecode~3_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[2]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][2]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][2]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~41_combout ;wire \A_SPW_TOP|SPW|RX|rx_data_flag~2_combout ;wire \A_SPW_TOP|rx_data|Selector250~0_combout ;wire \A_SPW_TOP|rx_data|mem[25][2]~q ;wire \A_SPW_TOP|rx_data|Selector178~0_combout ;wire \A_SPW_TOP|rx_data|mem[17][2]~q ;wire \A_SPW_TOP|rx_data|Selector538~0_combout ;wire \A_SPW_TOP|rx_data|mem[57][2]~q ;wire \A_SPW_TOP|rx_data|Selector466~0_combout ;wire \A_SPW_TOP|rx_data|mem[49][2]~q ;wire \A_SPW_TOP|rx_data|Mux6~7_combout ;wire \A_SPW_TOP|rx_data|Selector574~0_combout ;wire \A_SPW_TOP|rx_data|mem[61][2]~q ;wire \A_SPW_TOP|rx_data|Selector502~0_combout ;wire \A_SPW_TOP|rx_data|mem[53][2]~q ;wire \A_SPW_TOP|rx_data|Selector286~0_combout ;wire \A_SPW_TOP|rx_data|mem[29][2]~q ;wire \A_SPW_TOP|rx_data|Selector214~0_combout ;wire \A_SPW_TOP|rx_data|mem[21][2]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[21][2]~q ;wire \A_SPW_TOP|rx_data|Mux6~8_combout ;wire \A_SPW_TOP|rx_data|Selector358~0_combout ;wire \A_SPW_TOP|rx_data|mem[37][2]~q ;wire \A_SPW_TOP|rx_data|Selector70~0_combout ;wire \A_SPW_TOP|rx_data|mem[5][2]~q ;wire \A_SPW_TOP|rx_data|Selector142~0_combout ;wire \A_SPW_TOP|rx_data|mem[13][2]~q ;wire \A_SPW_TOP|rx_data|Selector430~0_combout ;wire \A_SPW_TOP|rx_data|mem[45][2]~q ;wire \A_SPW_TOP|rx_data|Mux6~6_combout ;wire \A_SPW_TOP|rx_data|Selector34~0_combout ;wire \A_SPW_TOP|rx_data|mem[1][2]~q ;wire \A_SPW_TOP|rx_data|Selector394~0_combout ;wire \A_SPW_TOP|rx_data|mem[41][2]~q ;wire \A_SPW_TOP|rx_data|Selector106~0_combout ;wire \A_SPW_TOP|rx_data|mem[9][2]~q ;wire \A_SPW_TOP|rx_data|Selector322~0_combout ;wire \A_SPW_TOP|rx_data|mem[33][2]~q ;wire \A_SPW_TOP|rx_data|Mux6~5_combout ;wire \A_SPW_TOP|rx_data|Mux6~9_combout ;wire \A_SPW_TOP|rx_data|Selector493~0_combout ;wire \A_SPW_TOP|rx_data|mem[52][2]~q ;wire \A_SPW_TOP|rx_data|Selector277~0_combout ;wire \A_SPW_TOP|rx_data|mem[28][2]~q ;wire \A_SPW_TOP|rx_data|Selector205~0_combout ;wire \A_SPW_TOP|rx_data|mem[20][2]~q ;wire \A_SPW_TOP|rx_data|Selector565~0_combout ;wire \A_SPW_TOP|rx_data|mem[60][2]~q ;wire \A_SPW_TOP|rx_data|Mux6~3_combout ;wire \A_SPW_TOP|rx_data|Selector61~0_combout ;wire \A_SPW_TOP|rx_data|mem[4][2]~q ;wire \A_SPW_TOP|rx_data|Selector421~0_combout ;wire \A_SPW_TOP|rx_data|mem[44][2]~q ;wire \A_SPW_TOP|rx_data|Selector133~0_combout ;wire \A_SPW_TOP|rx_data|mem[12][2]~q ;wire \A_SPW_TOP|rx_data|Selector349~0_combout ;wire \A_SPW_TOP|rx_data|mem[36][2]~q ;wire \A_SPW_TOP|rx_data|Mux6~1_combout ;wire \A_SPW_TOP|rx_data|Selector97~0_combout ;wire \A_SPW_TOP|rx_data|mem[8][2]~q ;wire \A_SPW_TOP|rx_data|Selector313~0_combout ;wire \A_SPW_TOP|rx_data|mem[32][2]~q ;wire \A_SPW_TOP|rx_data|Selector385~0_combout ;wire \A_SPW_TOP|rx_data|mem[40][2]~q ;wire \A_SPW_TOP|rx_data|Selector25~0_combout ;wire \A_SPW_TOP|rx_data|mem[0][2]~q ;wire \A_SPW_TOP|rx_data|Mux6~0_combout ;wire \A_SPW_TOP|rx_data|Selector457~0_combout ;wire \A_SPW_TOP|rx_data|mem[48][2]~q ;wire \A_SPW_TOP|rx_data|Selector241~0_combout ;wire \A_SPW_TOP|rx_data|mem[24][2]~q ;wire \A_SPW_TOP|rx_data|Selector529~0_combout ;wire \A_SPW_TOP|rx_data|mem[56][2]~q ;wire \A_SPW_TOP|rx_data|Selector169~0_combout ;wire \A_SPW_TOP|rx_data|mem[16][2]~q ;wire \A_SPW_TOP|rx_data|Mux6~2_combout ;wire \A_SPW_TOP|rx_data|Mux6~4_combout ;wire \A_SPW_TOP|rx_data|Selector187~0_combout ;wire \A_SPW_TOP|rx_data|mem[18][2]~q ;wire \A_SPW_TOP|rx_data|Selector475~0_combout ;wire \A_SPW_TOP|rx_data|mem[50][2]~q ;wire \A_SPW_TOP|rx_data|Selector547~0_combout ;wire \A_SPW_TOP|rx_data|mem[58][2]~q ;wire \A_SPW_TOP|rx_data|Selector259~0_combout ;wire \A_SPW_TOP|rx_data|mem[26][2]~q ;wire \A_SPW_TOP|rx_data|Mux6~12_combout ;wire \A_SPW_TOP|rx_data|Selector511~0_combout ;wire \A_SPW_TOP|rx_data|mem[54][2]~q ;wire \A_SPW_TOP|rx_data|Selector223~0_combout ;wire \A_SPW_TOP|rx_data|mem[22][2]~q ;wire \A_SPW_TOP|rx_data|Selector295~0_combout ;wire \A_SPW_TOP|rx_data|mem[30][2]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[30][2]~q ;wire \A_SPW_TOP|rx_data|Selector583~0_combout ;wire \A_SPW_TOP|rx_data|mem[62][2]~q ;wire \A_SPW_TOP|rx_data|Mux6~13_combout ;wire \A_SPW_TOP|rx_data|Selector79~0_combout ;wire \A_SPW_TOP|rx_data|mem[6][2]~q ;wire \A_SPW_TOP|rx_data|Selector439~0_combout ;wire \A_SPW_TOP|rx_data|mem[46][2]~q ;wire \A_SPW_TOP|rx_data|Selector367~0_combout ;wire \A_SPW_TOP|rx_data|mem[38][2]~q ;wire \A_SPW_TOP|rx_data|Selector151~0_combout ;wire \A_SPW_TOP|rx_data|mem[14][2]~q ;wire \A_SPW_TOP|rx_data|Mux6~11_combout ;wire \A_SPW_TOP|rx_data|Selector115~0_combout ;wire \A_SPW_TOP|rx_data|mem[10][2]~q ;wire \A_SPW_TOP|rx_data|Selector331~0_combout ;wire \A_SPW_TOP|rx_data|mem[34][2]~q ;wire \A_SPW_TOP|rx_data|Selector403~0_combout ;wire \A_SPW_TOP|rx_data|mem[42][2]~q ;wire \A_SPW_TOP|rx_data|Selector43~0_combout ;wire \A_SPW_TOP|rx_data|mem[2][2]~q ;wire \A_SPW_TOP|rx_data|Mux6~10_combout ;wire \A_SPW_TOP|rx_data|Mux6~14_combout ;wire \A_SPW_TOP|rx_data|Selector52~0_combout ;wire \A_SPW_TOP|rx_data|mem[3][2]~q ;wire \A_SPW_TOP|rx_data|Selector160~0_combout ;wire \A_SPW_TOP|rx_data|mem[15][2]~q ;wire \A_SPW_TOP|rx_data|Selector124~0_combout ;wire \A_SPW_TOP|rx_data|mem[11][2]~q ;wire \A_SPW_TOP|rx_data|Selector88~0_combout ;wire \A_SPW_TOP|rx_data|mem[7][2]~q ;wire \A_SPW_TOP|rx_data|Mux6~15_combout ;wire \A_SPW_TOP|rx_data|Selector304~0_combout ;wire \A_SPW_TOP|rx_data|mem[31][2]~q ;wire \A_SPW_TOP|rx_data|Selector232~0_combout ;wire \A_SPW_TOP|rx_data|mem[23][2]~q ;wire \A_SPW_TOP|rx_data|Selector268~0_combout ;wire \A_SPW_TOP|rx_data|mem[27][2]~q ;wire \A_SPW_TOP|rx_data|Mux6~17_combout ;wire \A_SPW_TOP|rx_data|Selector520~0_combout ;wire \A_SPW_TOP|rx_data|mem[55][2]~q ;wire \A_SPW_TOP|rx_data|Selector484~0_combout ;wire \A_SPW_TOP|rx_data|mem[51][2]~q ;wire \A_SPW_TOP|rx_data|Selector592~0_combout ;wire \A_SPW_TOP|rx_data|mem[63][2]~q ;wire \A_SPW_TOP|rx_data|Selector556~0_combout ;wire \A_SPW_TOP|rx_data|mem[59][2]~q ;wire \A_SPW_TOP|rx_data|Mux6~18_combout ;wire \A_SPW_TOP|rx_data|Selector340~0_combout ;wire \A_SPW_TOP|rx_data|mem[35][2]~q ;wire \A_SPW_TOP|rx_data|Selector412~0_combout ;wire \A_SPW_TOP|rx_data|mem[43][2]~q ;wire \A_SPW_TOP|rx_data|Selector448~0_combout ;wire \A_SPW_TOP|rx_data|mem[47][2]~q ;wire \A_SPW_TOP|rx_data|Selector376~0_combout ;wire \A_SPW_TOP|rx_data|mem[39][2]~q ;wire \A_SPW_TOP|rx_data|Mux6~16_combout ;wire \A_SPW_TOP|rx_data|Mux6~19_combout ;wire \A_SPW_TOP|rx_data|Mux6~20_combout ;wire \A_SPW_TOP|rx_data|Selector196~0_combout ;wire \A_SPW_TOP|rx_data|mem[19][2]~q ;wire \A_SPW_TOP|rx_data|Mux15~11_combout ;wire \A_SPW_TOP|rx_data|Mux15~10_combout ;wire \A_SPW_TOP|rx_data|Mux15~13_combout ;wire \A_SPW_TOP|rx_data|Mux15~12_combout ;wire \A_SPW_TOP|rx_data|Mux15~14_combout ;wire \A_SPW_TOP|rx_data|Mux15~6_combout ;wire \A_SPW_TOP|rx_data|Mux15~5_combout ;wire \A_SPW_TOP|rx_data|Mux15~7_combout ;wire \A_SPW_TOP|rx_data|Mux15~8_combout ;wire \A_SPW_TOP|rx_data|Mux15~9_combout ;wire \A_SPW_TOP|rx_data|Mux15~16_combout ;wire \A_SPW_TOP|rx_data|Mux15~18_combout ;wire \A_SPW_TOP|rx_data|Mux15~15_combout ;wire \A_SPW_TOP|rx_data|Mux15~17_combout ;wire \A_SPW_TOP|rx_data|Mux15~19_combout ;wire \A_SPW_TOP|rx_data|Mux15~1_combout ;wire \A_SPW_TOP|rx_data|Mux15~3_combout ;wire \A_SPW_TOP|rx_data|Mux15~2_combout ;wire \A_SPW_TOP|rx_data|Mux15~0_combout ;wire \A_SPW_TOP|rx_data|Mux15~4_combout ;wire \A_SPW_TOP|rx_data|Mux15~20_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][2]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][2]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~42_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][2]~q ;wire \u0|mm_interconnect_0|cmd_mux|src_payload~2_combout ;wire \u0|led_pio_test|data_out[2]~_Duplicate_1feeder_combout ;wire \u0|led_pio_test|data_out[2]~_Duplicate_1_q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][2]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~40_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~43_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][2]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][2]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~230_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ;wire \u0|mm_interconnect_0|router|Equal15~0_combout ;wire \u0|mm_interconnect_0|cmd_demux|src9_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_009|arb|grant[0]~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_009|src_payload~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|link_disable|always0~0_combout ;wire \u0|link_disable|data_out~q ;wire \u0|mm_interconnect_0|cmd_mux_007|src_payload~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|link_start|always0~0_combout ;wire \u0|link_start|data_out~q ;wire \u0|mm_interconnect_0|cmd_mux_008|src_payload~0_combout ;wire \u0|auto_start|data_out~feeder_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|m0_write~combout ;wire \u0|auto_start|always0~0_combout ;wire \u0|auto_start|data_out~q ;wire \A_SPW_TOP|SPW|FSM|state_fsm~26_combout ;wire \A_SPW_TOP|SPW|FSM|state_fsm~20_combout ;wire \A_SPW_TOP|SPW|FSM|state_fsm~16_combout ;wire \A_SPW_TOP|SPW|FSM|state_fsm.ready~q ;wire \A_SPW_TOP|SPW|FSM|state_fsm~27_combout ;wire \A_SPW_TOP|SPW|FSM|state_fsm~28_combout ;wire \A_SPW_TOP|SPW|FSM|state_fsm~17_combout ;wire \A_SPW_TOP|SPW|FSM|state_fsm.started~q ;wire \A_SPW_TOP|SPW|FSM|after128us~0_combout ;wire \A_SPW_TOP|SPW|FSM|Add0~1_sumout ;wire \A_SPW_TOP|SPW|FSM|after128us~1_combout ;wire \A_SPW_TOP|SPW|FSM|Add0~2 ;wire \A_SPW_TOP|SPW|FSM|Add0~5_sumout ;wire \A_SPW_TOP|SPW|FSM|after128us~2_combout ;wire \A_SPW_TOP|SPW|FSM|Add0~6 ;wire \A_SPW_TOP|SPW|FSM|Add0~9_sumout ;wire \A_SPW_TOP|SPW|FSM|after128us~3_combout ;wire \A_SPW_TOP|SPW|FSM|Add0~10 ;wire \A_SPW_TOP|SPW|FSM|Add0~13_sumout ;wire \A_SPW_TOP|SPW|FSM|after128us~4_combout ;wire \A_SPW_TOP|SPW|FSM|Add0~14 ;wire \A_SPW_TOP|SPW|FSM|Add0~17_sumout ;wire \A_SPW_TOP|SPW|FSM|after128us~5_combout ;wire \A_SPW_TOP|SPW|FSM|Add0~18 ;wire \A_SPW_TOP|SPW|FSM|Add0~21_sumout ;wire \A_SPW_TOP|SPW|FSM|after128us~6_combout ;wire \A_SPW_TOP|SPW|FSM|Add0~22 ;wire \A_SPW_TOP|SPW|FSM|Add0~26 ;wire \A_SPW_TOP|SPW|FSM|Add0~29_sumout ;wire \A_SPW_TOP|SPW|FSM|after128us~8_combout ;wire \A_SPW_TOP|SPW|FSM|Add0~30 ;wire \A_SPW_TOP|SPW|FSM|Add0~37_sumout ;wire \A_SPW_TOP|SPW|FSM|after128us~10_combout ;wire \A_SPW_TOP|SPW|FSM|Add0~38 ;wire \A_SPW_TOP|SPW|FSM|Add0~41_sumout ;wire \A_SPW_TOP|SPW|FSM|after128us~11_combout ;wire \A_SPW_TOP|SPW|FSM|Add0~42 ;wire \A_SPW_TOP|SPW|FSM|Add0~33_sumout ;wire \A_SPW_TOP|SPW|FSM|after128us~9_combout ;wire \A_SPW_TOP|SPW|FSM|Equal0~0_combout ;wire \A_SPW_TOP|SPW|FSM|LessThan0~0_combout ;wire \A_SPW_TOP|SPW|FSM|Add0~25_sumout ;wire \A_SPW_TOP|SPW|FSM|after128us~7_combout ;wire \A_SPW_TOP|SPW|FSM|Equal0~1_combout ;wire \A_SPW_TOP|SPW|FSM|Selector4~0_combout ;wire \A_SPW_TOP|SPW|FSM|Add0~34 ;wire \A_SPW_TOP|SPW|FSM|Add0~45_sumout ;wire \A_SPW_TOP|SPW|FSM|after128us~12_combout ;wire \A_SPW_TOP|SPW|FSM|Equal0~2_combout ;wire \A_SPW_TOP|SPW|FSM|Equal0~3_combout ;wire \A_SPW_TOP|SPW|FSM|Selector0~1_combout ;wire \A_SPW_TOP|SPW|FSM|Selector0~2_combout ;wire \A_SPW_TOP|SPW|FSM|got_bit_internal~0_combout ;wire \A_SPW_TOP|SPW|FSM|got_bit_internal~q ;wire \A_SPW_TOP|SPW|FSM|Add2~29_sumout ;wire \A_SPW_TOP|SPW|FSM|after850ns~7_combout ;wire \A_SPW_TOP|SPW|FSM|Add2~30 ;wire \A_SPW_TOP|SPW|FSM|Add2~25_sumout ;wire \A_SPW_TOP|SPW|FSM|after850ns~6_combout ;wire \A_SPW_TOP|SPW|FSM|Add2~26 ;wire \A_SPW_TOP|SPW|FSM|Add2~22 ;wire \A_SPW_TOP|SPW|FSM|Add2~9_sumout ;wire \A_SPW_TOP|SPW|FSM|after850ns~2_combout ;wire \A_SPW_TOP|SPW|FSM|Add2~10 ;wire \A_SPW_TOP|SPW|FSM|Add2~17_sumout ;wire \A_SPW_TOP|SPW|FSM|after850ns~4_combout ;wire \A_SPW_TOP|SPW|FSM|Add2~18 ;wire \A_SPW_TOP|SPW|FSM|Add2~5_sumout ;wire \A_SPW_TOP|SPW|FSM|after850ns~1_combout ;wire \A_SPW_TOP|SPW|FSM|Add2~6 ;wire \A_SPW_TOP|SPW|FSM|Add2~13_sumout ;wire \A_SPW_TOP|SPW|FSM|after850ns~3_combout ;wire \A_SPW_TOP|SPW|FSM|LessThan2~1_combout ;wire \A_SPW_TOP|SPW|FSM|Add2~14 ;wire \A_SPW_TOP|SPW|FSM|Add2~33_sumout ;wire \A_SPW_TOP|SPW|FSM|after850ns~8_combout ;wire \A_SPW_TOP|SPW|FSM|Add2~34 ;wire \A_SPW_TOP|SPW|FSM|Add2~37_sumout ;wire \A_SPW_TOP|SPW|FSM|after850ns~9_combout ;wire \A_SPW_TOP|SPW|FSM|Add2~38 ;wire \A_SPW_TOP|SPW|FSM|Add2~41_sumout ;wire \A_SPW_TOP|SPW|FSM|after850ns~10_combout ;wire \A_SPW_TOP|SPW|FSM|Add2~42 ;wire \A_SPW_TOP|SPW|FSM|Add2~45_sumout ;wire \A_SPW_TOP|SPW|FSM|after850ns~11_combout ;wire \A_SPW_TOP|SPW|FSM|Equal1~1_combout ;wire \A_SPW_TOP|SPW|FSM|always5~1_combout ;wire \A_SPW_TOP|SPW|FSM|Add2~21_sumout ;wire \A_SPW_TOP|SPW|FSM|after850ns~5_combout ;wire \A_SPW_TOP|SPW|FSM|LessThan2~0_combout ;wire \A_SPW_TOP|SPW|FSM|always5~0_combout ;wire \A_SPW_TOP|SPW|FSM|Add2~46 ;wire \A_SPW_TOP|SPW|FSM|Add2~1_sumout ;wire \A_SPW_TOP|SPW|FSM|after850ns~0_combout ;wire \A_SPW_TOP|SPW|FSM|Equal1~0_combout ;wire \A_SPW_TOP|SPW|FSM|Equal1~2_combout ;wire \A_SPW_TOP|rx_data|credit_counter_write[0]~0_combout ;wire \A_SPW_TOP|rx_data|Add2~2_combout ;wire \A_SPW_TOP|rx_data|Add2~1_combout ;wire \A_SPW_TOP|rx_data|credit_counter_reader~4_combout ;wire \A_SPW_TOP|rx_data|credit_counter_reader~3_combout ;wire \A_SPW_TOP|rx_data|credit_counter_reader~0_combout ;wire \A_SPW_TOP|rx_data|credit_counter_reader~1_combout ;wire \A_SPW_TOP|rx_data|Add2~0_combout ;wire \A_SPW_TOP|rx_data|Add5~14 ;wire \A_SPW_TOP|rx_data|Add5~15 ;wire \A_SPW_TOP|rx_data|Add5~10 ;wire \A_SPW_TOP|rx_data|Add5~11 ;wire \A_SPW_TOP|rx_data|Add5~6 ;wire \A_SPW_TOP|rx_data|Add5~7 ;wire \A_SPW_TOP|rx_data|Add5~1_sumout ;wire \A_SPW_TOP|rx_data|Add5~9_sumout ;wire \A_SPW_TOP|rx_data|Add5~13_sumout ;wire \A_SPW_TOP|rx_data|credit_counter_reader~6_combout ;wire \A_SPW_TOP|rx_data|credit_counter_reader~5_combout ;wire \A_SPW_TOP|rx_data|Add2~4_combout ;wire \A_SPW_TOP|rx_data|Add2~3_combout ;wire \A_SPW_TOP|rx_data|Add5~2 ;wire \A_SPW_TOP|rx_data|Add5~3 ;wire \A_SPW_TOP|rx_data|Add5~22 ;wire \A_SPW_TOP|rx_data|Add5~23 ;wire \A_SPW_TOP|rx_data|Add5~17_sumout ;wire \A_SPW_TOP|rx_data|Add5~21_sumout ;wire \A_SPW_TOP|rx_data|LessThan0~0_combout ;wire \A_SPW_TOP|rx_data|credit_counter_reader~2_combout ;wire \A_SPW_TOP|rx_data|Add5~5_sumout ;wire \A_SPW_TOP|rx_data|LessThan1~0_combout ;wire \A_SPW_TOP|rx_data|overflow_credit_error~q ;wire \A_SPW_TOP|SPW|FSM|Selector0~0_combout ;wire \A_SPW_TOP|SPW|FSM|state_fsm~13_combout ;wire \A_SPW_TOP|SPW|FSM|state_fsm~14_combout ;wire \A_SPW_TOP|SPW|FSM|state_fsm~15_combout ;wire \A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ;wire \A_SPW_TOP|SPW|FSM|Equal2~3_combout ;wire \A_SPW_TOP|SPW|FSM|Add1~5_sumout ;wire \A_SPW_TOP|SPW|FSM|after64us~2_combout ;wire \A_SPW_TOP|SPW|FSM|Add1~6 ;wire \A_SPW_TOP|SPW|FSM|Add1~10 ;wire \A_SPW_TOP|SPW|FSM|Add1~13_sumout ;wire \A_SPW_TOP|SPW|FSM|after64us~4_combout ;wire \A_SPW_TOP|SPW|FSM|Add1~14 ;wire \A_SPW_TOP|SPW|FSM|Add1~17_sumout ;wire \A_SPW_TOP|SPW|FSM|after64us~5_combout ;wire \A_SPW_TOP|SPW|FSM|Add1~18 ;wire \A_SPW_TOP|SPW|FSM|Add1~21_sumout ;wire \A_SPW_TOP|SPW|FSM|after64us~6_combout ;wire \A_SPW_TOP|SPW|FSM|Add1~22 ;wire \A_SPW_TOP|SPW|FSM|Add1~25_sumout ;wire \A_SPW_TOP|SPW|FSM|after64us~7_combout ;wire \A_SPW_TOP|SPW|FSM|Add1~26 ;wire \A_SPW_TOP|SPW|FSM|Add1~2 ;wire \A_SPW_TOP|SPW|FSM|Add1~34 ;wire \A_SPW_TOP|SPW|FSM|Add1~38 ;wire \A_SPW_TOP|SPW|FSM|Add1~30 ;wire \A_SPW_TOP|SPW|FSM|Add1~41_sumout ;wire \A_SPW_TOP|SPW|FSM|after64us~11_combout ;wire \A_SPW_TOP|SPW|FSM|Add1~42 ;wire \A_SPW_TOP|SPW|FSM|Add1~45_sumout ;wire \A_SPW_TOP|SPW|FSM|after64us~12_combout ;wire \A_SPW_TOP|SPW|FSM|after64us~0_combout ;wire \A_SPW_TOP|SPW|FSM|Add1~9_sumout ;wire \A_SPW_TOP|SPW|FSM|after64us~3_combout ;wire \A_SPW_TOP|SPW|FSM|Equal2~0_combout ;wire \A_SPW_TOP|SPW|FSM|Add1~29_sumout ;wire \A_SPW_TOP|SPW|FSM|after64us~8_combout ;wire \A_SPW_TOP|SPW|FSM|Add1~37_sumout ;wire \A_SPW_TOP|SPW|FSM|after64us~10_combout ;wire \A_SPW_TOP|SPW|FSM|Equal2~2_combout ;wire \A_SPW_TOP|SPW|FSM|Add1~1_sumout ;wire \A_SPW_TOP|SPW|FSM|after64us~1_combout ;wire \A_SPW_TOP|SPW|FSM|Add1~33_sumout ;wire \A_SPW_TOP|SPW|FSM|after64us~9_combout ;wire \A_SPW_TOP|SPW|FSM|Equal2~1_combout ;wire \A_SPW_TOP|SPW|FSM|rx_resetn~0_combout ;wire \A_SPW_TOP|SPW|FSM|rx_resetn~q ;wire \A_SPW_TOP|SPW|RX|WideOr7~0_combout ;wire \A_SPW_TOP|SPW|RX|Selector2~0_combout ;wire \A_SPW_TOP|SPW|RX|Selector3~0_combout ;wire \A_SPW_TOP|SPW|RX|Selector3~1_combout ;wire \A_SPW_TOP|SPW|RX|Selector2~1_combout ;wire \A_SPW_TOP|SPW|RX|Selector0~0_combout ;wire \A_SPW_TOP|SPW|RX|Selector4~0_combout ;wire \A_SPW_TOP|SPW|RX|Selector1~0_combout ;wire \A_SPW_TOP|SPW|RX|Selector1~1_combout ;wire \A_SPW_TOP|SPW|RX|Selector0~2_combout ;wire \A_SPW_TOP|SPW|RX|Selector5~0_combout ;wire \A_SPW_TOP|SPW|RX|Selector5~1_combout ;wire \A_SPW_TOP|SPW|RX|always1~0_combout ;wire \A_SPW_TOP|SPW|RX|ready_control_p_r~0_combout ;wire \A_SPW_TOP|SPW|RX|ready_control_p_r~q ;wire \A_SPW_TOP|SPW|RX|last_is_data~0_combout ;wire \A_SPW_TOP|SPW|RX|last_is_data~q ;wire \A_SPW_TOP|SPW|RX|rx_got_nchar~0_combout ;wire \A_SPW_TOP|SPW|RX|rx_got_nchar~feeder_combout ;wire \A_SPW_TOP|SPW|RX|rx_got_nchar~q ;wire \A_SPW_TOP|SPW|FSM|state_fsm~24_combout ;wire \A_SPW_TOP|SPW|FSM|state_fsm~22_combout ;wire \A_SPW_TOP|SPW|FSM|state_fsm~23_combout ;wire \A_SPW_TOP|SPW|FSM|state_fsm~25_combout ;wire \A_SPW_TOP|SPW|FSM|state_fsm~19_combout ;wire \A_SPW_TOP|SPW|FSM|state_fsm.run~q ;wire \A_SPW_TOP|SPW|FSM|state_fsm.error_reset~0_combout ;wire \A_SPW_TOP|SPW|FSM|state_fsm~11_combout ;wire \A_SPW_TOP|SPW|FSM|state_fsm~12_combout ;wire \A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q ;wire \A_SPW_TOP|SPW|FSM|WideOr0~combout ;wire \A_SPW_TOP|SPW|FSM|send_null_tx~q ;wire \A_SPW_TOP|SPW|TX|Selector63~3_combout ;wire \A_SPW_TOP|SPW|TX|Selector64~0_combout ;wire \A_SPW_TOP|SPW|TX|Equal0~4_combout ;wire \A_SPW_TOP|SPW|TX|Selector73~1_combout ;wire \A_SPW_TOP|SPW|TX|Selector60~0_combout ;wire \A_SPW_TOP|SPW|TX|ready_tx_data~q ;wire \A_SPW_TOP|tx_data|state_data_read~13_combout ;wire \A_SPW_TOP|tx_data|state_data_read.11~q ;wire \A_SPW_TOP|tx_data|state_data_read~12_combout ;wire \A_SPW_TOP|tx_data|state_data_read.10~q ;wire \A_SPW_TOP|tx_data|always3~0_combout ;wire \A_SPW_TOP|tx_data|Add2~2_combout ;wire \A_SPW_TOP|tx_data|Add2~3_combout ;wire \A_SPW_TOP|tx_data|Add3~17_sumout ;wire \A_SPW_TOP|tx_data|Equal0~0_combout ;wire \A_SPW_TOP|tx_data|f_full~q ;wire \u0|mm_interconnect_0|cmd_mux_011|src_payload~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|write_en_tx|always0~0_combout ;wire \u0|write_en_tx|data_out~q ;wire \A_SPW_TOP|tx_data|state_data_write~7_combout ;wire \A_SPW_TOP|tx_data|state_data_write.00~q ;wire \A_SPW_TOP|tx_data|state_data_write~8_combout ;wire \A_SPW_TOP|tx_data|state_data_write.01~q ;wire \A_SPW_TOP|tx_data|state_data_write~9_combout ;wire \A_SPW_TOP|tx_data|state_data_write.10~q ;wire \A_SPW_TOP|tx_data|Add1~0_combout ;wire \A_SPW_TOP|tx_data|Add3~5_sumout ;wire \u0|counter_tx_fifo|read_mux_out[1]~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][1]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][1]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~35_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][1]~q ;wire \u0|fsm_info|read_mux_out[1]~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][1]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~34_combout ;wire \u0|counter_rx_fifo|read_mux_out[1]~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][1]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][1]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~36_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][1]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][1]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~242_combout ;wire \m_x|rx_got_time_code~1_combout ;wire \m_x|rx_got_time_code~q ;wire \u0|mm_interconnect_0|cmd_mux|src_payload~1_combout ;wire \u0|led_pio_test|data_out[1]~_Duplicate_1feeder_combout ;wire \u0|led_pio_test|data_out[1]~_Duplicate_1_q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][1]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][1]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~30_combout ;wire \A_SPW_TOP|SPW|RX|timecode~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][1]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][1]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~31_combout ;wire \A_SPW_TOP|SPW|RX|rx_data_flag~1_combout ;wire \A_SPW_TOP|rx_data|Selector494~0_combout ;wire \A_SPW_TOP|rx_data|mem[52][1]~q ;wire \A_SPW_TOP|rx_data|Selector215~0_combout ;wire \A_SPW_TOP|rx_data|mem[21][1]~q ;wire \A_SPW_TOP|rx_data|Selector503~0_combout ;wire \A_SPW_TOP|rx_data|mem[53][1]~q ;wire \A_SPW_TOP|rx_data|Selector206~0_combout ;wire \A_SPW_TOP|rx_data|mem[20][1]~q ;wire \A_SPW_TOP|rx_data|Mux7~15_combout ;wire \A_SPW_TOP|rx_data|Selector566~0_combout ;wire \A_SPW_TOP|rx_data|mem[60][1]~q ;wire \A_SPW_TOP|rx_data|Selector278~0_combout ;wire \A_SPW_TOP|rx_data|mem[28][1]~q ;wire \A_SPW_TOP|rx_data|Selector287~0_combout ;wire \A_SPW_TOP|rx_data|mem[29][1]~q ;wire \A_SPW_TOP|rx_data|Selector575~0_combout ;wire \A_SPW_TOP|rx_data|mem[61][1]~q ;wire \A_SPW_TOP|rx_data|Mux7~16_combout ;wire \A_SPW_TOP|rx_data|Selector512~0_combout ;wire \A_SPW_TOP|rx_data|mem[54][1]~q ;wire \A_SPW_TOP|rx_data|Selector224~0_combout ;wire \A_SPW_TOP|rx_data|mem[22][1]~q ;wire \A_SPW_TOP|rx_data|Selector521~0_combout ;wire \A_SPW_TOP|rx_data|mem[55][1]~q ;wire \A_SPW_TOP|rx_data|Selector233~0_combout ;wire \A_SPW_TOP|rx_data|mem[23][1]~q ;wire \A_SPW_TOP|rx_data|Mux7~17_combout ;wire \A_SPW_TOP|rx_data|Selector584~0_combout ;wire \A_SPW_TOP|rx_data|mem[62][1]~q ;wire \A_SPW_TOP|rx_data|Selector593~0_combout ;wire \A_SPW_TOP|rx_data|mem[63][1]~q ;wire \A_SPW_TOP|rx_data|Selector305~0_combout ;wire \A_SPW_TOP|rx_data|mem[31][1]~q ;wire \A_SPW_TOP|rx_data|Selector296~0_combout ;wire \A_SPW_TOP|rx_data|mem[30][1]~q ;wire \A_SPW_TOP|rx_data|Mux7~18_combout ;wire \A_SPW_TOP|rx_data|Mux7~19_combout ;wire \A_SPW_TOP|rx_data|Selector152~0_combout ;wire \A_SPW_TOP|rx_data|mem[14][1]~q ;wire \A_SPW_TOP|rx_data|Selector134~0_combout ;wire \A_SPW_TOP|rx_data|mem[12][1]~q ;wire \A_SPW_TOP|rx_data|Selector161~0_combout ;wire \A_SPW_TOP|rx_data|mem[15][1]~q ;wire \A_SPW_TOP|rx_data|Selector143~0_combout ;wire \A_SPW_TOP|rx_data|mem[13][1]~q ;wire \A_SPW_TOP|rx_data|Mux7~11_combout ;wire \A_SPW_TOP|rx_data|Selector431~0_combout ;wire \A_SPW_TOP|rx_data|mem[45][1]~q ;wire \A_SPW_TOP|rx_data|Selector422~0_combout ;wire \A_SPW_TOP|rx_data|mem[44][1]~q ;wire \A_SPW_TOP|rx_data|Selector449~0_combout ;wire \A_SPW_TOP|rx_data|mem[47][1]~q ;wire \A_SPW_TOP|rx_data|Selector440~0_combout ;wire \A_SPW_TOP|rx_data|mem[46][1]~q ;wire \A_SPW_TOP|rx_data|Mux7~13_combout ;wire \A_SPW_TOP|rx_data|Selector359~0_combout ;wire \A_SPW_TOP|rx_data|mem[37][1]~q ;wire \A_SPW_TOP|rx_data|Selector368~0_combout ;wire \A_SPW_TOP|rx_data|mem[38][1]~q ;wire \A_SPW_TOP|rx_data|Selector350~0_combout ;wire \A_SPW_TOP|rx_data|mem[36][1]~q ;wire \A_SPW_TOP|rx_data|Selector377~0_combout ;wire \A_SPW_TOP|rx_data|mem[39][1]~q ;wire \A_SPW_TOP|rx_data|Mux7~12_combout ;wire \A_SPW_TOP|rx_data|Selector80~0_combout ;wire \A_SPW_TOP|rx_data|mem[6][1]~q ;wire \A_SPW_TOP|rx_data|Selector62~0_combout ;wire \A_SPW_TOP|rx_data|mem[4][1]~q ;wire \A_SPW_TOP|rx_data|Selector89~0_combout ;wire \A_SPW_TOP|rx_data|mem[7][1]~q ;wire \A_SPW_TOP|rx_data|Selector71~0_combout ;wire \A_SPW_TOP|rx_data|mem[5][1]~q ;wire \A_SPW_TOP|rx_data|Mux7~10_combout ;wire \A_SPW_TOP|rx_data|Mux7~14_combout ;wire \A_SPW_TOP|rx_data|Selector539~0_combout ;wire \A_SPW_TOP|rx_data|mem[57][1]~q ;wire \A_SPW_TOP|rx_data|Selector530~0_combout ;wire \A_SPW_TOP|rx_data|mem[56][1]~q ;wire \A_SPW_TOP|rx_data|Selector548~0_combout ;wire \A_SPW_TOP|rx_data|mem[58][1]~q ;wire \A_SPW_TOP|rx_data|Selector557~0_combout ;wire \A_SPW_TOP|rx_data|mem[59][1]~q ;wire \A_SPW_TOP|rx_data|Mux7~8_combout ;wire \A_SPW_TOP|rx_data|Selector269~0_combout ;wire \A_SPW_TOP|rx_data|mem[27][1]~q ;wire \A_SPW_TOP|rx_data|Selector242~0_combout ;wire \A_SPW_TOP|rx_data|mem[24][1]~q ;wire \A_SPW_TOP|rx_data|Selector251~0_combout ;wire \A_SPW_TOP|rx_data|mem[25][1]~q ;wire \A_SPW_TOP|rx_data|Selector260~0_combout ;wire \A_SPW_TOP|rx_data|mem[26][1]~q ;wire \A_SPW_TOP|rx_data|Mux7~6_combout ;wire \A_SPW_TOP|rx_data|Selector170~0_combout ;wire \A_SPW_TOP|rx_data|mem[16][1]~q ;wire \A_SPW_TOP|rx_data|Selector188~0_combout ;wire \A_SPW_TOP|rx_data|mem[18][1]~q ;wire \A_SPW_TOP|rx_data|Selector197~0_combout ;wire \A_SPW_TOP|rx_data|mem[19][1]~q ;wire \A_SPW_TOP|rx_data|Selector179~0_combout ;wire \A_SPW_TOP|rx_data|mem[17][1]~q ;wire \A_SPW_TOP|rx_data|Mux7~5_combout ;wire \A_SPW_TOP|rx_data|Selector467~0_combout ;wire \A_SPW_TOP|rx_data|mem[49][1]~q ;wire \A_SPW_TOP|rx_data|Selector485~0_combout ;wire \A_SPW_TOP|rx_data|mem[51][1]~q ;wire \A_SPW_TOP|rx_data|Selector458~0_combout ;wire \A_SPW_TOP|rx_data|mem[48][1]~q ;wire \A_SPW_TOP|rx_data|Selector476~0_combout ;wire \A_SPW_TOP|rx_data|mem[50][1]~q ;wire \A_SPW_TOP|rx_data|Mux7~7_combout ;wire \A_SPW_TOP|rx_data|Mux7~9_combout ;wire \A_SPW_TOP|rx_data|Selector116~0_combout ;wire \A_SPW_TOP|rx_data|mem[10][1]~q ;wire \A_SPW_TOP|rx_data|Selector125~0_combout ;wire \A_SPW_TOP|rx_data|mem[11][1]~q ;wire \A_SPW_TOP|rx_data|Selector98~0_combout ;wire \A_SPW_TOP|rx_data|mem[8][1]~q ;wire \A_SPW_TOP|rx_data|Mux7~1_combout ;wire \A_SPW_TOP|rx_data|Selector395~0_combout ;wire \A_SPW_TOP|rx_data|mem[41][1]~q ;wire \A_SPW_TOP|rx_data|Selector404~0_combout ;wire \A_SPW_TOP|rx_data|mem[42][1]~q ;wire \A_SPW_TOP|rx_data|Selector386~0_combout ;wire \A_SPW_TOP|rx_data|mem[40][1]~q ;wire \A_SPW_TOP|rx_data|Selector413~0_combout ;wire \A_SPW_TOP|rx_data|mem[43][1]~q ;wire \A_SPW_TOP|rx_data|Mux7~3_combout ;wire \A_SPW_TOP|rx_data|Selector44~0_combout ;wire \A_SPW_TOP|rx_data|mem[2][1]~q ;wire \A_SPW_TOP|rx_data|Selector35~0_combout ;wire \A_SPW_TOP|rx_data|mem[1][1]~q ;wire \A_SPW_TOP|rx_data|Selector53~0_combout ;wire \A_SPW_TOP|rx_data|mem[3][1]~q ;wire \A_SPW_TOP|rx_data|Selector26~0_combout ;wire \A_SPW_TOP|rx_data|mem[0][1]~q ;wire \A_SPW_TOP|rx_data|Mux7~0_combout ;wire \A_SPW_TOP|rx_data|Selector332~0_combout ;wire \A_SPW_TOP|rx_data|mem[34][1]~q ;wire \A_SPW_TOP|rx_data|Selector314~0_combout ;wire \A_SPW_TOP|rx_data|mem[32][1]~q ;wire \A_SPW_TOP|rx_data|Selector341~0_combout ;wire \A_SPW_TOP|rx_data|mem[35][1]~q ;wire \A_SPW_TOP|rx_data|Selector323~0_combout ;wire \A_SPW_TOP|rx_data|mem[33][1]~q ;wire \A_SPW_TOP|rx_data|Mux7~2_combout ;wire \A_SPW_TOP|rx_data|Mux7~4_combout ;wire \A_SPW_TOP|rx_data|Mux7~20_combout ;wire \A_SPW_TOP|rx_data|Selector107~0_combout ;wire \A_SPW_TOP|rx_data|mem[9][1]~q ;wire \A_SPW_TOP|rx_data|Mux16~7_combout ;wire \A_SPW_TOP|rx_data|Mux16~5_combout ;wire \A_SPW_TOP|rx_data|Mux16~6_combout ;wire \A_SPW_TOP|rx_data|Mux16~8_combout ;wire \A_SPW_TOP|rx_data|Mux16~9_combout ;wire \A_SPW_TOP|rx_data|Mux16~13_combout ;wire \A_SPW_TOP|rx_data|Mux16~10_combout ;wire \A_SPW_TOP|rx_data|Mux16~11_combout ;wire \A_SPW_TOP|rx_data|Mux16~12_combout ;wire \A_SPW_TOP|rx_data|Mux16~14_combout ;wire \A_SPW_TOP|rx_data|Mux16~16_combout ;wire \A_SPW_TOP|rx_data|Mux16~18_combout ;wire \A_SPW_TOP|rx_data|Mux16~15_combout ;wire \A_SPW_TOP|rx_data|Mux16~17_combout ;wire \A_SPW_TOP|rx_data|Mux16~19_combout ;wire \A_SPW_TOP|rx_data|Mux16~3_combout ;wire \A_SPW_TOP|rx_data|Mux16~2_combout ;wire \A_SPW_TOP|rx_data|Mux16~0_combout ;wire \A_SPW_TOP|rx_data|Mux16~1_combout ;wire \A_SPW_TOP|rx_data|Mux16~4_combout ;wire \A_SPW_TOP|rx_data|Mux16~20_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][1]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][1]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~32_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~33_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][1]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][1]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~37_combout ;wire \u0|mm_interconnect_0|cmd_mux_018|src_payload~1_combout ;wire \u0|clock_sel|readdata[1]~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][1]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][1]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~38_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~39_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][1]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][1]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~238_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|auto_start|readdata[0]~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~0_combout ;wire \u0|counter_rx_fifo|read_mux_out[0]~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~3_combout ;wire \u0|mm_interconnect_0|rsp_demux_008|src1_valid~combout ;wire \u0|counter_tx_fifo|read_mux_out[0]~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~2_combout ;wire \u0|fsm_info|read_mux_out[0]~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~1_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~4_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][0]~q ;wire \A_SPW_TOP|SPW|RX|rx_data_flag~12_combout ;wire \A_SPW_TOP|rx_data|Selector486~0_combout ;wire \A_SPW_TOP|rx_data|mem[51][0]~q ;wire \A_SPW_TOP|rx_data|Selector522~0_combout ;wire \A_SPW_TOP|rx_data|mem[55][0]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[55][0]~q ;wire \A_SPW_TOP|rx_data|Selector342~0_combout ;wire \A_SPW_TOP|rx_data|mem[35][0]~q ;wire \A_SPW_TOP|rx_data|Mux8~13_combout ;wire \A_SPW_TOP|rx_data|Selector477~0_combout ;wire \A_SPW_TOP|rx_data|mem[50][0]~q ;wire \A_SPW_TOP|rx_data|Selector369~0_combout ;wire \A_SPW_TOP|rx_data|mem[38][0]~q ;wire \A_SPW_TOP|rx_data|Selector513~0_combout ;wire \A_SPW_TOP|rx_data|mem[54][0]~q ;wire \A_SPW_TOP|rx_data|Selector333~0_combout ;wire \A_SPW_TOP|rx_data|mem[34][0]~q ;wire \A_SPW_TOP|rx_data|Mux8~12_combout ;wire \A_SPW_TOP|rx_data|Selector459~0_combout ;wire \A_SPW_TOP|rx_data|mem[48][0]~q ;wire \A_SPW_TOP|rx_data|Selector495~0_combout ;wire \A_SPW_TOP|rx_data|mem[52][0]~q ;wire \A_SPW_TOP|rx_data|Selector351~0_combout ;wire \A_SPW_TOP|rx_data|mem[36][0]~q ;wire \A_SPW_TOP|rx_data|Selector315~0_combout ;wire \A_SPW_TOP|rx_data|mem[32][0]~q ;wire \A_SPW_TOP|rx_data|Mux8~10_combout ;wire \A_SPW_TOP|rx_data|Selector324~0_combout ;wire \A_SPW_TOP|rx_data|mem[33][0]~q ;wire \A_SPW_TOP|rx_data|Selector504~0_combout ;wire \A_SPW_TOP|rx_data|mem[53][0]~q ;wire \A_SPW_TOP|rx_data|Selector468~0_combout ;wire \A_SPW_TOP|rx_data|mem[49][0]~q ;wire \A_SPW_TOP|rx_data|Selector360~0_combout ;wire \A_SPW_TOP|rx_data|mem[37][0]~q ;wire \A_SPW_TOP|rx_data|Mux8~11_combout ;wire \A_SPW_TOP|rx_data|Mux8~14_combout ;wire \A_SPW_TOP|rx_data|Selector423~0_combout ;wire \A_SPW_TOP|rx_data|mem[44][0]~q ;wire \A_SPW_TOP|rx_data|Selector567~0_combout ;wire \A_SPW_TOP|rx_data|mem[60][0]~q ;wire \A_SPW_TOP|rx_data|Selector441~0_combout ;wire \A_SPW_TOP|rx_data|mem[46][0]~q ;wire \A_SPW_TOP|rx_data|Selector585~0_combout ;wire \A_SPW_TOP|rx_data|mem[62][0]~q ;wire \A_SPW_TOP|rx_data|Mux8~17_combout ;wire \A_SPW_TOP|rx_data|Selector387~0_combout ;wire \A_SPW_TOP|rx_data|mem[40][0]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[40][0]~q ;wire \A_SPW_TOP|rx_data|Selector549~0_combout ;wire \A_SPW_TOP|rx_data|mem[58][0]~q ;wire \A_SPW_TOP|rx_data|Selector405~0_combout ;wire \A_SPW_TOP|rx_data|mem[42][0]~q ;wire \A_SPW_TOP|rx_data|Selector531~0_combout ;wire \A_SPW_TOP|rx_data|mem[56][0]~q ;wire \A_SPW_TOP|rx_data|Mux8~15_combout ;wire \A_SPW_TOP|rx_data|Selector396~0_combout ;wire \A_SPW_TOP|rx_data|mem[41][0]~q ;wire \A_SPW_TOP|rx_data|Selector414~0_combout ;wire \A_SPW_TOP|rx_data|mem[43][0]~q ;wire \A_SPW_TOP|rx_data|Selector558~0_combout ;wire \A_SPW_TOP|rx_data|mem[59][0]~q ;wire \A_SPW_TOP|rx_data|Selector540~0_combout ;wire \A_SPW_TOP|rx_data|mem[57][0]~q ;wire \A_SPW_TOP|rx_data|Mux8~16_combout ;wire \A_SPW_TOP|rx_data|Selector450~0_combout ;wire \A_SPW_TOP|rx_data|mem[47][0]~q ;wire \A_SPW_TOP|rx_data|Selector594~0_combout ;wire \A_SPW_TOP|rx_data|mem[63][0]~q ;wire \A_SPW_TOP|rx_data|Selector432~0_combout ;wire \A_SPW_TOP|rx_data|mem[45][0]~q ;wire \A_SPW_TOP|rx_data|Selector576~0_combout ;wire \A_SPW_TOP|rx_data|mem[61][0]~q ;wire \A_SPW_TOP|rx_data|Mux8~18_combout ;wire \A_SPW_TOP|rx_data|Mux8~19_combout ;wire \A_SPW_TOP|rx_data|Selector144~0_combout ;wire \A_SPW_TOP|rx_data|mem[13][0]~q ;wire \A_SPW_TOP|rx_data|Selector108~0_combout ;wire \A_SPW_TOP|rx_data|mem[9][0]~q ;wire \A_SPW_TOP|rx_data|Selector252~0_combout ;wire \A_SPW_TOP|rx_data|mem[25][0]~q ;wire \A_SPW_TOP|rx_data|Selector288~0_combout ;wire \A_SPW_TOP|rx_data|mem[29][0]~q ;wire \A_SPW_TOP|rx_data|Mux8~6_combout ;wire \A_SPW_TOP|rx_data|Selector261~0_combout ;wire \A_SPW_TOP|rx_data|mem[26][0]~q ;wire \A_SPW_TOP|rx_data|Selector117~0_combout ;wire \A_SPW_TOP|rx_data|mem[10][0]~q ;wire \A_SPW_TOP|rx_data|Selector153~0_combout ;wire \A_SPW_TOP|rx_data|mem[14][0]~q ;wire \A_SPW_TOP|rx_data|Selector297~0_combout ;wire \A_SPW_TOP|rx_data|mem[30][0]~q ;wire \A_SPW_TOP|rx_data|Mux8~7_combout ;wire \A_SPW_TOP|rx_data|Selector243~0_combout ;wire \A_SPW_TOP|rx_data|mem[24][0]~q ;wire \A_SPW_TOP|rx_data|Selector99~0_combout ;wire \A_SPW_TOP|rx_data|mem[8][0]~q ;wire \A_SPW_TOP|rx_data|Selector279~0_combout ;wire \A_SPW_TOP|rx_data|mem[28][0]~q ;wire \A_SPW_TOP|rx_data|Selector135~0_combout ;wire \A_SPW_TOP|rx_data|mem[12][0]~q ;wire \A_SPW_TOP|rx_data|Mux8~5_combout ;wire \A_SPW_TOP|rx_data|Selector126~0_combout ;wire \A_SPW_TOP|rx_data|mem[11][0]~q ;wire \A_SPW_TOP|rx_data|Selector270~0_combout ;wire \A_SPW_TOP|rx_data|mem[27][0]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[27][0]~q ;wire \A_SPW_TOP|rx_data|Selector306~0_combout ;wire \A_SPW_TOP|rx_data|mem[31][0]~q ;wire \A_SPW_TOP|rx_data|Selector162~0_combout ;wire \A_SPW_TOP|rx_data|mem[15][0]~q ;wire \A_SPW_TOP|rx_data|Mux8~8_combout ;wire \A_SPW_TOP|rx_data|Mux8~9_combout ;wire \A_SPW_TOP|rx_data|Selector207~0_combout ;wire \A_SPW_TOP|rx_data|mem[20][0]~q ;wire \A_SPW_TOP|rx_data|Selector63~0_combout ;wire \A_SPW_TOP|rx_data|mem[4][0]~q ;wire \A_SPW_TOP|rx_data|Selector171~0_combout ;wire \A_SPW_TOP|rx_data|mem[16][0]~q ;wire \A_SPW_TOP|rx_data|Selector27~0_combout ;wire \A_SPW_TOP|rx_data|mem[0][0]~q ;wire \A_SPW_TOP|rx_data|Mux8~0_combout ;wire \A_SPW_TOP|rx_data|Selector54~0_combout ;wire \A_SPW_TOP|rx_data|mem[3][0]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[3][0]~q ;wire \A_SPW_TOP|rx_data|Selector234~0_combout ;wire \A_SPW_TOP|rx_data|mem[23][0]~q ;wire \A_SPW_TOP|rx_data|Selector90~0_combout ;wire \A_SPW_TOP|rx_data|mem[7][0]~q ;wire \A_SPW_TOP|rx_data|Selector198~0_combout ;wire \A_SPW_TOP|rx_data|mem[19][0]~q ;wire \A_SPW_TOP|rx_data|Mux8~3_combout ;wire \A_SPW_TOP|rx_data|Selector45~0_combout ;wire \A_SPW_TOP|rx_data|mem[2][0]~q ;wire \A_SPW_TOP|rx_data|Selector189~0_combout ;wire \A_SPW_TOP|rx_data|mem[18][0]~q ;wire \A_SPW_TOP|rx_data|Selector81~0_combout ;wire \A_SPW_TOP|rx_data|mem[6][0]~q ;wire \A_SPW_TOP|rx_data|Selector225~0_combout ;wire \A_SPW_TOP|rx_data|mem[22][0]~q ;wire \A_SPW_TOP|rx_data|Mux8~2_combout ;wire \A_SPW_TOP|rx_data|Selector36~0_combout ;wire \A_SPW_TOP|rx_data|mem[1][0]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[1][0]~q ;wire \A_SPW_TOP|rx_data|Selector180~0_combout ;wire \A_SPW_TOP|rx_data|mem[17][0]~q ;wire \A_SPW_TOP|rx_data|Selector216~0_combout ;wire \A_SPW_TOP|rx_data|mem[21][0]~q ;wire \A_SPW_TOP|rx_data|Selector72~0_combout ;wire \A_SPW_TOP|rx_data|mem[5][0]~q ;wire \A_SPW_TOP|rx_data|Mux8~1_combout ;wire \A_SPW_TOP|rx_data|Mux8~4_combout ;wire \A_SPW_TOP|rx_data|Mux8~20_combout ;wire \A_SPW_TOP|rx_data|Selector378~0_combout ;wire \A_SPW_TOP|rx_data|mem[39][0]~q ;wire \A_SPW_TOP|rx_data|Mux17~3_combout ;wire \A_SPW_TOP|rx_data|Mux17~2_combout ;wire \A_SPW_TOP|rx_data|Mux17~0_combout ;wire \A_SPW_TOP|rx_data|Mux17~1_combout ;wire \A_SPW_TOP|rx_data|Mux17~4_combout ;wire \A_SPW_TOP|rx_data|Mux17~16_combout ;wire \A_SPW_TOP|rx_data|Mux17~18_combout ;wire \A_SPW_TOP|rx_data|Mux17~17_combout ;wire \A_SPW_TOP|rx_data|Mux17~15_combout ;wire \A_SPW_TOP|rx_data|Mux17~19_combout ;wire \A_SPW_TOP|rx_data|Mux17~13_combout ;wire \A_SPW_TOP|rx_data|Mux17~10_combout ;wire \A_SPW_TOP|rx_data|Mux17~12_combout ;wire \A_SPW_TOP|rx_data|Mux17~11_combout ;wire \A_SPW_TOP|rx_data|Mux17~14_combout ;wire \A_SPW_TOP|rx_data|Mux17~7_combout ;wire \A_SPW_TOP|rx_data|Mux17~8_combout ;wire \A_SPW_TOP|rx_data|Mux17~6_combout ;wire \A_SPW_TOP|rx_data|Mux17~5_combout ;wire \A_SPW_TOP|rx_data|Mux17~9_combout ;wire \A_SPW_TOP|rx_data|Mux17~20_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~13_combout ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~14_combout ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~15_combout ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~16_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~18_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~17_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~13_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \A_SPW_TOP|SPW|RX|rx_tick_out~0_combout ;wire \A_SPW_TOP|SPW|RX|rx_tick_out~feeder_combout ;wire \A_SPW_TOP|SPW|RX|rx_tick_out~q ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~12_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|timecode_ready_rx|read_mux_out~combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~17_combout ;wire \u0|mm_interconnect_0|cmd_mux|src_payload~0_combout ;wire \u0|led_pio_test|data_out[0]~_Duplicate_1_q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~15_combout ;wire \A_SPW_TOP|SPW|RX|timecode~1_combout ;wire \A_SPW_TOP|SPW|RX|timecode[0]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][0]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~16_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~18_combout ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~12_combout ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~14_combout ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~16_combout ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~15_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~13_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~17_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~18_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder_combout ;wire \u0|fifo_full_rx_status|read_mux_out~combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~20_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|data_read_en_rx|readdata[0]~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[0][0]~feeder_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~19_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~14_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~16_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~15_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~17_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~18_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~13_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~12_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|fifo_full_tx_status|read_mux_out~combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~22_combout ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~14_combout ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~16_combout ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~15_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~13_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~17_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~18_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~12_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|fifo_empty_rx_status|read_mux_out~combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~21_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~23_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~13_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~14_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~15_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~16_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~17_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~18_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~12_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector61~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector61~1_combout ;wire \A_SPW_TOP|SPW|TX|ready_tx_timecode~q ;wire \u0|timecode_tx_ready|read_mux_out~combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~26_combout ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~12_combout ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~14_combout ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~15_combout ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~16_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~13_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~17_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~18_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|fifo_empty_tx_status|read_mux_out~combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~25_combout ;wire \u0|link_start|readdata[0]~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~24_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~27_combout ;wire \m_x|rx_got_fct~0_combout ;wire \m_x|rx_got_fct~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~14_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~28_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|write_en_tx|readdata[0]~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~7_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~8_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~9_combout ;wire \u0|timecode_tx_enable|readdata[0]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~10_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|clock_sel|readdata[0]~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~11_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~12_combout ;wire \u0|link_disable|readdata[0]~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[0][0]~feeder_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~5_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~6_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~29_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~21_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116]~feeder_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ;wire \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[116]~56_combout ;wire \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[116]~59_combout ;wire \u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[116]~55_combout ;wire \u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[116]~58_combout ;wire \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[116]~57_combout ;wire \u0|mm_interconnect_0|router_001|Equal1~0_combout ;wire \u0|mm_interconnect_0|router_001|Equal21~0_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src15_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_015|update_grant~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_015|arb|grant[1]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][69]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][69]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][68]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][68]~q ;wire \u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout ;wire \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[115]~54_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[115]~51_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[115]~50_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[115]~53_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[115]~52_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|cmd_mux|update_grant~0_combout ;wire \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~2_combout ;wire \u0|mm_interconnect_0|cmd_mux|arb|grant[1]~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][69]~feeder_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][69]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][68]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][68]~q ;wire \u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ;wire \u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[114]~45_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[114]~47_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[114]~48_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[114]~46_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[114]~49_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_data[113]~44_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[113]~43_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[113]~40_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[113]~42_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[113]~41_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src0_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src0_valid~1_combout ;wire \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~0_combout ;wire \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~1_combout ;wire \u0|mm_interconnect_0|cmd_mux|arb|grant[0]~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_data[112]~35_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[112]~36_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[112]~38_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[112]~37_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[112]~39_combout ;wire \u0|mm_interconnect_0|router_001|Equal1~2_combout ;wire \u0|mm_interconnect_0|router_001|Equal3~0_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src10_valid~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_010|update_grant~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|arb|grant[1]~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_data[111]~32_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[111]~31_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[111]~30_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[111]~34_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[111]~33_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_data[110]~27_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[110]~29_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[110]~25_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[110]~26_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[110]~28_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~57_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector11~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout ;wire \u0|mm_interconnect_0|router|Equal13~0_combout ;wire \u0|mm_interconnect_0|cmd_demux|src7_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_007|arb|grant[0]~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_007|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_007|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_007|update_grant~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_data[109]~21_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[109]~20_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[109]~24_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[109]~22_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[109]~23_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~45_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector14~0_combout ;wire \u0|mm_interconnect_0|router|Equal7~0_combout ;wire \u0|mm_interconnect_0|router|Equal6~4_combout ;wire \u0|mm_interconnect_0|router|Equal6~1_combout ;wire \u0|mm_interconnect_0|router|Equal6~2_combout ;wire \u0|mm_interconnect_0|router|Equal6~3_combout ;wire \u0|mm_interconnect_0|router|Equal7~1_combout ;wire \u0|mm_interconnect_0|router|Equal16~0_combout ;wire \u0|mm_interconnect_0|cmd_demux|src10_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|arb|grant[0]~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][68]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][68]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][69]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][69]~q ;wire \u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout ;wire \u0|mm_interconnect_0|rsp_demux_010|WideOr0~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_data[108]~17_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[108]~15_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[108]~18_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[108]~19_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[108]~16_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_write~combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[107]~12_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[107]~10_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[107]~13_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[107]~14_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[107]~11_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106]~feeder_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_data[106]~5_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[106]~6_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[106]~8_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[106]~7_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[106]~9_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ;wire \u0|mm_interconnect_0|cmd_demux|src8_valid~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_008|arb|grant[0]~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent|local_write~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_data[105]~1_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[105]~0_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[105]~2_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[105]~4_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[105]~3_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~6 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~1_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~5_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[5]~4_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~1_combout ;wire \u0|mm_interconnect_0|router|Equal6~0_combout ;wire \u0|mm_interconnect_0|router|Equal6~6_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|cmd_demux|sink_ready~0_combout ;wire \u0|mm_interconnect_0|cmd_demux|sink_ready~7_combout ;wire \u0|mm_interconnect_0|cmd_demux|sink_ready~3_combout ;wire \u0|mm_interconnect_0|cmd_demux|sink_ready~4_combout ;wire \u0|mm_interconnect_0|cmd_demux|WideOr0~1_combout ;wire \u0|mm_interconnect_0|cmd_demux|sink_ready~5_combout ;wire \u0|mm_interconnect_0|cmd_demux|sink_ready~6_combout ;wire \u0|mm_interconnect_0|cmd_demux|WideOr0~2_combout ;wire \u0|mm_interconnect_0|cmd_demux|sink_ready~9_combout ;wire \u0|mm_interconnect_0|cmd_demux|sink_ready~8_combout ;wire \u0|mm_interconnect_0|cmd_demux|WideOr0~3_combout ;wire \u0|mm_interconnect_0|cmd_demux|WideOr0~4_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ;wire \u0|mm_interconnect_0|router|Equal6~8_combout ;wire \u0|mm_interconnect_0|cmd_demux|src18_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~4_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ;wire \u0|mm_interconnect_0|rsp_mux_001|WideOr1~0_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|WideOr1~1_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|WideOr1~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|rsp_mux_001|WideOr1~3_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|WideOr1~4_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|WideOr1~combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src7_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_007|arb|grant[1]~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~8_combout ;wire \u0|mm_interconnect_0|rsp_demux_004|src1_valid~combout ;wire \u0|mm_interconnect_0|rsp_demux_007|src1_valid~combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~7_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~6_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~2_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~3_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~5_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~4_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][130]~feeder_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~8_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~9_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~6_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~7_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][130]~feeder_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~10_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~11_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~4_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~5_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~12_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~13_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~14_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~15_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~24_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~25_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~26_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~27_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~22_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~23_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~18_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~19_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~20_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~21_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~16_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~17_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~28_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ;wire \u0|mm_interconnect_0|router|Equal21~0_combout ;wire \u0|mm_interconnect_0|cmd_demux|src15_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_015|arb|grant[0]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|cmd_demux|sink_ready~2_combout ;wire \u0|mm_interconnect_0|cmd_demux|sink_ready~1_combout ;wire \u0|mm_interconnect_0|cmd_demux|WideOr0~0_combout ;wire \u0|mm_interconnect_0|cmd_demux|sink_ready~10_combout ;wire \u0|mm_interconnect_0|cmd_demux|WideOr0~combout ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~9_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~10_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~12_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~11_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|next_pending_response_count~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|always1~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|next_pending_response_count~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~2_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ;wire \u0|mm_interconnect_0|router|src_data[103]~1_combout ;wire \u0|mm_interconnect_0|router|src_data~2_combout ;wire \u0|mm_interconnect_0|router|src_data[101]~5_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~1_combout ;wire \u0|mm_interconnect_0|router|src_data~4_combout ;wire \u0|mm_interconnect_0|router|src_data[104]~6_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~2_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~3_combout ;wire \u0|mm_interconnect_0|router|src_data[102]~3_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ;wire \u0|mm_interconnect_0|router|Equal14~0_combout ;wire \u0|mm_interconnect_0|router|Equal17~0_combout ;wire \u0|mm_interconnect_0|cmd_demux|src11_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_011|arb|grant[0]~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|m0_write~combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~4_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][69]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][69]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][68]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][68]~q ;wire \u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout ;wire \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ;wire \u0|mm_interconnect_0|rsp_mux|WideOr1~1_combout ;wire \u0|mm_interconnect_0|rsp_mux|WideOr1~0_combout ;wire \u0|mm_interconnect_0|rsp_mux|WideOr1~combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~0_combout ;wire \u0|mm_interconnect_0|router_001|Equal5~0_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~9_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~10_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~11_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~5_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~0_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~0_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~8_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~4_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~5_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~7_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~6_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~3_combout ;wire \u0|mm_interconnect_0|router_001|Equal6~0_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~4_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~3_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~2_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~2_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~1_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~1_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~6_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~13_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~16_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~7_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~15_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~14_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~12_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~17_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~8_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~9_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted~combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|next_pending_response_count~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|always1~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|next_pending_response_count~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~2_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~2_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|cmd_sink_ready~0_combout ;wire \u0|mm_interconnect_0|router_001|Equal6~1_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src18_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src18_valid~1_combout ;wire \u0|mm_interconnect_0|cmd_demux|src18_valid~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_018|arb|grant[1]~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_018|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_018|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_018|update_grant~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_018|arb|grant[0]~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_018|src_payload~0_combout ;wire \u0|clock_sel|data_out[0]~feeder_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~41_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~34 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~38 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~26 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~29_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~41_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~44_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~42_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~88_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~22 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~1_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~13_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~16_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~14_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~2 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~5_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~18_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~20_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~17_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~64_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~61_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~62_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~6 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~13_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~26_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~28_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~25_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~69_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~72_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~70_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~71_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Mux3~4_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~27_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Mux3~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~4_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|always4~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~63_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Mux4~4_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~19_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Mux4~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~2_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~12_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~57_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~60_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~58_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~59_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Mux5~4_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~15_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Mux5~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~1_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~85_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~86_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~87_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Mux7~4_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~43_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Mux7~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~8_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~30 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~21_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~34_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~77_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~80_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~78_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~79_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Mux6~4_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~36_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~33_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~35_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Mux6~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~6_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~98_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~100_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~97_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~99_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Mux11~4_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~54_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~56_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~53_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~55_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Mux11~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~11_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~42 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~33_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~46_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~90_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~92_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~89_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~91_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Mux10~4_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~48_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~45_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~47_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Mux10~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~9_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~14 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~17_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~30_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~32_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~29_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~76_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~73_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~74_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~75_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Mux2~4_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~31_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Mux2~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~5_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~18 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~9_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|Equal2~1_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~21_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~24_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~22_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~68_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~65_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~66_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~67_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Mux1~4_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~23_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Mux1~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~3_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~37_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~96_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~94_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~93_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~95_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Mux9~4_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~52_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~49_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~50_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~51_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Mux9~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~10_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~25_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~38_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~37_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~40_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~84_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~81_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~82_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~83_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Mux8~4_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~39_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Mux8~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~7_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~1_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~4_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~7_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~5_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|LessThan0~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~6_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Mux0~4_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~3_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~2_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Mux0~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ;wire \A_SPW_TOP|SPW|TX|last_tx_sout~q ;wire \A_SPW_TOP|SPW|TX|last_tx_dout~q ;wire \A_SPW_TOP|SPW|TX|tx_sout~0_combout ;wire \A_SPW_TOP|SPW|TX|tx_sout_e~q ;wire \db_system_spwulight_b|PB_down~0_combout ;wire \db_system_spwulight_b|PB_down~q ;wire [10:0] \A_SPW_TOP|rx_data|counter_wait ;wire [9:0] \m_x|dta_timec_p ;wire [2:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [2:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [1:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|aligned_address_bits ;wire [3:0] \m_x|control_p_r ;wire [9:0] \m_x|data ;wire [9:0] \m_x|dta_timec ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [6:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [2:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [29:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [2:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [29:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [5:0] \m_x|counter_neg ;wire [29:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [5:0] \A_SPW_TOP|SPW|RX|counter_neg ;wire [6:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [29:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [3:0] \A_SPW_TOP|SPW|RX|control_p_r ;wire [2:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [6:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [29:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [6:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [29:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [2:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [2:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [2:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [2:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [6:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [5:0] \A_SPW_TOP|rx_data|counter_reader ;wire [5:0] \A_SPW_TOP|rx_data|counter_writer ;wire [6:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [29:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [5:0] \A_SPW_TOP|tx_data|counter_reader ;wire [5:0] \A_SPW_TOP|tx_data|counter_writer ;wire [6:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [6:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [3:0] \A_SPW_TOP|SPW|RX|control_r ;wire [2:0] \A_SPW_TOP|SPW|TX|fct_flag ;wire [3:0] \m_x|control_l_r ;wire [3:0] \m_x|control ;wire [29:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [29:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [6:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [29:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [6:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [29:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [6:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [29:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [3:0] \A_SPW_TOP|SPW|RX|control ;wire [6:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [6:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [29:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [6:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [29:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [5:0] \A_SPW_TOP|rx_data|rd_ptr ;wire [6:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [29:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [29:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [29:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [29:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [29:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [6:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [29:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [29:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [6:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [29:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [6:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [29:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [6:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [10:0] \R_400_to_2_5_10_100_200_300MHZ|counter_100 ;wire [11:0] \A_SPW_TOP|SPW|FSM|after850ns ;wire [2:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [11:0] \A_SPW_TOP|SPW|FSM|after128us ;wire [8:0] \A_SPW_TOP|tx_data|data_out ;wire [152:0] \u0|mm_interconnect_0|rsp_mux_001|src_payload ;wire [1:0] \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used ;wire [1:0] \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used ;wire [0:0] \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg ;wire [29:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [8:0] \u0|write_data_fifo_tx|data_out ;wire [6:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [0:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg ;wire [29:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [1:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used ;wire [7:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [3:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [3:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [152:0] \u0|mm_interconnect_0|cmd_mux_009|src_payload ;wire [1:0] \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used ;wire [7:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [6:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [1:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used ;wire [3:0] \u0|hps_0|fpga_interfaces|h2f_WSTRB ;wire [5:0] \A_SPW_TOP|rx_data|credit_counter ;wire [1:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used ;wire [29:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [2:0] \u0|hps_0|fpga_interfaces|h2f_AWSIZE ;wire [1:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used ;wire [5:0] \A_SPW_TOP|tx_data|wr_ptr ;wire [128:0] \u0|mm_interconnect_0|cmd_mux_009|src_data ;wire [31:0] \u0|fifo_empty_tx_status|readdata ;wire [29:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [0:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg ;wire [6:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [7:0] \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [4:0] \u0|led_pio_test|data_out ;wire [0:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg ;wire [1:0] \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used ;wire [3:0] \u0|hps_0|fpga_interfaces|h2f_AWLEN ;wire [7:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [3:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [7:0] \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [3:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [7:0] \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [128:0] \u0|mm_interconnect_0|cmd_mux_010|src_data ;wire [6:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [0:0] \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg ;wire [29:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [29:0] \u0|hps_0|fpga_interfaces|h2f_AWADDR ;wire [1:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used ;wire [3:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [1:0] \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter ;wire [6:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [0:0] \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg ;wire [1:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count ;wire [0:0] \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg ;wire [7:0] \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [1:0] \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used ;wire [152:0] \u0|mm_interconnect_0|cmd_mux_007|src_payload ;wire [6:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_008|saved_grant ;wire [128:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [0:0] \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg ;wire [1:0] \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter ;wire [1:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used ;wire [2:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [7:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [128:0] \u0|mm_interconnect_0|rsp_mux_001|src_data ;wire [128:0] \u0|mm_interconnect_0|rsp_mux|src_data ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_007|saved_grant ;wire [29:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [3:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [29:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [31:0] \u0|fifo_full_tx_status|readdata ;wire [128:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [1:0] \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter ;wire [7:0] \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [3:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [0:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg ;wire [2:0] \u0|hps_0|fpga_interfaces|h2f_ARSIZE ;wire [128:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [2:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_021|saved_grant ;wire [1:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_010|saved_grant ;wire [1:0] \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [128:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [7:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [31:0] \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre ;wire [29:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [29:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [1:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter ;wire [0:0] \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg ;wire [3:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [3:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [29:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [6:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_015|saved_grant ;wire [11:0] \u0|hps_0|fpga_interfaces|h2f_ARID ;wire [5:0] \A_SPW_TOP|tx_data|rd_ptr ;wire [29:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [128:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [3:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [1:0] \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used ;wire [1:0] \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_002|saved_grant ;wire [1:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used ;wire [6:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [1:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_001|saved_grant ;wire [1:0] \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg ;wire [6:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [29:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [1:0] \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [0:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg ;wire [7:0] \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus ;wire [0:0] \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg ;wire [1:0] \u0|hps_0|fpga_interfaces|h2f_ARBURST ;wire [2:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [3:0] \m_x|control_r ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_017|saved_grant ;wire [31:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|av_readdata_pre ;wire [6:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [29:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [7:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [0:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_004|saved_grant ;wire [2:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [1:0] \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used ;wire [6:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [29:0] \u0|hps_0|fpga_interfaces|h2f_ARADDR ;wire [29:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [128:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [1:0] \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used ;wire [3:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [6:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [1:0] \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used ;wire [0:0] \u0|hps_0|fpga_interfaces|h2f_ARVALID ;wire [6:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [31:0] \u0|mm_interconnect_0|link_start_s1_translator|av_readdata_pre ;wire [1:0] \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used ;wire [31:0] \u0|led_pio_test|readdata ;wire [7:0] \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph ;wire [0:0] \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg ;wire [3:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [6:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [8:0] \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shiften ;wire [2:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [1:0] \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [1:0] \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter ;wire [3:0] \u0|hps_0|fpga_interfaces|h2f_ARLEN ;wire [0:0] \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg ;wire [29:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [29:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [31:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre ;wire [0:0] \u0|hps_0|fpga_interfaces|h2f_WLAST ;wire [31:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|av_readdata_pre ;wire [1:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter ;wire [6:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [0:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg ;wire [0:0] \u0|pll_0|altera_pll_i|cyclonev_pll|divclk ;wire [29:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [1:0] \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter ;wire [1:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used ;wire [6:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [29:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [0:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg ;wire [7:0] \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [31:0] \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre ;wire [0:0] \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg ;wire [4:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id ;wire [4:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id ;wire [2:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_011|saved_grant ;wire [21:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_012|saved_grant ;wire [29:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [1:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used ;wire [152:0] \u0|mm_interconnect_0|cmd_mux_010|src_payload ;wire [6:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [1:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter ;wire [1:0] \u0|hps_0|fpga_interfaces|h2f_AWBURST ;wire [1:0] \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used ;wire [29:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [7:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [128:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [7:0] \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg ;wire [3:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [1:0] \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter ;wire [128:0] \u0|mm_interconnect_0|cmd_mux_011|src_data ;wire [0:0] \u0|hps_0|fpga_interfaces|h2f_RREADY ;wire [128:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [29:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [7:0] \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [1:0] \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used ;wire [1:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used ;wire [1:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter ;wire [7:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [29:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [3:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [1:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used ;wire [1:0] \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used ;wire [6:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [6:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [1:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter ;wire [2:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [6:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_018|saved_grant ;wire [1:0] \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter ;wire [5:0] \A_SPW_TOP|SPW|TX|fct_counter_receive ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [1:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter ;wire [6:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [1:0] \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used ;wire [128:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [7:0] \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [9:0] \A_SPW_TOP|SPW|RX|dta_timec_p ;wire [128:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [1:0] \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used ;wire [0:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg ;wire [6:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [1:0] \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter ;wire [10:0] \R_400_to_2_5_10_100_200_300MHZ|counter ;wire [6:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [128:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [3:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [29:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [6:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_013|saved_grant ;wire [128:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [1:0] \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter ;wire [1:0] \u0|mm_interconnect_0|cmd_mux|saved_grant ;wire [1:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_006|saved_grant ;wire [3:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [128:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [6:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [6:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [31:0] \u0|hps_0|fpga_interfaces|h2f_WDATA ;wire [2:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [1:0] \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used ;wire [6:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [0:0] \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg ;wire [1:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used ;wire [1:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used ;wire [128:0] \u0|mm_interconnect_0|cmd_mux|src_data ;wire [0:0] \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg ;wire [8:0] \A_SPW_TOP|SPW|TX|tx_data_in_0 ;wire [1:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter ;wire [29:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [3:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [7:0] \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [1:0] \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used ;wire [1:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter ;wire [11:0] \u0|hps_0|fpga_interfaces|h2f_AWID ;wire [2:0] \A_SPW_TOP|SPW|TX|fct_flag_p ;wire [1:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used ;wire [128:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [31:0] \u0|write_data_fifo_tx|readdata ;wire [31:0] \u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre ;wire [3:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [152:0] \u0|mm_interconnect_0|cmd_mux_018|src_payload ;wire [31:0] \u0|timecode_rx|readdata ;wire [1:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_019|saved_grant ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_003|saved_grant ;wire [1:0] \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter ;wire [128:0] \u0|mm_interconnect_0|cmd_mux_014|src_data ;wire [1:0] \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_020|saved_grant ;wire [152:0] \u0|mm_interconnect_0|cmd_mux|src_payload ;wire [7:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [7:0] \A_SPW_TOP|SPW|TX|tx_tcode_in ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_014|saved_grant ;wire [1:0] \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter ;wire [7:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [128:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [3:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_016|saved_grant ;wire [128:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_005|saved_grant ;wire [31:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre ;wire [31:0] \u0|mm_interconnect_0|link_disable_s1_translator|av_readdata_pre ;wire [6:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [29:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [31:0] \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre ;wire [1:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used ;wire [31:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|av_readdata_pre ;wire [29:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [31:0] \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre ;wire [0:0] \u0|hps_0|fpga_interfaces|h2f_WVALID ;wire [31:0] \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre ;wire [0:0] \u0|hps_0|fpga_interfaces|h2f_AWVALID ;wire [31:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|av_readdata_pre ;wire [31:0] \u0|mm_interconnect_0|data_read_en_rx_s1_translator|av_readdata_pre ;wire [6:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [0:0] \u0|pll_0|altera_pll_i|cyclonev_pll|cascade_wire ;wire [31:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|av_readdata_pre ;wire [31:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|av_readdata_pre ;wire [1:0] \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fboutclk_wire ;wire [31:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|av_readdata_pre ;wire [1:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used ;wire [15:0] \db_system_spwulight_b|counter ;wire [6:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [1:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count ;wire [21:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel ;wire [6:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [6:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [128:0] \u0|mm_interconnect_0|cmd_mux_004|src_data ;wire [6:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [152:0] \u0|mm_interconnect_0|cmd_mux_004|src_payload ;wire [1:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used ;wire [6:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [29:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [6:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [6:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [6:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [6:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount ;wire [31:0] \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [152:0] \u0|mm_interconnect_0|cmd_mux_014|src_payload ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [2:0] \u0|clock_sel|data_out ;wire [29:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [128:0] \u0|mm_interconnect_0|cmd_mux_015|src_data ;wire [29:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [6:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [152:0] \u0|mm_interconnect_0|cmd_mux_015|src_payload ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [6:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [152:0] \u0|mm_interconnect_0|cmd_mux_011|src_payload ;wire [3:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [29:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [6:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg ;wire [6:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg ;wire [6:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [128:0] \u0|mm_interconnect_0|cmd_mux_018|src_data ;wire [8:0] \A_SPW_TOP|SPW|TX|tx_data_in ;wire [29:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [6:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [128:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [128:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [8:0] \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last ;wire [6:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [8:0] \A_SPW_TOP|SPW|RX|rx_data_flag ;wire [6:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [3:0] \A_SPW_TOP|SPW|RX|control_l_r ;wire [6:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [2:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [6:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [7:0] \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [6:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [6:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [128:0] \u0|mm_interconnect_0|cmd_mux_007|src_data ;wire [6:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [128:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [6:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [5:0] \A_SPW_TOP|rx_data|wr_ptr ;wire [128:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [6:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [2:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [13:0] \A_SPW_TOP|SPW|TX|timecode_s ;wire [31:0] \u0|timecode_tx_data|readdata ;wire [0:0] \u0|hps_0|fpga_interfaces|h2f_rst_n ;wire [6:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [0:0] \u0|hps_0|fpga_interfaces|h2f_BREADY ;wire [0:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg ;wire [6:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [1:0] \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used ;wire [128:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [2:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [6:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [6:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [2:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [6:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [6:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [6:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [29:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg ;wire [29:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg ;wire [29:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [5:0] \A_SPW_TOP|rx_data|credit_counter_reader ;wire [8:0] \u0|data_flag_rx|read_mux_out ;wire [31:0] \u0|mm_interconnect_0|write_en_tx_s1_translator|av_readdata_pre ;wire [6:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [5:0] \A_SPW_TOP|SPW|TX|fct_counter_p ;wire [3:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [128:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [31:0] \u0|mm_interconnect_0|auto_start_s1_translator|av_readdata_pre ;wire [7:0] \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [6:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [6:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [6:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [6:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [29:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [128:0] \u0|mm_interconnect_0|cmd_mux_008|src_data ;wire [152:0] \u0|mm_interconnect_0|cmd_mux_008|src_payload ;wire [6:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg ;wire [29:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [31:0] \u0|fsm_info|readdata ;wire [9:0] \A_SPW_TOP|SPW|RX|data ;wire [31:0] \u0|counter_tx_fifo|readdata ;wire [6:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [31:0] \u0|counter_rx_fifo|readdata ;wire [29:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [29:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [5:0] \A_SPW_TOP|rx_data|credit_counter_write ;wire [31:0] \u0|data_flag_rx|readdata ;wire [1:0] \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used ;wire [31:0] \u0|data_info|readdata ;wire [29:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [31:0] \u0|timecode_ready_rx|readdata ;wire [29:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [31:0] \u0|fifo_full_rx_status|readdata ;wire [31:0] \u0|fifo_empty_rx_status|readdata ;wire [29:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [3:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [31:0] \u0|timecode_tx_ready|readdata ;wire [3:0] \A_SPW_TOP|SPW|TX|global_counter_transfer ;wire [7:0] \u0|timecode_tx_data|data_out ;wire [7:0] \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx ;wire [29:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [1:0] \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain ;wire [1:0] \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain ;wire [29:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [6:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [29:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_009|saved_grant ;wire [5:0] \A_SPW_TOP|tx_data|counter ;wire [5:0] \A_SPW_TOP|rx_data|counter ;wire [13:0] \u0|data_info|read_mux_out ;wire [29:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [29:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [11:0] \A_SPW_TOP|SPW|FSM|after64us ;wire [29:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [31:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [6:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [29:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [6:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [1:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used ;wire [8:0] \A_SPW_TOP|rx_data|data_out ;wire [13:0] \m_x|info ;wire [7:0] \u0|timecode_rx|read_mux_out ;wire [29:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [6:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [1:0] \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used ;wire [9:0] \A_SPW_TOP|SPW|RX|timecode ;wire [9:0] \A_SPW_TOP|SPW|RX|dta_timec ;wire [6:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [29:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg ;wire [29:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [3:0] \u0|hps_0|fpga_interfaces|f2sdram_BONDING_OUT_1_bus ;wire [31:0] \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus ;wire [29:0] \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus ;wire [1:0] \u0|hps_0|fpga_interfaces|hps2fpga_ARBURST_bus ;wire [11:0] \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus ;wire [3:0] \u0|hps_0|fpga_interfaces|hps2fpga_ARLEN_bus ;wire [2:0] \u0|hps_0|fpga_interfaces|hps2fpga_ARSIZE_bus ;wire [29:0] \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus ;wire [1:0] \u0|hps_0|fpga_interfaces|hps2fpga_AWBURST_bus ;wire [11:0] \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus ;wire [3:0] \u0|hps_0|fpga_interfaces|hps2fpga_AWLEN_bus ;wire [2:0] \u0|hps_0|fpga_interfaces|hps2fpga_AWSIZE_bus ;wire [127:0] \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus ;wire [15:0] \u0|hps_0|fpga_interfaces|hps2fpga_WSTRB_bus ;wire [7:0] \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus ;wire [7:0] \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus ;wire [8:0] \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|PLL_RECONFIG_SHIFTEN_bus ;assign \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_10 = \u0|hps_0|fpga_interfaces|f2sdram_BONDING_OUT_1_bus [0];assign \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_11 = \u0|hps_0|fpga_interfaces|f2sdram_BONDING_OUT_1_bus [1];assign \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_12 = \u0|hps_0|fpga_interfaces|f2sdram_BONDING_OUT_1_bus [2];assign \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_13 = \u0|hps_0|fpga_interfaces|f2sdram_BONDING_OUT_1_bus [3];assign \u0|hps_0|fpga_interfaces|tpiu~trace_data = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [0];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA1 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [1];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA2 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [2];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA3 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [3];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA4 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [4];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA5 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [5];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA6 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [6];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA7 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [7];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA8 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [8];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA9 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [9];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA10 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [10];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA11 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [11];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA12 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [12];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA13 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [13];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA14 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [14];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA15 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [15];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA16 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [16];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA17 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [17];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA18 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [18];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA19 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [19];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA20 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [20];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA21 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [21];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA22 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [22];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA23 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [23];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA24 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [24];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA25 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [25];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA26 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [26];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA27 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [27];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA28 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [28];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA29 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [29];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA30 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [30];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA31 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [31];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [0] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [0];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [1] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [1];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [2] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [2];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [3] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [3];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [4] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [4];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [5] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [5];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [6] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [6];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [7] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [7];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [8] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [8];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [9] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [9];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [10] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [10];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [11] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [11];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [12] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [12];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [13] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [13];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [14] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [14];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [15] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [15];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [16] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [16];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [17] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [17];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [18] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [18];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [19] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [19];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [20] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [20];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [21] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [21];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [22] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [22];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [23] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [23];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [24] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [24];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [25] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [25];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [26] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [26];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [27] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [27];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [28] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [28];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [29] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [29];assign \u0|hps_0|fpga_interfaces|h2f_ARBURST [0] = \u0|hps_0|fpga_interfaces|hps2fpga_ARBURST_bus [0];assign \u0|hps_0|fpga_interfaces|h2f_ARBURST [1] = \u0|hps_0|fpga_interfaces|hps2fpga_ARBURST_bus [1];assign \u0|hps_0|fpga_interfaces|h2f_ARID [0] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [0];assign \u0|hps_0|fpga_interfaces|h2f_ARID [1] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [1];assign \u0|hps_0|fpga_interfaces|h2f_ARID [2] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [2];assign \u0|hps_0|fpga_interfaces|h2f_ARID [3] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [3];assign \u0|hps_0|fpga_interfaces|h2f_ARID [4] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [4];assign \u0|hps_0|fpga_interfaces|h2f_ARID [5] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [5];assign \u0|hps_0|fpga_interfaces|h2f_ARID [6] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [6];assign \u0|hps_0|fpga_interfaces|h2f_ARID [7] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [7];assign \u0|hps_0|fpga_interfaces|h2f_ARID [8] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [8];assign \u0|hps_0|fpga_interfaces|h2f_ARID [9] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [9];assign \u0|hps_0|fpga_interfaces|h2f_ARID [10] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [10];assign \u0|hps_0|fpga_interfaces|h2f_ARID [11] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [11];assign \u0|hps_0|fpga_interfaces|h2f_ARLEN [0] = \u0|hps_0|fpga_interfaces|hps2fpga_ARLEN_bus [0];assign \u0|hps_0|fpga_interfaces|h2f_ARLEN [1] = \u0|hps_0|fpga_interfaces|hps2fpga_ARLEN_bus [1];assign \u0|hps_0|fpga_interfaces|h2f_ARLEN [2] = \u0|hps_0|fpga_interfaces|hps2fpga_ARLEN_bus [2];assign \u0|hps_0|fpga_interfaces|h2f_ARLEN [3] = \u0|hps_0|fpga_interfaces|hps2fpga_ARLEN_bus [3];assign \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] = \u0|hps_0|fpga_interfaces|hps2fpga_ARSIZE_bus [0];assign \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] = \u0|hps_0|fpga_interfaces|hps2fpga_ARSIZE_bus [1];assign \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] = \u0|hps_0|fpga_interfaces|hps2fpga_ARSIZE_bus [2];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [0] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [0];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [1] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [1];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [2] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [2];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [3] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [3];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [4] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [4];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [5] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [5];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [6] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [6];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [7] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [7];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [8] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [8];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [9] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [9];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [10] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [10];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [11] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [11];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [12] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [12];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [13] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [13];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [14] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [14];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [15] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [15];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [16] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [16];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [17] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [17];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [18] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [18];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [19] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [19];assign \u0|hps_0|fpga_interfaces|h2f_AWBURST [0] = \u0|hps_0|fpga_interfaces|hps2fpga_AWBURST_bus [0];assign \u0|hps_0|fpga_interfaces|h2f_AWBURST [1] = \u0|hps_0|fpga_interfaces|hps2fpga_AWBURST_bus [1];assign \u0|hps_0|fpga_interfaces|h2f_AWID [0] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [0];assign \u0|hps_0|fpga_interfaces|h2f_AWID [1] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [1];assign \u0|hps_0|fpga_interfaces|h2f_AWID [2] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [2];assign \u0|hps_0|fpga_interfaces|h2f_AWID [3] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [3];assign \u0|hps_0|fpga_interfaces|h2f_AWID [4] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [4];assign \u0|hps_0|fpga_interfaces|h2f_AWID [5] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [5];assign \u0|hps_0|fpga_interfaces|h2f_AWID [6] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [6];assign \u0|hps_0|fpga_interfaces|h2f_AWID [7] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [7];assign \u0|hps_0|fpga_interfaces|h2f_AWID [8] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [8];assign \u0|hps_0|fpga_interfaces|h2f_AWID [9] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [9];assign \u0|hps_0|fpga_interfaces|h2f_AWID [10] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [10];assign \u0|hps_0|fpga_interfaces|h2f_AWID [11] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [11];assign \u0|hps_0|fpga_interfaces|h2f_AWLEN [0] = \u0|hps_0|fpga_interfaces|hps2fpga_AWLEN_bus [0];assign \u0|hps_0|fpga_interfaces|h2f_AWLEN [1] = \u0|hps_0|fpga_interfaces|hps2fpga_AWLEN_bus [1];assign \u0|hps_0|fpga_interfaces|h2f_AWLEN [2] = \u0|hps_0|fpga_interfaces|hps2fpga_AWLEN_bus [2];assign \u0|hps_0|fpga_interfaces|h2f_AWLEN [3] = \u0|hps_0|fpga_interfaces|hps2fpga_AWLEN_bus [3];assign \u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] = \u0|hps_0|fpga_interfaces|hps2fpga_AWSIZE_bus [0];assign \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] = \u0|hps_0|fpga_interfaces|hps2fpga_AWSIZE_bus [1];assign \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] = \u0|hps_0|fpga_interfaces|hps2fpga_AWSIZE_bus [2];assign \u0|hps_0|fpga_interfaces|h2f_WDATA [0] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [0];assign \u0|hps_0|fpga_interfaces|h2f_WDATA [1] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [1];assign \u0|hps_0|fpga_interfaces|h2f_WDATA [2] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [2];assign \u0|hps_0|fpga_interfaces|h2f_WDATA [3] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [3];assign \u0|hps_0|fpga_interfaces|h2f_WDATA [4] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [4];assign \u0|hps_0|fpga_interfaces|h2f_WDATA [5] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [5];assign \u0|hps_0|fpga_interfaces|h2f_WDATA [6] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [6];assign \u0|hps_0|fpga_interfaces|h2f_WDATA [7] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [7];assign \u0|hps_0|fpga_interfaces|h2f_WDATA [8] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [8];assign \u0|hps_0|fpga_interfaces|h2f_WSTRB [0] = \u0|hps_0|fpga_interfaces|hps2fpga_WSTRB_bus [0];assign \u0|hps_0|fpga_interfaces|h2f_WSTRB [1] = \u0|hps_0|fpga_interfaces|hps2fpga_WSTRB_bus [1];assign \u0|hps_0|fpga_interfaces|h2f_WSTRB [2] = \u0|hps_0|fpga_interfaces|hps2fpga_WSTRB_bus [2];assign \u0|hps_0|fpga_interfaces|h2f_WSTRB [3] = \u0|hps_0|fpga_interfaces|hps2fpga_WSTRB_bus [3];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [0] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [0];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [1] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [1];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [2] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [2];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [3] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [3];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [4] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [4];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [5] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [5];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [6] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [6];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [7] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [7];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [0] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [0];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [1] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [1];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [2] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [2];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [3] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [3];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [4] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [4];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [5] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [5];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [6] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [6];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [7] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [7];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shiften [2] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|PLL_RECONFIG_SHIFTEN_bus [2];// Location: IOOBUF_X53_Y0_N36cyclonev_io_obuf \sout_a~output (.i(\A_SPW_TOP|SPW|TX|tx_sout_e~q ),.oe(vcc),.dynamicterminationcontrol(gnd),.seriesterminationcontrol(16'b0000000000000000),.parallelterminationcontrol(16'b0000000000000000),.devoe(devoe),.o(sout_a),.obar(\sout_a(n) ));// synopsys translate_offdefparam \sout_a~output .bus_hold = "false";defparam \sout_a~output .open_drain_output = "false";defparam \sout_a~output .shift_series_termination_control = "false";// synopsys translate_on// Location: IOOBUF_X68_Y10_N96cyclonev_io_obuf \LED[5]~output (.i(\db_system_spwulight_b|PB_down~q ),.oe(vcc),.dynamicterminationcontrol(gnd),.seriesterminationcontrol(16'b0000000000000000),.parallelterminationcontrol(16'b0000000000000000),.devoe(devoe),.o(LED[5]),.obar());// synopsys translate_offdefparam \LED[5]~output .bus_hold = "false";defparam \LED[5]~output .open_drain_output = "false";defparam \LED[5]~output .shift_series_termination_control = "false";// synopsys translate_on// Location: IOOBUF_X68_Y13_N56cyclonev_io_obuf \LED[7]~output (.i(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),.oe(vcc),.dynamicterminationcontrol(gnd),.seriesterminationcontrol(16'b0000000000000000),.parallelterminationcontrol(16'b0000000000000000),.devoe(devoe),.o(LED[7]),.obar());// synopsys translate_offdefparam \LED[7]~output .bus_hold = "false";defparam \LED[7]~output .open_drain_output = "false";defparam \LED[7]~output .shift_series_termination_control = "false";// synopsys translate_on// Location: IOOBUF_X65_Y0_N36cyclonev_io_obuf \dout_a~output (.i(\A_SPW_TOP|SPW|TX|tx_dout_e~q ),.oe(vcc),.dynamicterminationcontrol(gnd),.seriesterminationcontrol(16'b0000000000000000),.parallelterminationcontrol(16'b0000000000000000),.devoe(devoe),.o(dout_a),.obar(\dout_a(n) ));// synopsys translate_offdefparam \dout_a~output .bus_hold = "false";defparam \dout_a~output .open_drain_output = "false";defparam \dout_a~output .shift_series_termination_control = "false";// synopsys translate_on// Location: IOOBUF_X68_Y12_N22cyclonev_io_obuf \LED[0]~output (.i(\u0|led_pio_test|data_out [0]),.oe(vcc),.dynamicterminationcontrol(gnd),.seriesterminationcontrol(16'b0000000000000000),.parallelterminationcontrol(16'b0000000000000000),.devoe(devoe),.o(LED[0]),.obar());// synopsys translate_offdefparam \LED[0]~output .bus_hold = "false";defparam \LED[0]~output .open_drain_output = "false";defparam \LED[0]~output .shift_series_termination_control = "false";// synopsys translate_on// Location: IOOBUF_X68_Y13_N39cyclonev_io_obuf \LED[1]~output (.i(\u0|led_pio_test|data_out [1]),.oe(vcc),.dynamicterminationcontrol(gnd),.seriesterminationcontrol(16'b0000000000000000),.parallelterminationcontrol(16'b0000000000000000),.devoe(devoe),.o(LED[1]),.obar());// synopsys translate_offdefparam \LED[1]~output .bus_hold = "false";defparam \LED[1]~output .open_drain_output = "false";defparam \LED[1]~output .shift_series_termination_control = "false";// synopsys translate_on// Location: IOOBUF_X68_Y13_N5cyclonev_io_obuf \LED[2]~output (.i(\u0|led_pio_test|data_out [2]),.oe(vcc),.dynamicterminationcontrol(gnd),.seriesterminationcontrol(16'b0000000000000000),.parallelterminationcontrol(16'b0000000000000000),.devoe(devoe),.o(LED[2]),.obar());// synopsys translate_offdefparam \LED[2]~output .bus_hold = "false";defparam \LED[2]~output .open_drain_output = "false";defparam \LED[2]~output .shift_series_termination_control = "false";// synopsys translate_on// Location: IOOBUF_X68_Y13_N22cyclonev_io_obuf \LED[3]~output (.i(\u0|led_pio_test|data_out [3]),.oe(vcc),.dynamicterminationcontrol(gnd),.seriesterminationcontrol(16'b0000000000000000),.parallelterminationcontrol(16'b0000000000000000),.devoe(devoe),.o(LED[3]),.obar());// synopsys translate_offdefparam \LED[3]~output .bus_hold = "false";defparam \LED[3]~output .open_drain_output = "false";defparam \LED[3]~output .shift_series_termination_control = "false";// synopsys translate_on// Location: IOOBUF_X68_Y10_N79cyclonev_io_obuf \LED[4]~output (.i(\u0|led_pio_test|data_out [4]),.oe(vcc),.dynamicterminationcontrol(gnd),.seriesterminationcontrol(16'b0000000000000000),.parallelterminationcontrol(16'b0000000000000000),.devoe(devoe),.o(LED[4]),.obar());// synopsys translate_offdefparam \LED[4]~output .bus_hold = "false";defparam \LED[4]~output .open_drain_output = "false";defparam \LED[4]~output .shift_series_termination_control = "false";// synopsys translate_on// Location: IOOBUF_X68_Y12_N5cyclonev_io_obuf \LED[6]~output (.i(gnd),.oe(vcc),.dynamicterminationcontrol(gnd),.seriesterminationcontrol(16'b0000000000000000),.parallelterminationcontrol(16'b0000000000000000),.devoe(devoe),.o(LED[6]),.obar());// synopsys translate_offdefparam \LED[6]~output .bus_hold = "false";defparam \LED[6]~output .open_drain_output = "false";defparam \LED[6]~output .shift_series_termination_control = "false";// synopsys translate_on// Location: IOIBUF_X38_Y0_N1cyclonev_io_ibuf \FPGA_CLK1_50~input (.i(FPGA_CLK1_50),.ibar(gnd),.dynamicterminationcontrol(gnd),.o(\FPGA_CLK1_50~input_o ));// synopsys translate_offdefparam \FPGA_CLK1_50~input .bus_hold = "false";defparam \FPGA_CLK1_50~input .simulate_z_as = "z";// synopsys translate_on// Location: PLLREFCLKSELECT_X68_Y7_N0cyclonev_pll_refclk_select \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT (.adjpllin(gnd),.cclk(gnd),.coreclkin(gnd),.extswitch(gnd),.iqtxrxclkin(gnd),.plliqclkin(gnd),.rxiqclkin(gnd),.clkin({gnd,gnd,gnd,\FPGA_CLK1_50~input_o }),.refiqclk(2'b00),.clk0bad(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|clk0bad ),.clk1bad(),.clkout(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|refclk_select_clkout_wire ),.extswitchbuf(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|refclk_select_extswitchbuf_wire ),.pllclksel());// synopsys translate_offdefparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_auto_clk_sw_en = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_clk_loss_edge = "both_edges";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_clk_loss_sw_en = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_clk_sw_dly = 0;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_clkin_0_src = "clk_0";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_clkin_1_src = "clk_1";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_manu_clk_sw_en = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_sw_refclk_src = "clk_0";// synopsys translate_on// Location: CLKCTRL_G5cyclonev_clkena \FPGA_CLK1_50~inputCLKENA0 (.inclk(\FPGA_CLK1_50~input_o ),.ena(vcc),.outclk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.enaout());// synopsys translate_offdefparam \FPGA_CLK1_50~inputCLKENA0 .clock_type = "global clock";defparam \FPGA_CLK1_50~inputCLKENA0 .disable_mode = "low";defparam \FPGA_CLK1_50~inputCLKENA0 .ena_register_mode = "always enabled";defparam \FPGA_CLK1_50~inputCLKENA0 .ena_register_power_up = "high";defparam \FPGA_CLK1_50~inputCLKENA0 .test_syn = "high";// synopsys translate_on// Location: IOIBUF_X46_Y0_N52cyclonev_io_ibuf \KEY[1]~input (.i(KEY[1]),.ibar(gnd),.dynamicterminationcontrol(gnd),.o(\KEY[1]~input_o ));// synopsys translate_offdefparam \KEY[1]~input .bus_hold = "false";defparam \KEY[1]~input .simulate_z_as = "z";// synopsys translate_on// Location: LABCELL_X46_Y1_N0cyclonev_lcell_comb \db_system_spwulight_b|Add0~61 (// Equation(s):// \db_system_spwulight_b|Add0~61_sumout = SUM(( \db_system_spwulight_b|counter [0] ) + ( VCC ) + ( !VCC ))// \db_system_spwulight_b|Add0~62 = CARRY(( \db_system_spwulight_b|counter [0] ) + ( VCC ) + ( !VCC )).dataa(gnd),.datab(gnd),.datac(!\db_system_spwulight_b|counter [0]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~61_sumout ),.cout(\db_system_spwulight_b|Add0~62 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~61 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~61 .lut_mask = 64'h0000000000000F0F;defparam \db_system_spwulight_b|Add0~61 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X46_Y1_N54cyclonev_lcell_comb \db_system_spwulight_b|counter~15 (// Equation(s):// \db_system_spwulight_b|counter~15_combout = ( \db_system_spwulight_b|counter [0] & ( \db_system_spwulight_b|Add0~61_sumout & ( !\KEY[1]~input_o ) ) ) # ( !\db_system_spwulight_b|counter [0] & ( \db_system_spwulight_b|Add0~61_sumout & (// (\db_system_spwulight_b|LessThan0~2_combout & (!\db_system_spwulight_b|counter [15] & (!\KEY[1]~input_o & !\db_system_spwulight_b|LessThan0~1_combout ))) ) ) ) # ( \db_system_spwulight_b|counter [0] & ( !\db_system_spwulight_b|Add0~61_sumout & (// (!\KEY[1]~input_o & ((!\db_system_spwulight_b|LessThan0~2_combout ) # ((\db_system_spwulight_b|LessThan0~1_combout ) # (\db_system_spwulight_b|counter [15])))) ) ) ).dataa(!\db_system_spwulight_b|LessThan0~2_combout ),.datab(!\db_system_spwulight_b|counter [15]),.datac(!\KEY[1]~input_o ),.datad(!\db_system_spwulight_b|LessThan0~1_combout ),.datae(!\db_system_spwulight_b|counter [0]),.dataf(!\db_system_spwulight_b|Add0~61_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~15_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~15 .extended_lut = "off";defparam \db_system_spwulight_b|counter~15 .lut_mask = 64'h0000B0F04000F0F0;defparam \db_system_spwulight_b|counter~15 .shared_arith = "off";// synopsys translate_on// Location: FF_X46_Y1_N56dffeas \db_system_spwulight_b|counter[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~15_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [0]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[0] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N3cyclonev_lcell_comb \db_system_spwulight_b|Add0~57 (// Equation(s):// \db_system_spwulight_b|Add0~57_sumout = SUM(( \db_system_spwulight_b|counter [1] ) + ( GND ) + ( \db_system_spwulight_b|Add0~62 ))// \db_system_spwulight_b|Add0~58 = CARRY(( \db_system_spwulight_b|counter [1] ) + ( GND ) + ( \db_system_spwulight_b|Add0~62 )).dataa(!\db_system_spwulight_b|counter [1]),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~62 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~57_sumout ),.cout(\db_system_spwulight_b|Add0~58 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~57 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~57 .lut_mask = 64'h0000FFFF00005555;defparam \db_system_spwulight_b|Add0~57 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X46_Y1_N51cyclonev_lcell_comb \db_system_spwulight_b|counter~14 (// Equation(s):// \db_system_spwulight_b|counter~14_combout = ( \db_system_spwulight_b|counter [1] & ( \db_system_spwulight_b|Add0~57_sumout & ( !\KEY[1]~input_o ) ) ) # ( !\db_system_spwulight_b|counter [1] & ( \db_system_spwulight_b|Add0~57_sumout & (// (\db_system_spwulight_b|LessThan0~2_combout & (!\db_system_spwulight_b|counter [15] & (!\db_system_spwulight_b|LessThan0~1_combout & !\KEY[1]~input_o ))) ) ) ) # ( \db_system_spwulight_b|counter [1] & ( !\db_system_spwulight_b|Add0~57_sumout & (// (!\KEY[1]~input_o & ((!\db_system_spwulight_b|LessThan0~2_combout ) # ((\db_system_spwulight_b|LessThan0~1_combout ) # (\db_system_spwulight_b|counter [15])))) ) ) ).dataa(!\db_system_spwulight_b|LessThan0~2_combout ),.datab(!\db_system_spwulight_b|counter [15]),.datac(!\db_system_spwulight_b|LessThan0~1_combout ),.datad(!\KEY[1]~input_o ),.datae(!\db_system_spwulight_b|counter [1]),.dataf(!\db_system_spwulight_b|Add0~57_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~14_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~14 .extended_lut = "off";defparam \db_system_spwulight_b|counter~14 .lut_mask = 64'h0000BF004000FF00;defparam \db_system_spwulight_b|counter~14 .shared_arith = "off";// synopsys translate_on// Location: FF_X46_Y1_N53dffeas \db_system_spwulight_b|counter[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~14_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [1]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[1] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N6cyclonev_lcell_comb \db_system_spwulight_b|Add0~53 (// Equation(s):// \db_system_spwulight_b|Add0~53_sumout = SUM(( \db_system_spwulight_b|counter [2] ) + ( GND ) + ( \db_system_spwulight_b|Add0~58 ))// \db_system_spwulight_b|Add0~54 = CARRY(( \db_system_spwulight_b|counter [2] ) + ( GND ) + ( \db_system_spwulight_b|Add0~58 )).dataa(gnd),.datab(gnd),.datac(!\db_system_spwulight_b|counter [2]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~58 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~53_sumout ),.cout(\db_system_spwulight_b|Add0~54 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~53 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~53 .lut_mask = 64'h0000FFFF00000F0F;defparam \db_system_spwulight_b|Add0~53 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X46_Y1_N48cyclonev_lcell_comb \db_system_spwulight_b|counter~13 (// Equation(s):// \db_system_spwulight_b|counter~13_combout = ( \db_system_spwulight_b|counter [2] & ( \db_system_spwulight_b|Add0~53_sumout & ( !\KEY[1]~input_o ) ) ) # ( !\db_system_spwulight_b|counter [2] & ( \db_system_spwulight_b|Add0~53_sumout & (// (\db_system_spwulight_b|LessThan0~2_combout & (!\db_system_spwulight_b|counter [15] & (!\KEY[1]~input_o & !\db_system_spwulight_b|LessThan0~1_combout ))) ) ) ) # ( \db_system_spwulight_b|counter [2] & ( !\db_system_spwulight_b|Add0~53_sumout & (// (!\KEY[1]~input_o & ((!\db_system_spwulight_b|LessThan0~2_combout ) # ((\db_system_spwulight_b|LessThan0~1_combout ) # (\db_system_spwulight_b|counter [15])))) ) ) ).dataa(!\db_system_spwulight_b|LessThan0~2_combout ),.datab(!\db_system_spwulight_b|counter [15]),.datac(!\KEY[1]~input_o ),.datad(!\db_system_spwulight_b|LessThan0~1_combout ),.datae(!\db_system_spwulight_b|counter [2]),.dataf(!\db_system_spwulight_b|Add0~53_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~13_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~13 .extended_lut = "off";defparam \db_system_spwulight_b|counter~13 .lut_mask = 64'h0000B0F04000F0F0;defparam \db_system_spwulight_b|counter~13 .shared_arith = "off";// synopsys translate_on// Location: FF_X46_Y1_N50dffeas \db_system_spwulight_b|counter[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~13_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [2]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[2] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N9cyclonev_lcell_comb \db_system_spwulight_b|Add0~49 (// Equation(s):// \db_system_spwulight_b|Add0~49_sumout = SUM(( \db_system_spwulight_b|counter [3] ) + ( GND ) + ( \db_system_spwulight_b|Add0~54 ))// \db_system_spwulight_b|Add0~50 = CARRY(( \db_system_spwulight_b|counter [3] ) + ( GND ) + ( \db_system_spwulight_b|Add0~54 )).dataa(gnd),.datab(gnd),.datac(!\db_system_spwulight_b|counter [3]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~54 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~49_sumout ),.cout(\db_system_spwulight_b|Add0~50 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~49 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~49 .lut_mask = 64'h0000FFFF00000F0F;defparam \db_system_spwulight_b|Add0~49 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X46_Y1_N57cyclonev_lcell_comb \db_system_spwulight_b|counter~12 (// Equation(s):// \db_system_spwulight_b|counter~12_combout = ( \db_system_spwulight_b|counter [3] & ( \db_system_spwulight_b|Add0~49_sumout & ( !\KEY[1]~input_o ) ) ) # ( !\db_system_spwulight_b|counter [3] & ( \db_system_spwulight_b|Add0~49_sumout & (// (\db_system_spwulight_b|LessThan0~2_combout & (!\db_system_spwulight_b|counter [15] & (!\db_system_spwulight_b|LessThan0~1_combout & !\KEY[1]~input_o ))) ) ) ) # ( \db_system_spwulight_b|counter [3] & ( !\db_system_spwulight_b|Add0~49_sumout & (// (!\KEY[1]~input_o & ((!\db_system_spwulight_b|LessThan0~2_combout ) # ((\db_system_spwulight_b|LessThan0~1_combout ) # (\db_system_spwulight_b|counter [15])))) ) ) ).dataa(!\db_system_spwulight_b|LessThan0~2_combout ),.datab(!\db_system_spwulight_b|counter [15]),.datac(!\db_system_spwulight_b|LessThan0~1_combout ),.datad(!\KEY[1]~input_o ),.datae(!\db_system_spwulight_b|counter [3]),.dataf(!\db_system_spwulight_b|Add0~49_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~12_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~12 .extended_lut = "off";defparam \db_system_spwulight_b|counter~12 .lut_mask = 64'h0000BF004000FF00;defparam \db_system_spwulight_b|counter~12 .shared_arith = "off";// synopsys translate_on// Location: FF_X46_Y1_N59dffeas \db_system_spwulight_b|counter[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~12_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [3]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[3] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N12cyclonev_lcell_comb \db_system_spwulight_b|Add0~37 (// Equation(s):// \db_system_spwulight_b|Add0~37_sumout = SUM(( \db_system_spwulight_b|counter [4] ) + ( GND ) + ( \db_system_spwulight_b|Add0~50 ))// \db_system_spwulight_b|Add0~38 = CARRY(( \db_system_spwulight_b|counter [4] ) + ( GND ) + ( \db_system_spwulight_b|Add0~50 )).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\db_system_spwulight_b|counter [4]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~50 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~37_sumout ),.cout(\db_system_spwulight_b|Add0~38 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~37 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~37 .lut_mask = 64'h0000FFFF000000FF;defparam \db_system_spwulight_b|Add0~37 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X46_Y1_N15cyclonev_lcell_comb \db_system_spwulight_b|Add0~41 (// Equation(s):// \db_system_spwulight_b|Add0~41_sumout = SUM(( \db_system_spwulight_b|counter [5] ) + ( GND ) + ( \db_system_spwulight_b|Add0~38 ))// \db_system_spwulight_b|Add0~42 = CARRY(( \db_system_spwulight_b|counter [5] ) + ( GND ) + ( \db_system_spwulight_b|Add0~38 )).dataa(!\db_system_spwulight_b|counter [5]),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~38 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~41_sumout ),.cout(\db_system_spwulight_b|Add0~42 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~41 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~41 .lut_mask = 64'h0000FFFF00005555;defparam \db_system_spwulight_b|Add0~41 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N39cyclonev_lcell_comb \db_system_spwulight_b|counter~10 (// Equation(s):// \db_system_spwulight_b|counter~10_combout = ( \db_system_spwulight_b|counter [5] & ( \db_system_spwulight_b|Add0~41_sumout & ( !\KEY[1]~input_o ) ) ) # ( !\db_system_spwulight_b|counter [5] & ( \db_system_spwulight_b|Add0~41_sumout & (// (!\db_system_spwulight_b|LessThan0~1_combout & (!\KEY[1]~input_o & (\db_system_spwulight_b|LessThan0~2_combout & !\db_system_spwulight_b|counter [15]))) ) ) ) # ( \db_system_spwulight_b|counter [5] & ( !\db_system_spwulight_b|Add0~41_sumout & (// (!\KEY[1]~input_o & (((!\db_system_spwulight_b|LessThan0~2_combout ) # (\db_system_spwulight_b|counter [15])) # (\db_system_spwulight_b|LessThan0~1_combout ))) ) ) ).dataa(!\db_system_spwulight_b|LessThan0~1_combout ),.datab(!\KEY[1]~input_o ),.datac(!\db_system_spwulight_b|LessThan0~2_combout ),.datad(!\db_system_spwulight_b|counter [15]),.datae(!\db_system_spwulight_b|counter [5]),.dataf(!\db_system_spwulight_b|Add0~41_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~10_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~10 .extended_lut = "off";defparam \db_system_spwulight_b|counter~10 .lut_mask = 64'h0000C4CC0800CCCC;defparam \db_system_spwulight_b|counter~10 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N41dffeas \db_system_spwulight_b|counter[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~10_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [5]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[5] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N18cyclonev_lcell_comb \db_system_spwulight_b|Add0~45 (// Equation(s):// \db_system_spwulight_b|Add0~45_sumout = SUM(( \db_system_spwulight_b|counter [6] ) + ( GND ) + ( \db_system_spwulight_b|Add0~42 ))// \db_system_spwulight_b|Add0~46 = CARRY(( \db_system_spwulight_b|counter [6] ) + ( GND ) + ( \db_system_spwulight_b|Add0~42 )).dataa(gnd),.datab(!\db_system_spwulight_b|counter [6]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~42 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~45_sumout ),.cout(\db_system_spwulight_b|Add0~46 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~45 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~45 .lut_mask = 64'h0000FFFF00003333;defparam \db_system_spwulight_b|Add0~45 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N18cyclonev_lcell_comb \db_system_spwulight_b|counter~11 (// Equation(s):// \db_system_spwulight_b|counter~11_combout = ( \db_system_spwulight_b|counter [6] & ( \db_system_spwulight_b|LessThan0~2_combout & ( (!\KEY[1]~input_o & (((\db_system_spwulight_b|counter [15]) # (\db_system_spwulight_b|Add0~45_sumout )) #// (\db_system_spwulight_b|LessThan0~1_combout ))) ) ) ) # ( !\db_system_spwulight_b|counter [6] & ( \db_system_spwulight_b|LessThan0~2_combout & ( (!\db_system_spwulight_b|LessThan0~1_combout & (\db_system_spwulight_b|Add0~45_sumout &// (!\db_system_spwulight_b|counter [15] & !\KEY[1]~input_o ))) ) ) ) # ( \db_system_spwulight_b|counter [6] & ( !\db_system_spwulight_b|LessThan0~2_combout & ( !\KEY[1]~input_o ) ) ).dataa(!\db_system_spwulight_b|LessThan0~1_combout ),.datab(!\db_system_spwulight_b|Add0~45_sumout ),.datac(!\db_system_spwulight_b|counter [15]),.datad(!\KEY[1]~input_o ),.datae(!\db_system_spwulight_b|counter [6]),.dataf(!\db_system_spwulight_b|LessThan0~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~11 .extended_lut = "off";defparam \db_system_spwulight_b|counter~11 .lut_mask = 64'h0000FF0020007F00;defparam \db_system_spwulight_b|counter~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N20dffeas \db_system_spwulight_b|counter[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~11_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [6]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[6] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N21cyclonev_lcell_comb \db_system_spwulight_b|Add0~29 (// Equation(s):// \db_system_spwulight_b|Add0~29_sumout = SUM(( \db_system_spwulight_b|counter [7] ) + ( GND ) + ( \db_system_spwulight_b|Add0~46 ))// \db_system_spwulight_b|Add0~30 = CARRY(( \db_system_spwulight_b|counter [7] ) + ( GND ) + ( \db_system_spwulight_b|Add0~46 )).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\db_system_spwulight_b|counter [7]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~46 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~29_sumout ),.cout(\db_system_spwulight_b|Add0~30 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~29 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~29 .lut_mask = 64'h0000FFFF000000FF;defparam \db_system_spwulight_b|Add0~29 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N0cyclonev_lcell_comb \db_system_spwulight_b|counter~7 (// Equation(s):// \db_system_spwulight_b|counter~7_combout = ( \db_system_spwulight_b|counter [7] & ( \db_system_spwulight_b|Add0~29_sumout & ( !\KEY[1]~input_o ) ) ) # ( !\db_system_spwulight_b|counter [7] & ( \db_system_spwulight_b|Add0~29_sumout & (// (!\db_system_spwulight_b|LessThan0~1_combout & (\db_system_spwulight_b|LessThan0~2_combout & (!\db_system_spwulight_b|counter [15] & !\KEY[1]~input_o ))) ) ) ) # ( \db_system_spwulight_b|counter [7] & ( !\db_system_spwulight_b|Add0~29_sumout & (// (!\KEY[1]~input_o & (((!\db_system_spwulight_b|LessThan0~2_combout ) # (\db_system_spwulight_b|counter [15])) # (\db_system_spwulight_b|LessThan0~1_combout ))) ) ) ).dataa(!\db_system_spwulight_b|LessThan0~1_combout ),.datab(!\db_system_spwulight_b|LessThan0~2_combout ),.datac(!\db_system_spwulight_b|counter [15]),.datad(!\KEY[1]~input_o ),.datae(!\db_system_spwulight_b|counter [7]),.dataf(!\db_system_spwulight_b|Add0~29_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~7 .extended_lut = "off";defparam \db_system_spwulight_b|counter~7 .lut_mask = 64'h0000DF002000FF00;defparam \db_system_spwulight_b|counter~7 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N2dffeas \db_system_spwulight_b|counter[7] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~7_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [7]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[7] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[7] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N24cyclonev_lcell_comb \db_system_spwulight_b|Add0~33 (// Equation(s):// \db_system_spwulight_b|Add0~33_sumout = SUM(( \db_system_spwulight_b|counter [8] ) + ( GND ) + ( \db_system_spwulight_b|Add0~30 ))// \db_system_spwulight_b|Add0~34 = CARRY(( \db_system_spwulight_b|counter [8] ) + ( GND ) + ( \db_system_spwulight_b|Add0~30 )).dataa(gnd),.datab(gnd),.datac(!\db_system_spwulight_b|counter [8]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~30 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~33_sumout ),.cout(\db_system_spwulight_b|Add0~34 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~33 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~33 .lut_mask = 64'h0000FFFF00000F0F;defparam \db_system_spwulight_b|Add0~33 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N3cyclonev_lcell_comb \db_system_spwulight_b|counter~8 (// Equation(s):// \db_system_spwulight_b|counter~8_combout = ( \db_system_spwulight_b|counter [8] & ( \db_system_spwulight_b|Add0~33_sumout & ( !\KEY[1]~input_o ) ) ) # ( !\db_system_spwulight_b|counter [8] & ( \db_system_spwulight_b|Add0~33_sumout & (// (!\db_system_spwulight_b|LessThan0~1_combout & (\db_system_spwulight_b|LessThan0~2_combout & (!\KEY[1]~input_o & !\db_system_spwulight_b|counter [15]))) ) ) ) # ( \db_system_spwulight_b|counter [8] & ( !\db_system_spwulight_b|Add0~33_sumout & (// (!\KEY[1]~input_o & (((!\db_system_spwulight_b|LessThan0~2_combout ) # (\db_system_spwulight_b|counter [15])) # (\db_system_spwulight_b|LessThan0~1_combout ))) ) ) ).dataa(!\db_system_spwulight_b|LessThan0~1_combout ),.datab(!\db_system_spwulight_b|LessThan0~2_combout ),.datac(!\KEY[1]~input_o ),.datad(!\db_system_spwulight_b|counter [15]),.datae(!\db_system_spwulight_b|counter [8]),.dataf(!\db_system_spwulight_b|Add0~33_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~8 .extended_lut = "off";defparam \db_system_spwulight_b|counter~8 .lut_mask = 64'h0000D0F02000F0F0;defparam \db_system_spwulight_b|counter~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N5dffeas \db_system_spwulight_b|counter[8] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~8_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [8]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[8] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[8] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N27cyclonev_lcell_comb \db_system_spwulight_b|Add0~9 (// Equation(s):// \db_system_spwulight_b|Add0~9_sumout = SUM(( \db_system_spwulight_b|counter [9] ) + ( GND ) + ( \db_system_spwulight_b|Add0~34 ))// \db_system_spwulight_b|Add0~10 = CARRY(( \db_system_spwulight_b|counter [9] ) + ( GND ) + ( \db_system_spwulight_b|Add0~34 )).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\db_system_spwulight_b|counter [9]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~34 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~9_sumout ),.cout(\db_system_spwulight_b|Add0~10 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~9 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~9 .lut_mask = 64'h0000FFFF000000FF;defparam \db_system_spwulight_b|Add0~9 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N27cyclonev_lcell_comb \db_system_spwulight_b|counter~2 (// Equation(s):// \db_system_spwulight_b|counter~2_combout = ( \db_system_spwulight_b|counter [9] & ( \db_system_spwulight_b|Add0~9_sumout & ( !\KEY[1]~input_o ) ) ) # ( !\db_system_spwulight_b|counter [9] & ( \db_system_spwulight_b|Add0~9_sumout & (// (!\db_system_spwulight_b|LessThan0~1_combout & (\db_system_spwulight_b|LessThan0~2_combout & (!\KEY[1]~input_o & !\db_system_spwulight_b|counter [15]))) ) ) ) # ( \db_system_spwulight_b|counter [9] & ( !\db_system_spwulight_b|Add0~9_sumout & (// !\KEY[1]~input_o ) ) ).dataa(!\db_system_spwulight_b|LessThan0~1_combout ),.datab(!\db_system_spwulight_b|LessThan0~2_combout ),.datac(!\KEY[1]~input_o ),.datad(!\db_system_spwulight_b|counter [15]),.datae(!\db_system_spwulight_b|counter [9]),.dataf(!\db_system_spwulight_b|Add0~9_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~2 .extended_lut = "off";defparam \db_system_spwulight_b|counter~2 .lut_mask = 64'h0000F0F02000F0F0;defparam \db_system_spwulight_b|counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N29dffeas \db_system_spwulight_b|counter[9] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~2_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [9]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[9] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[9] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N30cyclonev_lcell_comb \db_system_spwulight_b|Add0~13 (// Equation(s):// \db_system_spwulight_b|Add0~13_sumout = SUM(( \db_system_spwulight_b|counter [10] ) + ( GND ) + ( \db_system_spwulight_b|Add0~10 ))// \db_system_spwulight_b|Add0~14 = CARRY(( \db_system_spwulight_b|counter [10] ) + ( GND ) + ( \db_system_spwulight_b|Add0~10 )).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\db_system_spwulight_b|counter [10]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~10 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~13_sumout ),.cout(\db_system_spwulight_b|Add0~14 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~13 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~13 .lut_mask = 64'h0000FFFF000000FF;defparam \db_system_spwulight_b|Add0~13 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N42cyclonev_lcell_comb \db_system_spwulight_b|counter~3 (// Equation(s):// \db_system_spwulight_b|counter~3_combout = ( \db_system_spwulight_b|counter [10] & ( \db_system_spwulight_b|Add0~13_sumout & ( !\KEY[1]~input_o ) ) ) # ( !\db_system_spwulight_b|counter [10] & ( \db_system_spwulight_b|Add0~13_sumout & (// (!\db_system_spwulight_b|LessThan0~1_combout & (\db_system_spwulight_b|LessThan0~2_combout & (!\db_system_spwulight_b|counter [15] & !\KEY[1]~input_o ))) ) ) ) # ( \db_system_spwulight_b|counter [10] & ( !\db_system_spwulight_b|Add0~13_sumout & (// !\KEY[1]~input_o ) ) ).dataa(!\db_system_spwulight_b|LessThan0~1_combout ),.datab(!\db_system_spwulight_b|LessThan0~2_combout ),.datac(!\db_system_spwulight_b|counter [15]),.datad(!\KEY[1]~input_o ),.datae(!\db_system_spwulight_b|counter [10]),.dataf(!\db_system_spwulight_b|Add0~13_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~3 .extended_lut = "off";defparam \db_system_spwulight_b|counter~3 .lut_mask = 64'h0000FF002000FF00;defparam \db_system_spwulight_b|counter~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N44dffeas \db_system_spwulight_b|counter[10] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~3_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [10]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[10] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[10] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N33cyclonev_lcell_comb \db_system_spwulight_b|Add0~17 (// Equation(s):// \db_system_spwulight_b|Add0~17_sumout = SUM(( \db_system_spwulight_b|counter [11] ) + ( GND ) + ( \db_system_spwulight_b|Add0~14 ))// \db_system_spwulight_b|Add0~18 = CARRY(( \db_system_spwulight_b|counter [11] ) + ( GND ) + ( \db_system_spwulight_b|Add0~14 )).dataa(!\db_system_spwulight_b|counter [11]),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~14 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~17_sumout ),.cout(\db_system_spwulight_b|Add0~18 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~17 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~17 .lut_mask = 64'h0000FFFF00005555;defparam \db_system_spwulight_b|Add0~17 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N45cyclonev_lcell_comb \db_system_spwulight_b|counter~4 (// Equation(s):// \db_system_spwulight_b|counter~4_combout = ( \db_system_spwulight_b|counter [11] & ( \db_system_spwulight_b|Add0~17_sumout & ( !\KEY[1]~input_o ) ) ) # ( !\db_system_spwulight_b|counter [11] & ( \db_system_spwulight_b|Add0~17_sumout & (// (!\db_system_spwulight_b|LessThan0~1_combout & (\db_system_spwulight_b|LessThan0~2_combout & (!\KEY[1]~input_o & !\db_system_spwulight_b|counter [15]))) ) ) ) # ( \db_system_spwulight_b|counter [11] & ( !\db_system_spwulight_b|Add0~17_sumout & (// !\KEY[1]~input_o ) ) ).dataa(!\db_system_spwulight_b|LessThan0~1_combout ),.datab(!\db_system_spwulight_b|LessThan0~2_combout ),.datac(!\KEY[1]~input_o ),.datad(!\db_system_spwulight_b|counter [15]),.datae(!\db_system_spwulight_b|counter [11]),.dataf(!\db_system_spwulight_b|Add0~17_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~4 .extended_lut = "off";defparam \db_system_spwulight_b|counter~4 .lut_mask = 64'h0000F0F02000F0F0;defparam \db_system_spwulight_b|counter~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N47dffeas \db_system_spwulight_b|counter[11] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~4_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [11]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[11] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[11] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N36cyclonev_lcell_comb \db_system_spwulight_b|Add0~21 (// Equation(s):// \db_system_spwulight_b|Add0~21_sumout = SUM(( \db_system_spwulight_b|counter [12] ) + ( GND ) + ( \db_system_spwulight_b|Add0~18 ))// \db_system_spwulight_b|Add0~22 = CARRY(( \db_system_spwulight_b|counter [12] ) + ( GND ) + ( \db_system_spwulight_b|Add0~18 )).dataa(gnd),.datab(gnd),.datac(!\db_system_spwulight_b|counter [12]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~18 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~21_sumout ),.cout(\db_system_spwulight_b|Add0~22 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~21 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~21 .lut_mask = 64'h0000FFFF00000F0F;defparam \db_system_spwulight_b|Add0~21 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N30cyclonev_lcell_comb \db_system_spwulight_b|counter~5 (// Equation(s):// \db_system_spwulight_b|counter~5_combout = ( \db_system_spwulight_b|counter [12] & ( \db_system_spwulight_b|Add0~21_sumout & ( !\KEY[1]~input_o ) ) ) # ( !\db_system_spwulight_b|counter [12] & ( \db_system_spwulight_b|Add0~21_sumout & (// (!\db_system_spwulight_b|LessThan0~1_combout & (\db_system_spwulight_b|LessThan0~2_combout & (!\db_system_spwulight_b|counter [15] & !\KEY[1]~input_o ))) ) ) ) # ( \db_system_spwulight_b|counter [12] & ( !\db_system_spwulight_b|Add0~21_sumout & (// !\KEY[1]~input_o ) ) ).dataa(!\db_system_spwulight_b|LessThan0~1_combout ),.datab(!\db_system_spwulight_b|LessThan0~2_combout ),.datac(!\db_system_spwulight_b|counter [15]),.datad(!\KEY[1]~input_o ),.datae(!\db_system_spwulight_b|counter [12]),.dataf(!\db_system_spwulight_b|Add0~21_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~5 .extended_lut = "off";defparam \db_system_spwulight_b|counter~5 .lut_mask = 64'h0000FF002000FF00;defparam \db_system_spwulight_b|counter~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N32dffeas \db_system_spwulight_b|counter[12] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~5_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [12]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[12] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[12] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N39cyclonev_lcell_comb \db_system_spwulight_b|Add0~25 (// Equation(s):// \db_system_spwulight_b|Add0~25_sumout = SUM(( \db_system_spwulight_b|counter [13] ) + ( GND ) + ( \db_system_spwulight_b|Add0~22 ))// \db_system_spwulight_b|Add0~26 = CARRY(( \db_system_spwulight_b|counter [13] ) + ( GND ) + ( \db_system_spwulight_b|Add0~22 )).dataa(!\db_system_spwulight_b|counter [13]),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~22 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~25_sumout ),.cout(\db_system_spwulight_b|Add0~26 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~25 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~25 .lut_mask = 64'h0000FFFF00005555;defparam \db_system_spwulight_b|Add0~25 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N33cyclonev_lcell_comb \db_system_spwulight_b|counter~6 (// Equation(s):// \db_system_spwulight_b|counter~6_combout = ( \db_system_spwulight_b|counter [13] & ( \db_system_spwulight_b|Add0~25_sumout & ( !\KEY[1]~input_o ) ) ) # ( !\db_system_spwulight_b|counter [13] & ( \db_system_spwulight_b|Add0~25_sumout & (// (!\db_system_spwulight_b|LessThan0~1_combout & (\db_system_spwulight_b|LessThan0~2_combout & (!\KEY[1]~input_o & !\db_system_spwulight_b|counter [15]))) ) ) ) # ( \db_system_spwulight_b|counter [13] & ( !\db_system_spwulight_b|Add0~25_sumout & (// !\KEY[1]~input_o ) ) ).dataa(!\db_system_spwulight_b|LessThan0~1_combout ),.datab(!\db_system_spwulight_b|LessThan0~2_combout ),.datac(!\KEY[1]~input_o ),.datad(!\db_system_spwulight_b|counter [15]),.datae(!\db_system_spwulight_b|counter [13]),.dataf(!\db_system_spwulight_b|Add0~25_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~6 .extended_lut = "off";defparam \db_system_spwulight_b|counter~6 .lut_mask = 64'h0000F0F02000F0F0;defparam \db_system_spwulight_b|counter~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N35dffeas \db_system_spwulight_b|counter[13] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~6_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [13]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[13] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[13] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N42cyclonev_lcell_comb \db_system_spwulight_b|Add0~1 (// Equation(s):// \db_system_spwulight_b|Add0~1_sumout = SUM(( \db_system_spwulight_b|counter [14] ) + ( GND ) + ( \db_system_spwulight_b|Add0~26 ))// \db_system_spwulight_b|Add0~2 = CARRY(( \db_system_spwulight_b|counter [14] ) + ( GND ) + ( \db_system_spwulight_b|Add0~26 )).dataa(gnd),.datab(!\db_system_spwulight_b|counter [14]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~26 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~1_sumout ),.cout(\db_system_spwulight_b|Add0~2 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~1 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~1 .lut_mask = 64'h0000FFFF00003333;defparam \db_system_spwulight_b|Add0~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N24cyclonev_lcell_comb \db_system_spwulight_b|counter~0 (// Equation(s):// \db_system_spwulight_b|counter~0_combout = ( \db_system_spwulight_b|counter [14] & ( \db_system_spwulight_b|Add0~1_sumout & ( !\KEY[1]~input_o ) ) ) # ( !\db_system_spwulight_b|counter [14] & ( \db_system_spwulight_b|Add0~1_sumout & (// (!\db_system_spwulight_b|LessThan0~1_combout & (\db_system_spwulight_b|LessThan0~2_combout & (!\db_system_spwulight_b|counter [15] & !\KEY[1]~input_o ))) ) ) ) # ( \db_system_spwulight_b|counter [14] & ( !\db_system_spwulight_b|Add0~1_sumout & (// !\KEY[1]~input_o ) ) ).dataa(!\db_system_spwulight_b|LessThan0~1_combout ),.datab(!\db_system_spwulight_b|LessThan0~2_combout ),.datac(!\db_system_spwulight_b|counter [15]),.datad(!\KEY[1]~input_o ),.datae(!\db_system_spwulight_b|counter [14]),.dataf(!\db_system_spwulight_b|Add0~1_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~0 .extended_lut = "off";defparam \db_system_spwulight_b|counter~0 .lut_mask = 64'h0000FF002000FF00;defparam \db_system_spwulight_b|counter~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N26dffeas \db_system_spwulight_b|counter[14] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~0_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [14]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[14] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[14] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X47_Y1_N12cyclonev_lcell_comb \db_system_spwulight_b|LessThan0~0 (// Equation(s):// \db_system_spwulight_b|LessThan0~0_combout = ( !\db_system_spwulight_b|counter [11] & ( !\db_system_spwulight_b|counter [10] & ( (!\db_system_spwulight_b|counter [9] & (!\db_system_spwulight_b|counter [12] & !\db_system_spwulight_b|counter [13])) ) ) ).dataa(!\db_system_spwulight_b|counter [9]),.datab(!\db_system_spwulight_b|counter [12]),.datac(!\db_system_spwulight_b|counter [13]),.datad(gnd),.datae(!\db_system_spwulight_b|counter [11]),.dataf(!\db_system_spwulight_b|counter [10]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|LessThan0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|LessThan0~0 .extended_lut = "off";defparam \db_system_spwulight_b|LessThan0~0 .lut_mask = 64'h8080000000000000;defparam \db_system_spwulight_b|LessThan0~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N57cyclonev_lcell_comb \db_system_spwulight_b|LessThan0~2 (// Equation(s):// \db_system_spwulight_b|LessThan0~2_combout = ( \db_system_spwulight_b|LessThan0~0_combout & ( !\db_system_spwulight_b|counter [14] ) ).dataa(gnd),.datab(gnd),.datac(!\db_system_spwulight_b|counter [14]),.datad(gnd),.datae(gnd),.dataf(!\db_system_spwulight_b|LessThan0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|LessThan0~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|LessThan0~2 .extended_lut = "off";defparam \db_system_spwulight_b|LessThan0~2 .lut_mask = 64'h00000000F0F0F0F0;defparam \db_system_spwulight_b|LessThan0~2 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N36cyclonev_lcell_comb \db_system_spwulight_b|counter~9 (// Equation(s):// \db_system_spwulight_b|counter~9_combout = ( \db_system_spwulight_b|counter [4] & ( \db_system_spwulight_b|Add0~37_sumout & ( !\KEY[1]~input_o ) ) ) # ( !\db_system_spwulight_b|counter [4] & ( \db_system_spwulight_b|Add0~37_sumout & (// (!\db_system_spwulight_b|LessThan0~1_combout & (!\KEY[1]~input_o & (!\db_system_spwulight_b|counter [15] & \db_system_spwulight_b|LessThan0~2_combout ))) ) ) ) # ( \db_system_spwulight_b|counter [4] & ( !\db_system_spwulight_b|Add0~37_sumout & (// (!\KEY[1]~input_o & (((!\db_system_spwulight_b|LessThan0~2_combout ) # (\db_system_spwulight_b|counter [15])) # (\db_system_spwulight_b|LessThan0~1_combout ))) ) ) ).dataa(!\db_system_spwulight_b|LessThan0~1_combout ),.datab(!\KEY[1]~input_o ),.datac(!\db_system_spwulight_b|counter [15]),.datad(!\db_system_spwulight_b|LessThan0~2_combout ),.datae(!\db_system_spwulight_b|counter [4]),.dataf(!\db_system_spwulight_b|Add0~37_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~9 .extended_lut = "off";defparam \db_system_spwulight_b|counter~9 .lut_mask = 64'h0000CC4C0080CCCC;defparam \db_system_spwulight_b|counter~9 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N38dffeas \db_system_spwulight_b|counter[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~9_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [4]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[4] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[4] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X47_Y1_N54cyclonev_lcell_comb \db_system_spwulight_b|LessThan0~1 (// Equation(s):// \db_system_spwulight_b|LessThan0~1_combout = ( \db_system_spwulight_b|counter [5] & ( (\db_system_spwulight_b|counter [8] & \db_system_spwulight_b|counter [7]) ) ) # ( !\db_system_spwulight_b|counter [5] & ( (\db_system_spwulight_b|counter [8] &// (\db_system_spwulight_b|counter [7] & ((\db_system_spwulight_b|counter [6]) # (\db_system_spwulight_b|counter [4])))) ) ).dataa(!\db_system_spwulight_b|counter [4]),.datab(!\db_system_spwulight_b|counter [6]),.datac(!\db_system_spwulight_b|counter [8]),.datad(!\db_system_spwulight_b|counter [7]),.datae(gnd),.dataf(!\db_system_spwulight_b|counter [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|LessThan0~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|LessThan0~1 .extended_lut = "off";defparam \db_system_spwulight_b|LessThan0~1 .lut_mask = 64'h00070007000F000F;defparam \db_system_spwulight_b|LessThan0~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X46_Y1_N45cyclonev_lcell_comb \db_system_spwulight_b|Add0~5 (// Equation(s):// \db_system_spwulight_b|Add0~5_sumout = SUM(( \db_system_spwulight_b|counter [15] ) + ( GND ) + ( \db_system_spwulight_b|Add0~2 )).dataa(gnd),.datab(gnd),.datac(!\db_system_spwulight_b|counter [15]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~2 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~5_sumout ),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~5 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~5 .lut_mask = 64'h0000FFFF00000F0F;defparam \db_system_spwulight_b|Add0~5 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N48cyclonev_lcell_comb \db_system_spwulight_b|counter~1 (// Equation(s):// \db_system_spwulight_b|counter~1_combout = ( \db_system_spwulight_b|counter [15] & ( \db_system_spwulight_b|LessThan0~2_combout & ( !\KEY[1]~input_o ) ) ) # ( !\db_system_spwulight_b|counter [15] & ( \db_system_spwulight_b|LessThan0~2_combout & (// (!\db_system_spwulight_b|LessThan0~1_combout & (!\KEY[1]~input_o & \db_system_spwulight_b|Add0~5_sumout )) ) ) ) # ( \db_system_spwulight_b|counter [15] & ( !\db_system_spwulight_b|LessThan0~2_combout & ( !\KEY[1]~input_o ) ) ).dataa(!\db_system_spwulight_b|LessThan0~1_combout ),.datab(!\KEY[1]~input_o ),.datac(!\db_system_spwulight_b|Add0~5_sumout ),.datad(gnd),.datae(!\db_system_spwulight_b|counter [15]),.dataf(!\db_system_spwulight_b|LessThan0~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~1 .extended_lut = "off";defparam \db_system_spwulight_b|counter~1 .lut_mask = 64'h0000CCCC0808CCCC;defparam \db_system_spwulight_b|counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N50dffeas \db_system_spwulight_b|counter[15] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~1_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [15]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[15] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[15] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X47_Y1_N9cyclonev_lcell_comb \db_system_spwulight_b|aux_pb~0 (// Equation(s):// \db_system_spwulight_b|aux_pb~0_combout = ( \db_system_spwulight_b|LessThan0~1_combout & ( \db_system_spwulight_b|aux_pb~q & ( !\KEY[1]~input_o ) ) ) # ( !\db_system_spwulight_b|LessThan0~1_combout & ( \db_system_spwulight_b|aux_pb~q & (// !\KEY[1]~input_o ) ) ) # ( \db_system_spwulight_b|LessThan0~1_combout & ( !\db_system_spwulight_b|aux_pb~q & ( !\KEY[1]~input_o ) ) ) # ( !\db_system_spwulight_b|LessThan0~1_combout & ( !\db_system_spwulight_b|aux_pb~q & ( (!\KEY[1]~input_o &// (((!\db_system_spwulight_b|LessThan0~0_combout ) # (\db_system_spwulight_b|counter [14])) # (\db_system_spwulight_b|counter [15]))) ) ) ).dataa(!\db_system_spwulight_b|counter [15]),.datab(!\db_system_spwulight_b|counter [14]),.datac(!\db_system_spwulight_b|LessThan0~0_combout ),.datad(!\KEY[1]~input_o ),.datae(!\db_system_spwulight_b|LessThan0~1_combout ),.dataf(!\db_system_spwulight_b|aux_pb~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|aux_pb~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|aux_pb~0 .extended_lut = "off";defparam \db_system_spwulight_b|aux_pb~0 .lut_mask = 64'hF700FF00FF00FF00;defparam \db_system_spwulight_b|aux_pb~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N17dffeas \db_system_spwulight_b|aux_pb (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\db_system_spwulight_b|aux_pb~0_combout ),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|aux_pb~q ),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|aux_pb .is_wysiwyg = "true";defparam \db_system_spwulight_b|aux_pb .power_up = "low";// synopsys translate_on// Location: FRACTIONALPLL_X68_Y1_N0cyclonev_fractional_pll \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll (.coreclkfb(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fboutclk_wire [0]),.ecnc1test(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|refclk_select_extswitchbuf_wire ),.ecnc2test(gnd),.fbclkfpll(gnd),.lvdsfbin(gnd),.nresync(!\db_system_spwulight_b|aux_pb~q ),.pfden(vcc),.refclkin(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|refclk_select_clkout_wire ),.shift(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shift ),.shiftdonein(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shift ),.shiften(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|pll_reconfig_shiftenm_wire ),.up(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|pll_reconfig_up_wire ),.zdb(gnd),.cntnen(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|cntnen ),.fbclk(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fboutclk_wire [0]),.fblvdsout(),.lock(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),.mcntout(),.plniotribuf(),.shiftdoneout(),.tclk(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|tclk ),.mhi(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus ),.vcoph(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus ));// synopsys translate_offdefparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .dsm_accumulator_reset_value = 0;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .forcelock = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .mimic_fbclk_type = "none";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .nreset_invert = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .output_clock_frequency = "400.0 mhz";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_atb = 0;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_bwctrl = 4000;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_cmp_buf_dly = "0 ps";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_cp_comp = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_cp_current = 10;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_ctrl_override_setting = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_dsm_dither = "disable";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_dsm_out_sel = "disable";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_dsm_reset = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_ecn_bypass = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_ecn_test_en = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_enable = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_fbclk_mux_1 = "glb";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_fbclk_mux_2 = "m_cnt";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_fractional_carry_out = 32;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_fractional_division = 1;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_fractional_division_string = "1";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_fractional_value_ready = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_lf_testen = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_lock_fltr_cfg = 25;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_lock_fltr_test = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_bypass_en = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_coarse_dly = "0 ps";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_fine_dly = "0 ps";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_hi_div = 4;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_in_src = "ph_mux_clk";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_lo_div = 4;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_odd_div_duty_en = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_ph_mux_prst = 0;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_prst = 1;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_n_cnt_bypass_en = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_n_cnt_coarse_dly = "0 ps";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_n_cnt_fine_dly = "0 ps";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_n_cnt_hi_div = 1;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_n_cnt_lo_div = 1;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_n_cnt_odd_div_duty_en = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_ref_buf_dly = "0 ps";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_reg_boost = 0;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_regulator_bypass = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_ripplecap_ctrl = 0;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_slf_rst = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_tclk_mux_en = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_tclk_sel = "n_src";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_test_enable = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_testdn_enable = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_testup_enable = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_unlock_fltr_cfg = 2;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_div = 2;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph0_en = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph1_en = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph2_en = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph3_en = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph4_en = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph5_en = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph6_en = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph7_en = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vctrl_test_voltage = 750;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .reference_clock_frequency = "100.0 mhz";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .vccd0g_atb = "disable";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .vccd0g_output = 0;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .vccd1g_atb = "disable";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .vccd1g_output = 0;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .vccm1g_tap = 2;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .vccr_pd = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .vcodiv_override = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .fractional_pll_index = 0;// synopsys translate_on// Location: PLLRECONFIG_X68_Y5_N0cyclonev_pll_reconfig \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|PLL_RECONFIG (.atpgmode(gnd),.clk(gnd),.cntnen(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|cntnen ),.fpllcsrtest(gnd),.iocsrclkin(gnd),.iocsrdatain(gnd),.iocsren(gnd),.iocsrrstn(gnd),.mdiodis(vcc),.phaseen(gnd),.read(gnd),.rstn(vcc),.scanen(gnd),.sershiftload(vcc),.shiftdonei(gnd),.updn(gnd),.write(gnd),.addr(6'b000000),.byteen(2'b00),.cntsel(5'b00000),.din(16'b0000000000000000),.mhi({\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [7],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [6],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [5],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [4],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [3],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [2],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [1],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [0]}),.blockselect(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|blockselect ),.iocsrdataout(),.iocsrenbuf(),.iocsrrstnbuf(),.phasedone(),.shift(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shift ),.shiftenm(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|pll_reconfig_shiftenm_wire ),.up(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|pll_reconfig_up_wire ),.dout(),.dprioout(),.shiften(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|PLL_RECONFIG_SHIFTEN_bus ));// synopsys translate_offdefparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|PLL_RECONFIG .fractional_pll_index = 0;// synopsys translate_on// Location: PLLOUTPUTCOUNTER_X68_Y2_N1cyclonev_pll_output_counter \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter (.cascadein(gnd),.nen0(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|cntnen ),.shift0(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shift ),.shiftdone0i(gnd),.shiften(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shiften [2]),.tclk0(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|tclk ),.up0(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|pll_reconfig_up_wire ),.vco0ph({\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [7],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [6],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [5],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [4],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [3],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [2],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [1],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [0]}),.cascadeout(\u0|pll_0|altera_pll_i|cyclonev_pll|cascade_wire [0]),.divclk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk [0]),.shiftdone0o());// synopsys translate_offdefparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .c_cnt_coarse_dly = "0 ps";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .c_cnt_fine_dly = "0 ps";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .c_cnt_in_src = "ph_mux_clk";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .c_cnt_ph_mux_prst = 0;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .c_cnt_prst = 1;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .cnt_fpll_src = "fpll_0";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .dprio0_cnt_bypass_en = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .dprio0_cnt_hi_div = 256;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .dprio0_cnt_lo_div = 256;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .dprio0_cnt_odd_div_even_duty_en = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .duty_cycle = 50;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .output_clock_frequency = "400.0 mhz";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .phase_shift = "0 ps";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .fractional_pll_index = 0;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .output_counter_index = 2;// synopsys translate_on// Location: CLKCTRL_G11cyclonev_clkena \u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0 (.inclk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk [0]),.ena(vcc),.outclk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),.enaout());// synopsys translate_offdefparam \u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0 .clock_type = "global clock";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0 .disable_mode = "low";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0 .ena_register_mode = "always enabled";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0 .ena_register_power_up = "high";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0 .test_syn = "high";// synopsys translate_on// Location: LABCELL_X21_Y20_N24cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~2 (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~2_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~0_combout & ( !\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0] $// (!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [1]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0]),.datad(!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~2 .lut_mask = 64'h000000000FF00FF0;defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X31_Y11_N45cyclonev_lcell_comb \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder (// Equation(s):// \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder .extended_lut = "off";defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X31_Y11_N47dffeas \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout ),.asdata(vcc),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [1]),.prn(vcc));// synopsys translate_offdefparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] .is_wysiwyg = "true";defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] .power_up = "low";// synopsys translate_on// Location: FF_X31_Y11_N32dffeas \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [1]),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [0]),.prn(vcc));// synopsys translate_offdefparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] .is_wysiwyg = "true";defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] .power_up = "low";// synopsys translate_on// Location: FF_X31_Y11_N17dffeas \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [0]),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.prn(vcc));// synopsys translate_offdefparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out .is_wysiwyg = "true";defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out .power_up = "low";// synopsys translate_on// Location: CLKCTRL_G3cyclonev_clkena \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 (.inclk(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.ena(vcc),.outclk(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.enaout());// synopsys translate_offdefparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 .clock_type = "global clock";defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 .disable_mode = "low";defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 .ena_register_mode = "always enabled";defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 .ena_register_power_up = "high";defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 .test_syn = "high";// synopsys translate_on// Location: FF_X21_Y20_N26dffeas \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y20_N9cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y20_N11dffeas \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y21_N36cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y21_N38dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y20_N15cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y20_N17dffeas \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: LABCELL_X10_Y25_N48cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~2 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~2_combout = ( \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1] & ( \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~0_combout & (// !\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0] ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1] & ( \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~0_combout & (// \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0] ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]),.datac(gnd),.datad(gnd),.datae(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1]),.dataf(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~2 .lut_mask = 64'h000000003333CCCC;defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y25_N50dffeas \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y14_N24cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y14_N26dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y27_N45cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~1 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~1_combout = ( \u0|mm_interconnect_0|cmd_mux_007|arb|grant[0]~1_combout & ( (\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [1]) #// (\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~0_combout ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_007|arb|grant[0]~1_combout & ( (!\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~0_combout &// \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [1]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~0_combout ),.datad(!\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_007|arb|grant[0]~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~1 .lut_mask = 64'h00F000F00FFF0FFF;defparam \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y27_N47dffeas \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg[1] .power_up = "low";// synopsys translate_on// Location: FF_X22_Y24_N44dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][110] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~15_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][110]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";// synopsys translate_on// Location: FF_X27_Y17_N59dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][69] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][69]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][69] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][69] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y24_N12cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_payload[0] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux|src_payload [0] = ( \u0|hps_0|fpga_interfaces|h2f_WLAST [0] & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [0]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WLAST [0] & (// \u0|mm_interconnect_0|cmd_mux|saved_grant [1] ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),.datac(gnd),.datad(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux|src_payload [0]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux|src_payload[0] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux|src_payload[0] .lut_mask = 64'h00FF00FF33FF33FF;defparam \u0|mm_interconnect_0|cmd_mux|src_payload[0] .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y24_N27cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|packet_in_progress~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux|packet_in_progress~0_combout = ( !\u0|mm_interconnect_0|cmd_mux|update_grant~0_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux|update_grant~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux|packet_in_progress~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux|packet_in_progress~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux|packet_in_progress~0 .lut_mask = 64'hFFFFFFFF00000000;defparam \u0|mm_interconnect_0|cmd_mux|packet_in_progress~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y24_N28dffeas \u0|mm_interconnect_0|cmd_mux|packet_in_progress (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux|packet_in_progress~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|cmd_mux|packet_in_progress~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux|packet_in_progress .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|cmd_mux|packet_in_progress .power_up = "low";// synopsys translate_on// Location: LABCELL_X10_Y25_N27cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y25_N29dffeas \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: LABCELL_X10_Y25_N21cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout = ( !\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1] & ( \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0 .lut_mask = 64'h00FF00FF00000000;defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y25_N3cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|local_write~0_combout & ( (\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout &// (!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0] $ (((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ))))) ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_agent|local_write~0_combout & ( (\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout & \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout ),.datab(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|local_write~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4 .lut_mask = 64'h1111111141114111;defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y25_N39cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~1 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~1_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4_combout & ( \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~0_combout ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~0_combout ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h0000000055555555;defparam \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y25_N41dffeas \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg[0] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y17_N3cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_010|src1_valid (// Equation(s):// \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout & ( !\u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout ),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|rsp_demux_010|src1_valid .extended_lut = "off";defparam \u0|mm_interconnect_0|rsp_demux_010|src1_valid .lut_mask = 64'hCCCCCCCC00000000;defparam \u0|mm_interconnect_0|rsp_demux_010|src1_valid .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X45_Y7_N6cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~5 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|Add1~5_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [2] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~2 ))// \R_400_to_2_5_10_100_200_300MHZ|Add1~6 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [2] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~2 )).dataa(gnd),.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [2]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~2 ),.sharein(gnd),.combout(),.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~5_sumout ),.cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~6 ),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|Add1~5 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~5 .lut_mask = 64'h0000FFFF00003333;defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~5 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X45_Y7_N9cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~29 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|Add1~29_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [3] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~6 ))// \R_400_to_2_5_10_100_200_300MHZ|Add1~30 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [3] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~6 )).dataa(gnd),.datab(gnd),.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [3]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~6 ),.sharein(gnd),.combout(),.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~29_sumout ),.cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~30 ),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|Add1~29 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~29 .lut_mask = 64'h0000FFFF00000F0F;defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~29 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X45_Y7_N39cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~8 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|counter_100~8_combout = ( \R_400_to_2_5_10_100_200_300MHZ|Add1~29_sumout & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout ) ).dataa(gnd),.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout ),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add1~29_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~8 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~8 .lut_mask = 64'h0000000033333333;defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X45_Y7_N41dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[3] (.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),.d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~8_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [3]),.prn(vcc));// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[3] .is_wysiwyg = "true";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X45_Y7_N12cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~33 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|Add1~33_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [4] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~30 ))// \R_400_to_2_5_10_100_200_300MHZ|Add1~34 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [4] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~30 )).dataa(gnd),.datab(gnd),.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [4]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~30 ),.sharein(gnd),.combout(),.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~33_sumout ),.cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~34 ),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|Add1~33 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~33 .lut_mask = 64'h0000FFFF00000F0F;defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~33 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X45_Y7_N36cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~9 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|counter_100~9_combout = ( \R_400_to_2_5_10_100_200_300MHZ|Add1~33_sumout & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout ) ).dataa(gnd),.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout ),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add1~33_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~9 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~9 .lut_mask = 64'h0000000033333333;defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~9 .shared_arith = "off";// synopsys translate_on// Location: FF_X45_Y7_N38dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[4] (.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),.d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~9_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [4]),.prn(vcc));// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[4] .is_wysiwyg = "true";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X45_Y7_N15cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~37 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|Add1~37_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [5] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~34 ))// \R_400_to_2_5_10_100_200_300MHZ|Add1~38 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [5] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~34 )).dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [5]),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~34 ),.sharein(gnd),.combout(),.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~37_sumout ),.cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~38 ),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|Add1~37 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~37 .lut_mask = 64'h0000FFFF00005555;defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~37 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X45_Y7_N54cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~10 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|counter_100~10_combout = ( \R_400_to_2_5_10_100_200_300MHZ|Add1~37_sumout & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout ) ).dataa(gnd),.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout ),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add1~37_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~10_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~10 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~10 .lut_mask = 64'h0000000033333333;defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~10 .shared_arith = "off";// synopsys translate_on// Location: FF_X45_Y7_N56dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[5] (.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),.d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~10_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [5]),.prn(vcc));// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[5] .is_wysiwyg = "true";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X45_Y7_N18cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~41 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|Add1~41_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [6] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~38 ))// \R_400_to_2_5_10_100_200_300MHZ|Add1~42 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [6] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~38 )).dataa(gnd),.datab(gnd),.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [6]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~38 ),.sharein(gnd),.combout(),.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~41_sumout ),.cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~42 ),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|Add1~41 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~41 .lut_mask = 64'h0000FFFF00000F0F;defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~41 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X45_Y7_N51cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~11 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|counter_100~11_combout = ( \R_400_to_2_5_10_100_200_300MHZ|Add1~41_sumout & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout ) ).dataa(gnd),.datab(gnd),.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add1~41_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~11 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~11 .lut_mask = 64'h000000000F0F0F0F;defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X45_Y7_N53dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[6] (.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),.d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~11_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [6]),.prn(vcc));// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[6] .is_wysiwyg = "true";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X45_Y7_N42cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|LessThan16~0 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|LessThan16~0_combout = ( !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [6] & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [5] & (!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [3] &// !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [4])) ) ).dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [5]),.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [3]),.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [4]),.datad(gnd),.datae(gnd),.dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [6]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\R_400_to_2_5_10_100_200_300MHZ|LessThan16~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|LessThan16~0 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan16~0 .lut_mask = 64'h8080808000000000;defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan16~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X45_Y7_N21cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~13 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|Add1~13_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [7] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~42 ))// \R_400_to_2_5_10_100_200_300MHZ|Add1~14 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [7] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~42 )).dataa(gnd),.datab(gnd),.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [7]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~42 ),.sharein(gnd),.combout(),.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~13_sumout ),.cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~14 ),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|Add1~13 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~13 .lut_mask = 64'h0000FFFF00000F0F;defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~13 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X45_Y7_N45cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~4 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|counter_100~4_combout = (\R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout & \R_400_to_2_5_10_100_200_300MHZ|Add1~13_sumout ).dataa(gnd),.datab(gnd),.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout ),.datad(!\R_400_to_2_5_10_100_200_300MHZ|Add1~13_sumout ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~4 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~4 .lut_mask = 64'h000F000F000F000F;defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X45_Y7_N47dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[7] (.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),.d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~4_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [7]),.prn(vcc));// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[7] .is_wysiwyg = "true";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[7] .power_up = "low";// synopsys translate_on// Location: LABCELL_X45_Y7_N24cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~17 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|Add1~17_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [8] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~14 ))// \R_400_to_2_5_10_100_200_300MHZ|Add1~18 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [8] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~14 )).dataa(gnd),.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [8]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~14 ),.sharein(gnd),.combout(),.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~17_sumout ),.cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~18 ),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|Add1~17 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~17 .lut_mask = 64'h0000FFFF00003333;defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~17 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X46_Y7_N57cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~5 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|counter_100~5_combout = ( \R_400_to_2_5_10_100_200_300MHZ|Add1~17_sumout & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout ) ).dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add1~17_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~5 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~5 .lut_mask = 64'h0000000055555555;defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X46_Y7_N59dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[8] (.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),.d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~5_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [8]),.prn(vcc));// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[8] .is_wysiwyg = "true";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[8] .power_up = "low";// synopsys translate_on// Location: LABCELL_X45_Y7_N27cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~21 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|Add1~21_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [9] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~18 ))// \R_400_to_2_5_10_100_200_300MHZ|Add1~22 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [9] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~18 )).dataa(gnd),.datab(gnd),.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [9]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~18 ),.sharein(gnd),.combout(),.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~21_sumout ),.cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~22 ),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|Add1~21 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~21 .lut_mask = 64'h0000FFFF00000F0F;defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~21 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X46_Y7_N18cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~6 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|counter_100~6_combout = ( \R_400_to_2_5_10_100_200_300MHZ|Add1~21_sumout & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\R_400_to_2_5_10_100_200_300MHZ|Add1~21_sumout ),.dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~6 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~6 .lut_mask = 64'h000000000000FFFF;defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X46_Y7_N20dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[9] (.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),.d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~6_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [9]),.prn(vcc));// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[9] .is_wysiwyg = "true";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[9] .power_up = "low";// synopsys translate_on// Location: LABCELL_X45_Y7_N30cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~25 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|Add1~25_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [10] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~22 )).dataa(gnd),.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [10]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~22 ),.sharein(gnd),.combout(),.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~25_sumout ),.cout(),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|Add1~25 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~25 .lut_mask = 64'h0000FFFF00003333;defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~25 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X45_Y7_N57cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~7 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|counter_100~7_combout = ( \R_400_to_2_5_10_100_200_300MHZ|Add1~25_sumout & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout ) ).dataa(gnd),.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout ),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add1~25_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~7 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~7 .lut_mask = 64'h0000000033333333;defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~7 .shared_arith = "off";// synopsys translate_on// Location: FF_X45_Y7_N59dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[10] (.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),.d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~7_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [10]),.prn(vcc));// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[10] .is_wysiwyg = "true";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[10] .power_up = "low";// synopsys translate_on// Location: LABCELL_X45_Y7_N48cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout = ( !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [9] & ( (\R_400_to_2_5_10_100_200_300MHZ|LessThan16~0_combout & (!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [10] &// (!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [7] & !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [8]))) ) ).dataa(!\R_400_to_2_5_10_100_200_300MHZ|LessThan16~0_combout ),.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [10]),.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [7]),.datad(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [8]),.datae(gnd),.dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [9]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1 .lut_mask = 64'h4000400000000000;defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X45_Y7_N0cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~9 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|Add1~9_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [0] ) + ( VCC ) + ( !VCC ))// \R_400_to_2_5_10_100_200_300MHZ|Add1~10 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [0] ) + ( VCC ) + ( !VCC )).dataa(gnd),.datab(gnd),.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [0]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(),.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~9_sumout ),.cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~10 ),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|Add1~9 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~9 .lut_mask = 64'h0000000000000F0F;defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~9 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X46_Y7_N30cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~3 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|counter_100~3_combout = ( \R_400_to_2_5_10_100_200_300MHZ|Add1~9_sumout & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout ) ).dataa(gnd),.datab(gnd),.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add1~9_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~3 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~3 .lut_mask = 64'h000000000F0F0F0F;defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X46_Y7_N32dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[0] (.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),.d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~3_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [0]),.prn(vcc));// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[0] .is_wysiwyg = "true";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y7_N48cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~0 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout = ( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [1] & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [0] & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [2] &// (\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock & \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout )) ) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [1] & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [0] & (// (!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [2] & (\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock & \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout )) ) ) ) # ( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [1] & (// !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [0] & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [2] & (\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock & \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout )) ) ) ) # (// !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [1] & ( !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [0] & ( (\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock & \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout ) ) ) ).dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [2]),.datab(gnd),.datac(!\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),.datad(!\R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout ),.datae(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [1]),.dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~0 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~0 .lut_mask = 64'h000F000A000A000A;defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X45_Y7_N3cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~1 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|Add1~1_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [1] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~10 ))// \R_400_to_2_5_10_100_200_300MHZ|Add1~2 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [1] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~10 )).dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [1]),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~10 ),.sharein(gnd),.combout(),.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~1_sumout ),.cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~2 ),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|Add1~1 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~1 .lut_mask = 64'h0000FFFF00005555;defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X46_Y7_N45cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~1 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|counter_100~1_combout = ( \R_400_to_2_5_10_100_200_300MHZ|Add1~1_sumout & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout ) ).dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add1~1_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~1 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~1 .lut_mask = 64'h0000000055555555;defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X46_Y7_N47dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[1] (.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),.d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~1_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [1]),.prn(vcc));// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[1] .is_wysiwyg = "true";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y7_N24cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~2 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|counter_100~2_combout = ( \R_400_to_2_5_10_100_200_300MHZ|Add1~5_sumout & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\R_400_to_2_5_10_100_200_300MHZ|Add1~5_sumout ),.dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter_100~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~2 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~2 .lut_mask = 64'h000000000000FFFF;defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X46_Y7_N26dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[2] (.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),.d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~2_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [2]),.prn(vcc));// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[2] .is_wysiwyg = "true";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y7_N3cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~0 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~0_combout = ( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [1] & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [0] & ( (\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock &// ((!\R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout ) # (\R_400_to_2_5_10_100_200_300MHZ|counter_100 [2]))) ) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [1] & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [0] & (// \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ) ) ) # ( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [1] & ( !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [0] & ( (\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock &// ((!\R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout ) # (\R_400_to_2_5_10_100_200_300MHZ|counter_100 [2]))) ) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [1] & ( !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [0] & (// (\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock & ((!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [2]) # (!\R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout ))) ) ) ).dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [2]),.datab(!\R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout ),.datac(gnd),.datad(!\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),.datae(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [1]),.dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~0 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~0 .lut_mask = 64'h00EE00DD00FF00DD;defparam \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X46_Y7_N5dffeas \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i (.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),.d(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~0_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),.prn(vcc));// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i .is_wysiwyg = "true";defparam \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i .power_up = "low";// synopsys translate_on// Location: MLABCELL_X37_Y10_N54cyclonev_lcell_comb \A_SPW_TOP|tx_data|counter_writer[0]~0 (// Equation(s):// \A_SPW_TOP|tx_data|counter_writer[0]~0_combout = !\A_SPW_TOP|tx_data|counter_writer [0].dataa(gnd),.datab(gnd),.datac(!\A_SPW_TOP|tx_data|counter_writer [0]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|tx_data|counter_writer[0]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|tx_data|counter_writer[0]~0 .extended_lut = "off";defparam \A_SPW_TOP|tx_data|counter_writer[0]~0 .lut_mask = 64'hF0F0F0F0F0F0F0F0;defparam \A_SPW_TOP|tx_data|counter_writer[0]~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X37_Y10_N45cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add1~1 (// Equation(s):// \A_SPW_TOP|tx_data|Add1~1_combout = ( \A_SPW_TOP|tx_data|counter_writer [0] & ( !\A_SPW_TOP|tx_data|counter_writer [1] $ (!\A_SPW_TOP|tx_data|counter_writer [2]) ) ) # ( !\A_SPW_TOP|tx_data|counter_writer [0] & ( \A_SPW_TOP|tx_data|counter_writer [2] ) ).dataa(!\A_SPW_TOP|tx_data|counter_writer [1]),.datab(!\A_SPW_TOP|tx_data|counter_writer [2]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\A_SPW_TOP|tx_data|counter_writer [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|tx_data|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|tx_data|Add1~1 .extended_lut = "off";defparam \A_SPW_TOP|tx_data|Add1~1 .lut_mask = 64'h3333333366666666;defparam \A_SPW_TOP|tx_data|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X37_Y10_N14dffeas \A_SPW_TOP|tx_data|counter_writer[2] (.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),.d(gnd),.asdata(\A_SPW_TOP|tx_data|Add1~1_combout ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\A_SPW_TOP|tx_data|state_data_write.10~q ),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|tx_data|counter_writer [2]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|tx_data|counter_writer[2] .is_wysiwyg = "true";defparam \A_SPW_TOP|tx_data|counter_writer[2] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X37_Y10_N42cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add1~2 (// Equation(s):// \A_SPW_TOP|tx_data|Add1~2_combout = ( \A_SPW_TOP|tx_data|counter_writer [3] & ( (!\A_SPW_TOP|tx_data|counter_writer [2]) # ((!\A_SPW_TOP|tx_data|counter_writer [1]) # (!\A_SPW_TOP|tx_data|counter_writer [0])) ) ) # ( !\A_SPW_TOP|tx_data|counter_writer// [3] & ( (\A_SPW_TOP|tx_data|counter_writer [2] & (\A_SPW_TOP|tx_data|counter_writer [1] & \A_SPW_TOP|tx_data|counter_writer [0])) ) ).dataa(gnd),.datab(!\A_SPW_TOP|tx_data|counter_writer [2]),.datac(!\A_SPW_TOP|tx_data|counter_writer [1]),.datad(!\A_SPW_TOP|tx_data|counter_writer [0]),.datae(gnd),.dataf(!\A_SPW_TOP|tx_data|counter_writer [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|tx_data|Add1~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|tx_data|Add1~2 .extended_lut = "off";defparam \A_SPW_TOP|tx_data|Add1~2 .lut_mask = 64'h00030003FFFCFFFC;defparam \A_SPW_TOP|tx_data|Add1~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X37_Y10_N17dffeas \A_SPW_TOP|tx_data|counter_writer[3] (.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),.d(gnd),.asdata(\A_SPW_TOP|tx_data|Add1~2_combout ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\A_SPW_TOP|tx_data|state_data_write.10~q ),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|tx_data|counter_writer [3]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|tx_data|counter_writer[3] .is_wysiwyg = "true";defparam \A_SPW_TOP|tx_data|counter_writer[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X36_Y10_N24cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add1~3 (// Equation(s):// \A_SPW_TOP|tx_data|Add1~3_combout = ( \A_SPW_TOP|tx_data|counter_writer [2] & ( !\A_SPW_TOP|tx_data|counter_writer [4] $ (((!\A_SPW_TOP|tx_data|counter_writer [1]) # ((!\A_SPW_TOP|tx_data|counter_writer [0]) # (!\A_SPW_TOP|tx_data|counter_writer [3]))))// ) ) # ( !\A_SPW_TOP|tx_data|counter_writer [2] & ( \A_SPW_TOP|tx_data|counter_writer [4] ) ).dataa(!\A_SPW_TOP|tx_data|counter_writer [1]),.datab(!\A_SPW_TOP|tx_data|counter_writer [0]),.datac(!\A_SPW_TOP|tx_data|counter_writer [3]),.datad(!\A_SPW_TOP|tx_data|counter_writer [4]),.datae(gnd),.dataf(!\A_SPW_TOP|tx_data|counter_writer [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|tx_data|Add1~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|tx_data|Add1~3 .extended_lut = "off";defparam \A_SPW_TOP|tx_data|Add1~3 .lut_mask = 64'h00FF00FF01FE01FE;defparam \A_SPW_TOP|tx_data|Add1~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X37_Y10_N2dffeas \A_SPW_TOP|tx_data|counter_writer[4] (.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),.d(gnd),.asdata(\A_SPW_TOP|tx_data|Add1~3_combout ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\A_SPW_TOP|tx_data|state_data_write.10~q ),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|tx_data|counter_writer [4]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|tx_data|counter_writer[4] .is_wysiwyg = "true";defparam \A_SPW_TOP|tx_data|counter_writer[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X35_Y10_N33cyclonev_lcell_comb \A_SPW_TOP|tx_data|counter_reader[0]~0 (// Equation(s):// \A_SPW_TOP|tx_data|counter_reader[0]~0_combout = ( !\A_SPW_TOP|tx_data|counter_reader [0] ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\A_SPW_TOP|tx_data|counter_reader [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|tx_data|counter_reader[0]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|tx_data|counter_reader[0]~0 .extended_lut = "off";defparam \A_SPW_TOP|tx_data|counter_reader[0]~0 .lut_mask = 64'hFFFFFFFF00000000;defparam \A_SPW_TOP|tx_data|counter_reader[0]~0 .shared_arith = "off";// synopsys translate_on// Location: IOIBUF_X51_Y0_N1cyclonev_io_ibuf \sin_a~input (.i(sin_a),.ibar(\sin_a(n) ),.dynamicterminationcontrol(gnd),.o(\sin_a~input_o ));// synopsys translate_offdefparam \sin_a~input .bus_hold = "false";defparam \sin_a~input .simulate_z_as = "z";// synopsys translate_on// Location: IOIBUF_X46_Y0_N1cyclonev_io_ibuf \din_a~input (.i(din_a),.ibar(\din_a(n) ),.dynamicterminationcontrol(gnd),.o(\din_a~input_o ));// synopsys translate_offdefparam \din_a~input .bus_hold = "false";defparam \din_a~input .simulate_z_as = "z";// synopsys translate_on// Location: LABCELL_X48_Y2_N57cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|always3~0 (// Equation(s):// \A_SPW_TOP|SPW|RX|always3~0_combout = LCELL(( \din_a~input_o & ( !\sin_a~input_o ) ) # ( !\din_a~input_o & ( \sin_a~input_o ) )).dataa(gnd),.datab(gnd),.datac(!\sin_a~input_o ),.datad(gnd),.datae(gnd),.dataf(!\din_a~input_o ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|always3~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|always3~0 .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|always3~0 .lut_mask = 64'h0F0F0F0FF0F0F0F0;defparam \A_SPW_TOP|SPW|RX|always3~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X49_Y3_N42cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|counter_neg[0]~feeder (// Equation(s):// \A_SPW_TOP|SPW|RX|counter_neg[0]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|counter_neg[0]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|counter_neg[0]~feeder .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|counter_neg[0]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \A_SPW_TOP|SPW|RX|counter_neg[0]~feeder .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X50_Y3_N12cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|always2~0 (// Equation(s):// \A_SPW_TOP|SPW|RX|always2~0_combout = LCELL(( \A_SPW_TOP|SPW|RX|counter_neg [2] & ( \A_SPW_TOP|SPW|RX|always3~0_combout & ( (\A_SPW_TOP|SPW|RX|Selector0~0_combout & !\A_SPW_TOP|SPW|RX|counter_neg [1]) ) ) )).dataa(gnd),.datab(gnd),.datac(!\A_SPW_TOP|SPW|RX|Selector0~0_combout ),.datad(!\A_SPW_TOP|SPW|RX|counter_neg [1]),.datae(!\A_SPW_TOP|SPW|RX|counter_neg [2]),.dataf(!\A_SPW_TOP|SPW|RX|always3~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|always2~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|always2~0 .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|always2~0 .lut_mask = 64'h0000000000000F00;defparam \A_SPW_TOP|SPW|RX|always2~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X49_Y3_N45cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|ready_data_p (// Equation(s):// \A_SPW_TOP|SPW|RX|ready_data_p~combout = LCELL(( \A_SPW_TOP|SPW|RX|always3~0_combout & ( (\A_SPW_TOP|SPW|RX|Selector1~0_combout & (!\A_SPW_TOP|SPW|RX|counter_neg [4] & (!\A_SPW_TOP|SPW|RX|always2~0_combout & \A_SPW_TOP|SPW|RX|counter_neg [5]))) ) )).dataa(!\A_SPW_TOP|SPW|RX|Selector1~0_combout ),.datab(!\A_SPW_TOP|SPW|RX|counter_neg [4]),.datac(!\A_SPW_TOP|SPW|RX|always2~0_combout ),.datad(!\A_SPW_TOP|SPW|RX|counter_neg [5]),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|RX|always3~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|ready_data_p~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|ready_data_p .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|ready_data_p .lut_mask = 64'h0000000000400040;defparam \A_SPW_TOP|SPW|RX|ready_data_p .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X49_Y3_N18cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|ready_data (// Equation(s):// \A_SPW_TOP|SPW|RX|ready_data~combout = LCELL(( !\A_SPW_TOP|SPW|RX|always3~0_combout & ( (!\A_SPW_TOP|SPW|RX|always1~0_combout & (!\A_SPW_TOP|SPW|RX|counter_neg [4] & (\A_SPW_TOP|SPW|RX|Selector1~0_combout & \A_SPW_TOP|SPW|RX|counter_neg [5]))) ) )).dataa(!\A_SPW_TOP|SPW|RX|always1~0_combout ),.datab(!\A_SPW_TOP|SPW|RX|counter_neg [4]),.datac(!\A_SPW_TOP|SPW|RX|Selector1~0_combout ),.datad(!\A_SPW_TOP|SPW|RX|counter_neg [5]),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|RX|always3~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|ready_data~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|ready_data .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|ready_data .lut_mask = 64'h0008000800000000;defparam \A_SPW_TOP|SPW|RX|ready_data .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X48_Y2_N24cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|bit_d_1~feeder (// Equation(s):// \A_SPW_TOP|SPW|RX|bit_d_1~feeder_combout = ( \din_a~input_o ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\din_a~input_o ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|bit_d_1~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|bit_d_1~feeder .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|bit_d_1~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \A_SPW_TOP|SPW|RX|bit_d_1~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X48_Y2_N26dffeas \A_SPW_TOP|SPW|RX|bit_d_1 (.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),.d(\A_SPW_TOP|SPW|RX|bit_d_1~feeder_combout ),.asdata(vcc),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|bit_d_1~q ),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|bit_d_1 .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|bit_d_1 .power_up = "low";// synopsys translate_on// Location: LABCELL_X48_Y2_N0cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|bit_d_3~feeder (// Equation(s):// \A_SPW_TOP|SPW|RX|bit_d_3~feeder_combout = ( \A_SPW_TOP|SPW|RX|bit_d_1~q ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|RX|bit_d_1~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|bit_d_3~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|bit_d_3~feeder .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|bit_d_3~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \A_SPW_TOP|SPW|RX|bit_d_3~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X48_Y2_N2dffeas \A_SPW_TOP|SPW|RX|bit_d_3 (.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),.d(\A_SPW_TOP|SPW|RX|bit_d_3~feeder_combout ),.asdata(vcc),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|bit_d_3~q ),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|bit_d_3 .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|bit_d_3 .power_up = "low";// synopsys translate_on// Location: FF_X48_Y2_N5dffeas \A_SPW_TOP|SPW|RX|bit_d_5 (.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),.d(gnd),.asdata(\A_SPW_TOP|SPW|RX|bit_d_3~q ),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|bit_d_5~q ),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|bit_d_5 .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|bit_d_5 .power_up = "low";// synopsys translate_on// Location: FF_X48_Y2_N35dffeas \A_SPW_TOP|SPW|RX|bit_d_7 (.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),.d(gnd),.asdata(\A_SPW_TOP|SPW|RX|bit_d_5~q ),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|bit_d_7~q ),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|bit_d_7 .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|bit_d_7 .power_up = "low";// synopsys translate_on// Location: LABCELL_X48_Y2_N27cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|bit_d_9~feeder (// Equation(s):// \A_SPW_TOP|SPW|RX|bit_d_9~feeder_combout = ( \A_SPW_TOP|SPW|RX|bit_d_7~q ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|RX|bit_d_7~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|bit_d_9~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|bit_d_9~feeder .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|bit_d_9~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \A_SPW_TOP|SPW|RX|bit_d_9~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X48_Y2_N28dffeas \A_SPW_TOP|SPW|RX|bit_d_9 (.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),.d(\A_SPW_TOP|SPW|RX|bit_d_9~feeder_combout ),.asdata(vcc),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|bit_d_9~q ),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|bit_d_9 .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|bit_d_9 .power_up = "low";// synopsys translate_on// Location: MLABCELL_X50_Y2_N36cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|parity_rec_d~feeder (// Equation(s):// \A_SPW_TOP|SPW|RX|parity_rec_d~feeder_combout = ( \A_SPW_TOP|SPW|RX|bit_d_9~q ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|RX|bit_d_9~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|parity_rec_d~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|parity_rec_d~feeder .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|parity_rec_d~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \A_SPW_TOP|SPW|RX|parity_rec_d~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X50_Y2_N38dffeas \A_SPW_TOP|SPW|RX|parity_rec_d (.clk(\A_SPW_TOP|SPW|RX|ready_data~combout ),.d(\A_SPW_TOP|SPW|RX|parity_rec_d~feeder_combout ),.asdata(vcc),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|parity_rec_d~q ),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|parity_rec_d .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|parity_rec_d .power_up = "low";// synopsys translate_on// Location: FF_X48_Y2_N14dffeas \A_SPW_TOP|SPW|RX|bit_d_0 (.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),.d(gnd),.asdata(\din_a~input_o ),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|bit_d_0~q ),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|bit_d_0 .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|bit_d_0 .power_up = "low";// synopsys translate_on// Location: FF_X48_Y2_N50dffeas \A_SPW_TOP|SPW|RX|bit_d_2 (.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),.d(gnd),.asdata(\A_SPW_TOP|SPW|RX|bit_d_0~q ),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|bit_d_2~q ),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|bit_d_2 .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|bit_d_2 .power_up = "low";// synopsys translate_on// Location: FF_X48_Y2_N38dffeas \A_SPW_TOP|SPW|RX|bit_d_4 (.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),.d(gnd),.asdata(\A_SPW_TOP|SPW|RX|bit_d_2~q ),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|bit_d_4~q ),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|bit_d_4 .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|bit_d_4 .power_up = "low";// synopsys translate_on// Location: MLABCELL_X50_Y2_N33cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|bit_d_6~feeder (// Equation(s):// \A_SPW_TOP|SPW|RX|bit_d_6~feeder_combout = ( \A_SPW_TOP|SPW|RX|bit_d_4~q ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|RX|bit_d_4~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|bit_d_6~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|bit_d_6~feeder .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|bit_d_6~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \A_SPW_TOP|SPW|RX|bit_d_6~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X50_Y2_N35dffeas \A_SPW_TOP|SPW|RX|bit_d_6 (.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),.d(\A_SPW_TOP|SPW|RX|bit_d_6~feeder_combout ),.asdata(vcc),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|bit_d_6~q ),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|bit_d_6 .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|bit_d_6 .power_up = "low";// synopsys translate_on// Location: MLABCELL_X50_Y2_N12cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|bit_d_8~feeder (// Equation(s):// \A_SPW_TOP|SPW|RX|bit_d_8~feeder_combout = ( \A_SPW_TOP|SPW|RX|bit_d_6~q ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|RX|bit_d_6~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|bit_d_8~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|bit_d_8~feeder .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|bit_d_8~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \A_SPW_TOP|SPW|RX|bit_d_8~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X50_Y2_N14dffeas \A_SPW_TOP|SPW|RX|bit_d_8 (.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),.d(\A_SPW_TOP|SPW|RX|bit_d_8~feeder_combout ),.asdata(vcc),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|bit_d_8~q ),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|bit_d_8 .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|bit_d_8 .power_up = "low";// synopsys translate_on// Location: LABCELL_X49_Y2_N18cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|dta_timec[8]~feeder (// Equation(s):// \A_SPW_TOP|SPW|RX|dta_timec[8]~feeder_combout = ( \A_SPW_TOP|SPW|RX|bit_d_8~q ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|RX|bit_d_8~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|dta_timec[8]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|dta_timec[8]~feeder .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|dta_timec[8]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \A_SPW_TOP|SPW|RX|dta_timec[8]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X49_Y2_N20dffeas \A_SPW_TOP|SPW|RX|dta_timec[8] (.clk(\A_SPW_TOP|SPW|RX|ready_data~combout ),.d(\A_SPW_TOP|SPW|RX|dta_timec[8]~feeder_combout ),.asdata(vcc),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|dta_timec [8]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|dta_timec[8] .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|dta_timec[8] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X50_Y2_N27cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|always15~0 (// Equation(s):// \A_SPW_TOP|SPW|RX|always15~0_combout = ( !\A_SPW_TOP|SPW|RX|parity_rec_d~q & ( \A_SPW_TOP|SPW|RX|dta_timec [8] ) ) # ( \A_SPW_TOP|SPW|RX|parity_rec_d~q & ( !\A_SPW_TOP|SPW|RX|dta_timec [8] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\A_SPW_TOP|SPW|RX|parity_rec_d~q ),.dataf(!\A_SPW_TOP|SPW|RX|dta_timec [8]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|always15~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|always15~0 .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|always15~0 .lut_mask = 64'h0000FFFFFFFF0000;defparam \A_SPW_TOP|SPW|RX|always15~0 .shared_arith = "off";// synopsys translate_on// Location: DDIOINCELL_X46_Y0_N14dffeas \A_SPW_TOP|SPW|RX|control_bit_found (.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),.d(\din_a~input_o ),.asdata(vcc),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|control_bit_found~q ),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|control_bit_found .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|control_bit_found .power_up = "low";// synopsys translate_on// Location: LABCELL_X49_Y3_N6cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|Selector0~1 (// Equation(s):// \A_SPW_TOP|SPW|RX|Selector0~1_combout = ( !\A_SPW_TOP|SPW|RX|counter_neg [3] & ( !\A_SPW_TOP|SPW|RX|counter_neg [4] & ( (\A_SPW_TOP|SPW|RX|counter_neg [0] & ((!\A_SPW_TOP|SPW|RX|counter_neg [5] & (!\A_SPW_TOP|SPW|RX|counter_neg [2] $// (!\A_SPW_TOP|SPW|RX|counter_neg [1]))) # (\A_SPW_TOP|SPW|RX|counter_neg [5] & (!\A_SPW_TOP|SPW|RX|counter_neg [2] & !\A_SPW_TOP|SPW|RX|counter_neg [1])))) ) ) ).dataa(!\A_SPW_TOP|SPW|RX|counter_neg [5]),.datab(!\A_SPW_TOP|SPW|RX|counter_neg [0]),.datac(!\A_SPW_TOP|SPW|RX|counter_neg [2]),.datad(!\A_SPW_TOP|SPW|RX|counter_neg [1]),.datae(!\A_SPW_TOP|SPW|RX|counter_neg [3]),.dataf(!\A_SPW_TOP|SPW|RX|counter_neg [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|Selector0~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|Selector0~1 .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|Selector0~1 .lut_mask = 64'h1220000000000000;defparam \A_SPW_TOP|SPW|RX|Selector0~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X49_Y3_N12cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|Selector0~3 (// Equation(s):// \A_SPW_TOP|SPW|RX|Selector0~3_combout = ( \A_SPW_TOP|SPW|RX|Selector0~1_combout & ( (\A_SPW_TOP|SPW|RX|Selector0~2_combout & (\A_SPW_TOP|SPW|RX|counter_neg [1] & \A_SPW_TOP|SPW|RX|control_bit_found~q )) ) ) # ( !\A_SPW_TOP|SPW|RX|Selector0~1_combout &// ( \A_SPW_TOP|SPW|RX|is_control~q ) ).dataa(!\A_SPW_TOP|SPW|RX|Selector0~2_combout ),.datab(!\A_SPW_TOP|SPW|RX|counter_neg [1]),.datac(!\A_SPW_TOP|SPW|RX|control_bit_found~q ),.datad(!\A_SPW_TOP|SPW|RX|is_control~q ),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|RX|Selector0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|Selector0~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|Selector0~3 .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|Selector0~3 .lut_mask = 64'h00FF00FF01010101;defparam \A_SPW_TOP|SPW|RX|Selector0~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X49_Y3_N59dffeas \A_SPW_TOP|SPW|RX|is_control (.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),.d(gnd),.asdata(\A_SPW_TOP|SPW|RX|Selector0~3_combout ),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|is_control~q ),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|is_control .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|is_control .power_up = "low";// synopsys translate_on// Location: LABCELL_X48_Y3_N45cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|ready_data_p_r~0 (// Equation(s):// \A_SPW_TOP|SPW|RX|ready_data_p_r~0_combout = ( !\A_SPW_TOP|SPW|RX|is_control~q & ( \A_SPW_TOP|SPW|RX|ready_data~combout ) ) # ( !\A_SPW_TOP|SPW|RX|is_control~q & ( !\A_SPW_TOP|SPW|RX|ready_data~combout & ( \A_SPW_TOP|SPW|RX|ready_data_p~combout ) )// ).dataa(!\A_SPW_TOP|SPW|RX|ready_data_p~combout ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\A_SPW_TOP|SPW|RX|is_control~q ),.dataf(!\A_SPW_TOP|SPW|RX|ready_data~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|ready_data_p_r~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|ready_data_p_r~0 .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|ready_data_p_r~0 .lut_mask = 64'h55550000FFFF0000;defparam \A_SPW_TOP|SPW|RX|ready_data_p_r~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X48_Y3_N47dffeas \A_SPW_TOP|SPW|RX|ready_data_p_r (.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),.d(\A_SPW_TOP|SPW|RX|ready_data_p_r~0_combout ),.asdata(vcc),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|ready_data_p_r~q ),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|ready_data_p_r .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|ready_data_p_r .power_up = "low";// synopsys translate_on// Location: MLABCELL_X47_Y3_N24cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|last_is_control~0 (// Equation(s):// \A_SPW_TOP|SPW|RX|last_is_control~0_combout = ( \A_SPW_TOP|SPW|RX|last_is_control~q & ( (!\A_SPW_TOP|SPW|RX|ready_data_p_r~q ) # (\A_SPW_TOP|SPW|RX|ready_control_p_r~q ) ) ) # ( !\A_SPW_TOP|SPW|RX|last_is_control~q & (// \A_SPW_TOP|SPW|RX|ready_control_p_r~q ) ).dataa(gnd),.datab(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),.datac(!\A_SPW_TOP|SPW|RX|ready_data_p_r~q ),.datad(gnd),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|RX|last_is_control~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|last_is_control~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|last_is_control~0 .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|last_is_control~0 .lut_mask = 64'h33333333F3F3F3F3;defparam \A_SPW_TOP|SPW|RX|last_is_control~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X48_Y3_N51cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|next_state_data_process.01~0 (// Equation(s):// \A_SPW_TOP|SPW|RX|next_state_data_process.01~0_combout = ( \A_SPW_TOP|SPW|RX|ready_control_p_r~q & ( !\A_SPW_TOP|SPW|RX|state_data_process.01~q ) ) # ( !\A_SPW_TOP|SPW|RX|ready_control_p_r~q & ( (!\A_SPW_TOP|SPW|RX|state_data_process.01~q &// \A_SPW_TOP|SPW|RX|ready_data_p_r~q ) ) ).dataa(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),.datab(gnd),.datac(!\A_SPW_TOP|SPW|RX|ready_data_p_r~q ),.datad(gnd),.datae(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|next_state_data_process.01~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|next_state_data_process.01~0 .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|next_state_data_process.01~0 .lut_mask = 64'h0A0AAAAA0A0AAAAA;defparam \A_SPW_TOP|SPW|RX|next_state_data_process.01~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X48_Y3_N3cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|state_data_process.01~feeder (// Equation(s):// \A_SPW_TOP|SPW|RX|state_data_process.01~feeder_combout = ( \A_SPW_TOP|SPW|RX|next_state_data_process.01~0_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|RX|next_state_data_process.01~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|state_data_process.01~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|state_data_process.01~feeder .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|state_data_process.01~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \A_SPW_TOP|SPW|RX|state_data_process.01~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X48_Y3_N5dffeas \A_SPW_TOP|SPW|RX|state_data_process.01 (.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),.d(\A_SPW_TOP|SPW|RX|state_data_process.01~feeder_combout ),.asdata(vcc),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|state_data_process.01~q ),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|state_data_process.01 .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|state_data_process.01 .power_up = "low";// synopsys translate_on// Location: FF_X47_Y3_N11dffeas \A_SPW_TOP|SPW|RX|last_is_control (.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),.d(gnd),.asdata(\A_SPW_TOP|SPW|RX|last_is_control~0_combout ),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|last_is_control~q ),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|last_is_control .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|last_is_control .power_up = "low";// synopsys translate_on// Location: MLABCELL_X50_Y3_N39cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_error_c~0 (// Equation(s):// \A_SPW_TOP|SPW|RX|rx_error_c~0_combout = ( \A_SPW_TOP|SPW|RX|last_is_data~q & ( !\A_SPW_TOP|SPW|RX|last_is_control~q ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\A_SPW_TOP|SPW|RX|last_is_data~q ),.dataf(!\A_SPW_TOP|SPW|RX|last_is_control~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|rx_error_c~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|rx_error_c~0 .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|rx_error_c~0 .lut_mask = 64'h0000FFFF00000000;defparam \A_SPW_TOP|SPW|RX|rx_error_c~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X49_Y3_N41dffeas \A_SPW_TOP|SPW|RX|bit_c_1 (.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),.d(gnd),.asdata(\din_a~input_o ),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|bit_c_1~q ),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|bit_c_1 .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|bit_c_1 .power_up = "low";// synopsys translate_on// Location: MLABCELL_X50_Y3_N27cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|control_r[1]~feeder (// Equation(s):// \A_SPW_TOP|SPW|RX|control_r[1]~feeder_combout = ( \A_SPW_TOP|SPW|RX|bit_c_1~q ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|RX|bit_c_1~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|control_r[1]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|control_r[1]~feeder .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|control_r[1]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \A_SPW_TOP|SPW|RX|control_r[1]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X50_Y3_N28dffeas \A_SPW_TOP|SPW|RX|control_r[1] (.clk(\A_SPW_TOP|SPW|RX|always1~0_combout ),.d(\A_SPW_TOP|SPW|RX|control_r[1]~feeder_combout ),.asdata(vcc),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|control_r [1]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|control_r[1] .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|control_r[1] .power_up = "low";// synopsys translate_on// Location: FF_X50_Y3_N14dffeas \A_SPW_TOP|SPW|RX|control_p_r[1] (.clk(\A_SPW_TOP|SPW|RX|always2~0_combout ),.d(gnd),.asdata(\A_SPW_TOP|SPW|RX|control_r [1]),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|control_p_r [1]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|control_p_r[1] .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|control_p_r[1] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X47_Y3_N57cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|control~1 (// Equation(s):// \A_SPW_TOP|SPW|RX|control~1_combout = (!\A_SPW_TOP|SPW|RX|ready_control_p_r~q & (\A_SPW_TOP|SPW|RX|control [1])) # (\A_SPW_TOP|SPW|RX|ready_control_p_r~q & ((\A_SPW_TOP|SPW|RX|control_p_r [1]))).dataa(gnd),.datab(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),.datac(!\A_SPW_TOP|SPW|RX|control [1]),.datad(!\A_SPW_TOP|SPW|RX|control_p_r [1]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|control~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|control~1 .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|control~1 .lut_mask = 64'h0C3F0C3F0C3F0C3F;defparam \A_SPW_TOP|SPW|RX|control~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y3_N17dffeas \A_SPW_TOP|SPW|RX|control[1] (.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),.d(gnd),.asdata(\A_SPW_TOP|SPW|RX|control~1_combout ),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|control [1]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|control[1] .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|control[1] .power_up = "low";// synopsys translate_on// Location: FF_X49_Y3_N29dffeas \A_SPW_TOP|SPW|RX|bit_c_0 (.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),.d(gnd),.asdata(\din_a~input_o ),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|bit_c_0~q ),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|bit_c_0 .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|bit_c_0 .power_up = "low";// synopsys translate_on// Location: FF_X50_Y3_N49dffeas \A_SPW_TOP|SPW|RX|control_r[0] (.clk(\A_SPW_TOP|SPW|RX|always1~0_combout ),.d(gnd),.asdata(\A_SPW_TOP|SPW|RX|bit_c_0~q ),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|control_r [0]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|control_r[0] .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|control_r[0] .power_up = "low";// synopsys translate_on// Location: FF_X50_Y3_N17dffeas \A_SPW_TOP|SPW|RX|control_p_r[0] (.clk(\A_SPW_TOP|SPW|RX|always2~0_combout ),.d(gnd),.asdata(\A_SPW_TOP|SPW|RX|control_r [0]),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|control_p_r [0]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|control_p_r[0] .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|control_p_r[0] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X47_Y3_N48cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|control~2 (// Equation(s):// \A_SPW_TOP|SPW|RX|control~2_combout = ( \A_SPW_TOP|SPW|RX|control_p_r [0] & ( (\A_SPW_TOP|SPW|RX|control [0]) # (\A_SPW_TOP|SPW|RX|ready_control_p_r~q ) ) ) # ( !\A_SPW_TOP|SPW|RX|control_p_r [0] & ( (!\A_SPW_TOP|SPW|RX|ready_control_p_r~q &// \A_SPW_TOP|SPW|RX|control [0]) ) ).dataa(gnd),.datab(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),.datac(gnd),.datad(!\A_SPW_TOP|SPW|RX|control [0]),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|RX|control_p_r [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|control~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|control~2 .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|control~2 .lut_mask = 64'h00CC00CC33FF33FF;defparam \A_SPW_TOP|SPW|RX|control~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y3_N35dffeas \A_SPW_TOP|SPW|RX|control[0] (.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),.d(gnd),.asdata(\A_SPW_TOP|SPW|RX|control~2_combout ),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|control [0]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|control[0] .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|control[0] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X50_Y3_N30cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_error_d~0 (// Equation(s):// \A_SPW_TOP|SPW|RX|rx_error_d~0_combout = ( \A_SPW_TOP|SPW|RX|control [0] & ( (\A_SPW_TOP|SPW|RX|last_is_control~q & (!\A_SPW_TOP|SPW|RX|control [1] $ (!\A_SPW_TOP|SPW|RX|parity_rec_d~q $ (\A_SPW_TOP|SPW|RX|dta_timec [8])))) ) ) # (// !\A_SPW_TOP|SPW|RX|control [0] & ( (\A_SPW_TOP|SPW|RX|last_is_control~q & (!\A_SPW_TOP|SPW|RX|control [1] $ (!\A_SPW_TOP|SPW|RX|parity_rec_d~q $ (!\A_SPW_TOP|SPW|RX|dta_timec [8])))) ) ).dataa(!\A_SPW_TOP|SPW|RX|control [1]),.datab(!\A_SPW_TOP|SPW|RX|parity_rec_d~q ),.datac(!\A_SPW_TOP|SPW|RX|dta_timec [8]),.datad(!\A_SPW_TOP|SPW|RX|last_is_control~q ),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|RX|control [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|rx_error_d~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|rx_error_d~0 .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|rx_error_d~0 .lut_mask = 64'h0096009600690069;defparam \A_SPW_TOP|SPW|RX|rx_error_d~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X50_Y2_N54cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|dta_timec[3]~feeder (// Equation(s):// \A_SPW_TOP|SPW|RX|dta_timec[3]~feeder_combout = ( \A_SPW_TOP|SPW|RX|bit_d_4~q ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|RX|bit_d_4~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|dta_timec[3]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|dta_timec[3]~feeder .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|dta_timec[3]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \A_SPW_TOP|SPW|RX|dta_timec[3]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X50_Y2_N55dffeas \A_SPW_TOP|SPW|RX|dta_timec[3] (.clk(\A_SPW_TOP|SPW|RX|ready_data~combout ),.d(\A_SPW_TOP|SPW|RX|dta_timec[3]~feeder_combout ),.asdata(vcc),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|dta_timec [3]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|dta_timec[3] .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|dta_timec[3] .power_up = "low";// synopsys translate_on// Location: FF_X49_Y2_N47dffeas \A_SPW_TOP|SPW|RX|dta_timec_p[3] (.clk(\A_SPW_TOP|SPW|RX|ready_data_p~combout ),.d(gnd),.asdata(\A_SPW_TOP|SPW|RX|dta_timec [3]),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|dta_timec_p [3]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|dta_timec_p[3] .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|dta_timec_p[3] .power_up = "low";// synopsys translate_on// Location: FF_X49_Y3_N1dffeas \A_SPW_TOP|SPW|RX|bit_c_2 (.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),.d(gnd),.asdata(\A_SPW_TOP|SPW|RX|bit_c_0~q ),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|bit_c_2~q ),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|bit_c_2 .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|bit_c_2 .power_up = "low";// synopsys translate_on// Location: FF_X50_Y3_N53dffeas \A_SPW_TOP|SPW|RX|control_r[2] (.clk(\A_SPW_TOP|SPW|RX|always1~0_combout ),.d(gnd),.asdata(\A_SPW_TOP|SPW|RX|bit_c_2~q ),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|control_r [2]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|control_r[2] .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|control_r[2] .power_up = "low";// synopsys translate_on// Location: FF_X50_Y3_N32dffeas \A_SPW_TOP|SPW|RX|control_p_r[2] (.clk(\A_SPW_TOP|SPW|RX|always2~0_combout ),.d(gnd),.asdata(\A_SPW_TOP|SPW|RX|control_r [2]),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|control_p_r [2]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|control_p_r[2] .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|control_p_r[2] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X47_Y3_N6cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|control~0 (// Equation(s):// \A_SPW_TOP|SPW|RX|control~0_combout = (!\A_SPW_TOP|SPW|RX|ready_control_p_r~q & ((\A_SPW_TOP|SPW|RX|control [2]))) # (\A_SPW_TOP|SPW|RX|ready_control_p_r~q & (\A_SPW_TOP|SPW|RX|control_p_r [2])).dataa(gnd),.datab(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),.datac(!\A_SPW_TOP|SPW|RX|control_p_r [2]),.datad(!\A_SPW_TOP|SPW|RX|control [2]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|control~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|control~0 .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|control~0 .lut_mask = 64'h03CF03CF03CF03CF;defparam \A_SPW_TOP|SPW|RX|control~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y3_N3cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|control[2]~feeder (// Equation(s):// \A_SPW_TOP|SPW|RX|control[2]~feeder_combout = ( \A_SPW_TOP|SPW|RX|control~0_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|RX|control~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|control[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|control[2]~feeder .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|control[2]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \A_SPW_TOP|SPW|RX|control[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y3_N5dffeas \A_SPW_TOP|SPW|RX|control[2] (.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),.d(\A_SPW_TOP|SPW|RX|control[2]~feeder_combout ),.asdata(vcc),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|control [2]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|control[2] .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|control[2] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X47_Y3_N33cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|data~0 (// Equation(s):// \A_SPW_TOP|SPW|RX|data~0_combout = ( \A_SPW_TOP|SPW|RX|ready_data_p_r~q & ( (\A_SPW_TOP|SPW|RX|control [2] & (\A_SPW_TOP|SPW|RX|control [1] & \A_SPW_TOP|SPW|RX|control [0])) ) ) # ( !\A_SPW_TOP|SPW|RX|ready_data_p_r~q ).dataa(!\A_SPW_TOP|SPW|RX|control [2]),.datab(gnd),.datac(!\A_SPW_TOP|SPW|RX|control [1]),.datad(!\A_SPW_TOP|SPW|RX|control [0]),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|RX|ready_data_p_r~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|data~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|data~0 .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|data~0 .lut_mask = 64'hFFFFFFFF00050005;defparam \A_SPW_TOP|SPW|RX|data~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X46_Y2_N3cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|data~5 (// Equation(s):// \A_SPW_TOP|SPW|RX|data~5_combout = ( \A_SPW_TOP|SPW|RX|data [3] & ( \A_SPW_TOP|SPW|RX|data~0_combout ) ) # ( \A_SPW_TOP|SPW|RX|data [3] & ( !\A_SPW_TOP|SPW|RX|data~0_combout & ( (\A_SPW_TOP|SPW|RX|ready_control_p_r~q ) # (\A_SPW_TOP|SPW|RX|dta_timec_p// [3]) ) ) ) # ( !\A_SPW_TOP|SPW|RX|data [3] & ( !\A_SPW_TOP|SPW|RX|data~0_combout & ( (\A_SPW_TOP|SPW|RX|dta_timec_p [3] & !\A_SPW_TOP|SPW|RX|ready_control_p_r~q ) ) ) ).dataa(!\A_SPW_TOP|SPW|RX|dta_timec_p [3]),.datab(gnd),.datac(gnd),.datad(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),.datae(!\A_SPW_TOP|SPW|RX|data [3]),.dataf(!\A_SPW_TOP|SPW|RX|data~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|data~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|data~5 .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|data~5 .lut_mask = 64'h550055FF0000FFFF;defparam \A_SPW_TOP|SPW|RX|data~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X46_Y2_N2dffeas \A_SPW_TOP|SPW|RX|data[3] (.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),.d(gnd),.asdata(\A_SPW_TOP|SPW|RX|data~5_combout ),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|data [3]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|data[3] .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|data[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X49_Y2_N15cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|dta_timec[6]~feeder (// Equation(s):// \A_SPW_TOP|SPW|RX|dta_timec[6]~feeder_combout = ( \A_SPW_TOP|SPW|RX|bit_d_1~q ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|RX|bit_d_1~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|dta_timec[6]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|dta_timec[6]~feeder .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|dta_timec[6]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \A_SPW_TOP|SPW|RX|dta_timec[6]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X49_Y2_N17dffeas \A_SPW_TOP|SPW|RX|dta_timec[6] (.clk(\A_SPW_TOP|SPW|RX|ready_data~combout ),.d(\A_SPW_TOP|SPW|RX|dta_timec[6]~feeder_combout ),.asdata(vcc),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|dta_timec [6]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|dta_timec[6] .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|dta_timec[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X49_Y2_N51cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|dta_timec_p[6]~feeder (// Equation(s):// \A_SPW_TOP|SPW|RX|dta_timec_p[6]~feeder_combout = ( \A_SPW_TOP|SPW|RX|dta_timec [6] ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|RX|dta_timec [6]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|dta_timec_p[6]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|dta_timec_p[6]~feeder .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|dta_timec_p[6]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \A_SPW_TOP|SPW|RX|dta_timec_p[6]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X49_Y2_N52dffeas \A_SPW_TOP|SPW|RX|dta_timec_p[6] (.clk(\A_SPW_TOP|SPW|RX|ready_data_p~combout ),.d(\A_SPW_TOP|SPW|RX|dta_timec_p[6]~feeder_combout ),.asdata(vcc),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|dta_timec_p [6]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|dta_timec_p[6] .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|dta_timec_p[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y2_N54cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|data~2 (// Equation(s):// \A_SPW_TOP|SPW|RX|data~2_combout = ( \A_SPW_TOP|SPW|RX|data~0_combout & ( \A_SPW_TOP|SPW|RX|data [6] ) ) # ( !\A_SPW_TOP|SPW|RX|data~0_combout & ( \A_SPW_TOP|SPW|RX|data [6] & ( (\A_SPW_TOP|SPW|RX|dta_timec_p [6]) #// (\A_SPW_TOP|SPW|RX|ready_control_p_r~q ) ) ) ) # ( !\A_SPW_TOP|SPW|RX|data~0_combout & ( !\A_SPW_TOP|SPW|RX|data [6] & ( (!\A_SPW_TOP|SPW|RX|ready_control_p_r~q & \A_SPW_TOP|SPW|RX|dta_timec_p [6]) ) ) ).dataa(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),.datab(gnd),.datac(!\A_SPW_TOP|SPW|RX|dta_timec_p [6]),.datad(gnd),.datae(!\A_SPW_TOP|SPW|RX|data~0_combout ),.dataf(!\A_SPW_TOP|SPW|RX|data [6]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|data~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|data~2 .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|data~2 .lut_mask = 64'h0A0A00005F5FFFFF;defparam \A_SPW_TOP|SPW|RX|data~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X46_Y2_N8dffeas \A_SPW_TOP|SPW|RX|data[6] (.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),.d(gnd),.asdata(\A_SPW_TOP|SPW|RX|data~2_combout ),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|data [6]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|data[6] .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|data[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X49_Y2_N21cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|dta_timec[2]~feeder (// Equation(s):// \A_SPW_TOP|SPW|RX|dta_timec[2]~feeder_combout = ( \A_SPW_TOP|SPW|RX|bit_d_5~q ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|RX|bit_d_5~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|dta_timec[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|dta_timec[2]~feeder .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|dta_timec[2]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \A_SPW_TOP|SPW|RX|dta_timec[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X49_Y2_N23dffeas \A_SPW_TOP|SPW|RX|dta_timec[2] (.clk(\A_SPW_TOP|SPW|RX|ready_data~combout ),.d(\A_SPW_TOP|SPW|RX|dta_timec[2]~feeder_combout ),.asdata(vcc),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|dta_timec [2]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|dta_timec[2] .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|dta_timec[2] .power_up = "low";// synopsys translate_on// Location: FF_X49_Y2_N5dffeas \A_SPW_TOP|SPW|RX|dta_timec_p[2] (.clk(\A_SPW_TOP|SPW|RX|ready_data_p~combout ),.d(gnd),.asdata(\A_SPW_TOP|SPW|RX|dta_timec [2]),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|dta_timec_p [2]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|dta_timec_p[2] .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|dta_timec_p[2] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X47_Y2_N9cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|data~6 (// Equation(s):// \A_SPW_TOP|SPW|RX|data~6_combout = ( \A_SPW_TOP|SPW|RX|dta_timec_p [2] & ( ((!\A_SPW_TOP|SPW|RX|data~0_combout & !\A_SPW_TOP|SPW|RX|ready_control_p_r~q )) # (\A_SPW_TOP|SPW|RX|data [2]) ) ) # ( !\A_SPW_TOP|SPW|RX|dta_timec_p [2] & (// (\A_SPW_TOP|SPW|RX|data [2] & ((\A_SPW_TOP|SPW|RX|ready_control_p_r~q ) # (\A_SPW_TOP|SPW|RX|data~0_combout ))) ) ).dataa(!\A_SPW_TOP|SPW|RX|data~0_combout ),.datab(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),.datac(!\A_SPW_TOP|SPW|RX|data [2]),.datad(gnd),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|RX|dta_timec_p [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|data~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|data~6 .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|data~6 .lut_mask = 64'h070707078F8F8F8F;defparam \A_SPW_TOP|SPW|RX|data~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y2_N47dffeas \A_SPW_TOP|SPW|RX|data[2] (.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),.d(gnd),.asdata(\A_SPW_TOP|SPW|RX|data~6_combout ),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|data [2]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|data[2] .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|data[2] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X50_Y2_N18cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|dta_timec[7]~feeder (// Equation(s):// \A_SPW_TOP|SPW|RX|dta_timec[7]~feeder_combout = ( \A_SPW_TOP|SPW|RX|bit_d_0~q ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|RX|bit_d_0~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|dta_timec[7]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|dta_timec[7]~feeder .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|dta_timec[7]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \A_SPW_TOP|SPW|RX|dta_timec[7]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X50_Y2_N19dffeas \A_SPW_TOP|SPW|RX|dta_timec[7] (.clk(\A_SPW_TOP|SPW|RX|ready_data~combout ),.d(\A_SPW_TOP|SPW|RX|dta_timec[7]~feeder_combout ),.asdata(vcc),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|dta_timec [7]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|dta_timec[7] .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|dta_timec[7] .power_up = "low";// synopsys translate_on// Location: FF_X49_Y2_N11dffeas \A_SPW_TOP|SPW|RX|dta_timec_p[7] (.clk(\A_SPW_TOP|SPW|RX|ready_data_p~combout ),.d(gnd),.asdata(\A_SPW_TOP|SPW|RX|dta_timec [7]),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|dta_timec_p [7]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|dta_timec_p[7] .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|dta_timec_p[7] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X47_Y2_N45cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|data~1 (// Equation(s):// \A_SPW_TOP|SPW|RX|data~1_combout = ( \A_SPW_TOP|SPW|RX|data [7] & ( ((\A_SPW_TOP|SPW|RX|dta_timec_p [7]) # (\A_SPW_TOP|SPW|RX|ready_control_p_r~q )) # (\A_SPW_TOP|SPW|RX|data~0_combout ) ) ) # ( !\A_SPW_TOP|SPW|RX|data [7] & (// (!\A_SPW_TOP|SPW|RX|data~0_combout & (!\A_SPW_TOP|SPW|RX|ready_control_p_r~q & \A_SPW_TOP|SPW|RX|dta_timec_p [7])) ) ).dataa(!\A_SPW_TOP|SPW|RX|data~0_combout ),.datab(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),.datac(!\A_SPW_TOP|SPW|RX|dta_timec_p [7]),.datad(gnd),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|RX|data [7]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|data~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|data~1 .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|data~1 .lut_mask = 64'h080808087F7F7F7F;defparam \A_SPW_TOP|SPW|RX|data~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y2_N44dffeas \A_SPW_TOP|SPW|RX|data[7] (.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),.d(gnd),.asdata(\A_SPW_TOP|SPW|RX|data~1_combout ),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|data [7]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|data[7] .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|data[7] .power_up = "low";// synopsys translate_on// Location: LABCELL_X49_Y2_N27cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|dta_timec[4]~feeder (// Equation(s):// \A_SPW_TOP|SPW|RX|dta_timec[4]~feeder_combout = ( \A_SPW_TOP|SPW|RX|bit_d_3~q ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|RX|bit_d_3~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|dta_timec[4]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|dta_timec[4]~feeder .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|dta_timec[4]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \A_SPW_TOP|SPW|RX|dta_timec[4]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X49_Y2_N29dffeas \A_SPW_TOP|SPW|RX|dta_timec[4] (.clk(\A_SPW_TOP|SPW|RX|ready_data~combout ),.d(\A_SPW_TOP|SPW|RX|dta_timec[4]~feeder_combout ),.asdata(vcc),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|dta_timec [4]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|dta_timec[4] .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|dta_timec[4] .power_up = "low";// synopsys translate_on// Location: FF_X49_Y2_N41dffeas \A_SPW_TOP|SPW|RX|dta_timec_p[4] (.clk(\A_SPW_TOP|SPW|RX|ready_data_p~combout ),.d(gnd),.asdata(\A_SPW_TOP|SPW|RX|dta_timec [4]),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|dta_timec_p [4]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|dta_timec_p[4] .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|dta_timec_p[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y2_N36cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|data~4 (// Equation(s):// \A_SPW_TOP|SPW|RX|data~4_combout = ( \A_SPW_TOP|SPW|RX|ready_control_p_r~q & ( \A_SPW_TOP|SPW|RX|data~0_combout & ( \A_SPW_TOP|SPW|RX|data [4] ) ) ) # ( !\A_SPW_TOP|SPW|RX|ready_control_p_r~q & ( \A_SPW_TOP|SPW|RX|data~0_combout & (// \A_SPW_TOP|SPW|RX|data [4] ) ) ) # ( \A_SPW_TOP|SPW|RX|ready_control_p_r~q & ( !\A_SPW_TOP|SPW|RX|data~0_combout & ( \A_SPW_TOP|SPW|RX|data [4] ) ) ) # ( !\A_SPW_TOP|SPW|RX|ready_control_p_r~q & ( !\A_SPW_TOP|SPW|RX|data~0_combout & (// \A_SPW_TOP|SPW|RX|dta_timec_p [4] ) ) ).dataa(!\A_SPW_TOP|SPW|RX|data [4]),.datab(gnd),.datac(!\A_SPW_TOP|SPW|RX|dta_timec_p [4]),.datad(gnd),.datae(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),.dataf(!\A_SPW_TOP|SPW|RX|data~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|data~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|data~4 .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|data~4 .lut_mask = 64'h0F0F555555555555;defparam \A_SPW_TOP|SPW|RX|data~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X46_Y2_N29dffeas \A_SPW_TOP|SPW|RX|data[4] (.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),.d(gnd),.asdata(\A_SPW_TOP|SPW|RX|data~4_combout ),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|data [4]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|data[4] .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|data[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X49_Y2_N12cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|dta_timec[5]~feeder (// Equation(s):// \A_SPW_TOP|SPW|RX|dta_timec[5]~feeder_combout = ( \A_SPW_TOP|SPW|RX|bit_d_2~q ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|RX|bit_d_2~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|dta_timec[5]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|dta_timec[5]~feeder .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|dta_timec[5]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \A_SPW_TOP|SPW|RX|dta_timec[5]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X49_Y2_N14dffeas \A_SPW_TOP|SPW|RX|dta_timec[5] (.clk(\A_SPW_TOP|SPW|RX|ready_data~combout ),.d(\A_SPW_TOP|SPW|RX|dta_timec[5]~feeder_combout ),.asdata(vcc),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|dta_timec [5]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|dta_timec[5] .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|dta_timec[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X49_Y2_N6cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|dta_timec_p[5]~feeder (// Equation(s):// \A_SPW_TOP|SPW|RX|dta_timec_p[5]~feeder_combout = ( \A_SPW_TOP|SPW|RX|dta_timec [5] ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|RX|dta_timec [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|dta_timec_p[5]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|dta_timec_p[5]~feeder .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|dta_timec_p[5]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \A_SPW_TOP|SPW|RX|dta_timec_p[5]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X49_Y2_N8dffeas \A_SPW_TOP|SPW|RX|dta_timec_p[5] (.clk(\A_SPW_TOP|SPW|RX|ready_data_p~combout ),.d(\A_SPW_TOP|SPW|RX|dta_timec_p[5]~feeder_combout ),.asdata(vcc),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|dta_timec_p [5]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|dta_timec_p[5] .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|dta_timec_p[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y2_N51cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|data~3 (// Equation(s):// \A_SPW_TOP|SPW|RX|data~3_combout = ( \A_SPW_TOP|SPW|RX|ready_control_p_r~q & ( \A_SPW_TOP|SPW|RX|data [5] ) ) # ( !\A_SPW_TOP|SPW|RX|ready_control_p_r~q & ( \A_SPW_TOP|SPW|RX|data [5] & ( (\A_SPW_TOP|SPW|RX|data~0_combout ) #// (\A_SPW_TOP|SPW|RX|dta_timec_p [5]) ) ) ) # ( !\A_SPW_TOP|SPW|RX|ready_control_p_r~q & ( !\A_SPW_TOP|SPW|RX|data [5] & ( (\A_SPW_TOP|SPW|RX|dta_timec_p [5] & !\A_SPW_TOP|SPW|RX|data~0_combout ) ) ) ).dataa(gnd),.datab(!\A_SPW_TOP|SPW|RX|dta_timec_p [5]),.datac(!\A_SPW_TOP|SPW|RX|data~0_combout ),.datad(gnd),.datae(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),.dataf(!\A_SPW_TOP|SPW|RX|data [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|data~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|data~3 .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|data~3 .lut_mask = 64'h303000003F3FFFFF;defparam \A_SPW_TOP|SPW|RX|data~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X46_Y2_N50dffeas \A_SPW_TOP|SPW|RX|data[5] (.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),.d(gnd),.asdata(\A_SPW_TOP|SPW|RX|data~3_combout ),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|data [5]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|data[5] .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|data[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y2_N24cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|always16~0 (// Equation(s):// \A_SPW_TOP|SPW|RX|always16~0_combout = ( \A_SPW_TOP|SPW|RX|data [4] & ( \A_SPW_TOP|SPW|RX|data [5] & ( !\A_SPW_TOP|SPW|RX|data [3] $ (!\A_SPW_TOP|SPW|RX|data [6] $ (!\A_SPW_TOP|SPW|RX|data [2] $ (!\A_SPW_TOP|SPW|RX|data [7]))) ) ) ) # (// !\A_SPW_TOP|SPW|RX|data [4] & ( \A_SPW_TOP|SPW|RX|data [5] & ( !\A_SPW_TOP|SPW|RX|data [3] $ (!\A_SPW_TOP|SPW|RX|data [6] $ (!\A_SPW_TOP|SPW|RX|data [2] $ (\A_SPW_TOP|SPW|RX|data [7]))) ) ) ) # ( \A_SPW_TOP|SPW|RX|data [4] & ( !\A_SPW_TOP|SPW|RX|data [5]// & ( !\A_SPW_TOP|SPW|RX|data [3] $ (!\A_SPW_TOP|SPW|RX|data [6] $ (!\A_SPW_TOP|SPW|RX|data [2] $ (\A_SPW_TOP|SPW|RX|data [7]))) ) ) ) # ( !\A_SPW_TOP|SPW|RX|data [4] & ( !\A_SPW_TOP|SPW|RX|data [5] & ( !\A_SPW_TOP|SPW|RX|data [3] $ (!\A_SPW_TOP|SPW|RX|data// [6] $ (!\A_SPW_TOP|SPW|RX|data [2] $ (!\A_SPW_TOP|SPW|RX|data [7]))) ) ) ).dataa(!\A_SPW_TOP|SPW|RX|data [3]),.datab(!\A_SPW_TOP|SPW|RX|data [6]),.datac(!\A_SPW_TOP|SPW|RX|data [2]),.datad(!\A_SPW_TOP|SPW|RX|data [7]),.datae(!\A_SPW_TOP|SPW|RX|data [4]),.dataf(!\A_SPW_TOP|SPW|RX|data [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|always16~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|always16~0 .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|always16~0 .lut_mask = 64'h6996966996696996;defparam \A_SPW_TOP|SPW|RX|always16~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X49_Y2_N24cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|dta_timec[0]~feeder (// Equation(s):// \A_SPW_TOP|SPW|RX|dta_timec[0]~feeder_combout = ( \A_SPW_TOP|SPW|RX|bit_d_7~q ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|RX|bit_d_7~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|dta_timec[0]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|dta_timec[0]~feeder .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|dta_timec[0]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \A_SPW_TOP|SPW|RX|dta_timec[0]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X49_Y2_N26dffeas \A_SPW_TOP|SPW|RX|dta_timec[0] (.clk(\A_SPW_TOP|SPW|RX|ready_data~combout ),.d(\A_SPW_TOP|SPW|RX|dta_timec[0]~feeder_combout ),.asdata(vcc),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|dta_timec [0]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|dta_timec[0] .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|dta_timec[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X49_Y2_N57cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|dta_timec_p[0]~feeder (// Equation(s):// \A_SPW_TOP|SPW|RX|dta_timec_p[0]~feeder_combout = ( \A_SPW_TOP|SPW|RX|dta_timec [0] ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|RX|dta_timec [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|dta_timec_p[0]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|dta_timec_p[0]~feeder .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|dta_timec_p[0]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \A_SPW_TOP|SPW|RX|dta_timec_p[0]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X49_Y2_N59dffeas \A_SPW_TOP|SPW|RX|dta_timec_p[0] (.clk(\A_SPW_TOP|SPW|RX|ready_data_p~combout ),.d(\A_SPW_TOP|SPW|RX|dta_timec_p[0]~feeder_combout ),.asdata(vcc),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|dta_timec_p [0]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|dta_timec_p[0] .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|dta_timec_p[0] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X47_Y2_N21cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|data~8 (// Equation(s):// \A_SPW_TOP|SPW|RX|data~8_combout = ( \A_SPW_TOP|SPW|RX|data~0_combout & ( \A_SPW_TOP|SPW|RX|data [0] ) ) # ( !\A_SPW_TOP|SPW|RX|data~0_combout & ( \A_SPW_TOP|SPW|RX|data [0] & ( (\A_SPW_TOP|SPW|RX|ready_control_p_r~q ) # (\A_SPW_TOP|SPW|RX|dta_timec_p// [0]) ) ) ) # ( !\A_SPW_TOP|SPW|RX|data~0_combout & ( !\A_SPW_TOP|SPW|RX|data [0] & ( (\A_SPW_TOP|SPW|RX|dta_timec_p [0] & !\A_SPW_TOP|SPW|RX|ready_control_p_r~q ) ) ) ).dataa(!\A_SPW_TOP|SPW|RX|dta_timec_p [0]),.datab(gnd),.datac(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),.datad(gnd),.datae(!\A_SPW_TOP|SPW|RX|data~0_combout ),.dataf(!\A_SPW_TOP|SPW|RX|data [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|data~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|data~8 .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|data~8 .lut_mask = 64'h505000005F5FFFFF;defparam \A_SPW_TOP|SPW|RX|data~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y2_N20dffeas \A_SPW_TOP|SPW|RX|data[0] (.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),.d(gnd),.asdata(\A_SPW_TOP|SPW|RX|data~8_combout ),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|data [0]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|data[0] .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|data[0] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X50_Y2_N45cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|dta_timec[1]~feeder (// Equation(s):// \A_SPW_TOP|SPW|RX|dta_timec[1]~feeder_combout = ( \A_SPW_TOP|SPW|RX|bit_d_6~q ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|RX|bit_d_6~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|dta_timec[1]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|dta_timec[1]~feeder .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|dta_timec[1]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \A_SPW_TOP|SPW|RX|dta_timec[1]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X50_Y2_N47dffeas \A_SPW_TOP|SPW|RX|dta_timec[1] (.clk(\A_SPW_TOP|SPW|RX|ready_data~combout ),.d(\A_SPW_TOP|SPW|RX|dta_timec[1]~feeder_combout ),.asdata(vcc),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|dta_timec [1]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|dta_timec[1] .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|dta_timec[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X49_Y2_N33cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|dta_timec_p[1]~feeder (// Equation(s):// \A_SPW_TOP|SPW|RX|dta_timec_p[1]~feeder_combout = ( \A_SPW_TOP|SPW|RX|dta_timec [1] ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|RX|dta_timec [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|dta_timec_p[1]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|dta_timec_p[1]~feeder .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|dta_timec_p[1]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \A_SPW_TOP|SPW|RX|dta_timec_p[1]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X49_Y2_N35dffeas \A_SPW_TOP|SPW|RX|dta_timec_p[1] (.clk(\A_SPW_TOP|SPW|RX|ready_data_p~combout ),.d(\A_SPW_TOP|SPW|RX|dta_timec_p[1]~feeder_combout ),.asdata(vcc),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|dta_timec_p [1]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|dta_timec_p[1] .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|dta_timec_p[1] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X47_Y2_N36cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|data~7 (// Equation(s):// \A_SPW_TOP|SPW|RX|data~7_combout = ( \A_SPW_TOP|SPW|RX|data~0_combout & ( \A_SPW_TOP|SPW|RX|data [1] ) ) # ( !\A_SPW_TOP|SPW|RX|data~0_combout & ( \A_SPW_TOP|SPW|RX|data [1] & ( (\A_SPW_TOP|SPW|RX|ready_control_p_r~q ) # (\A_SPW_TOP|SPW|RX|dta_timec_p// [1]) ) ) ) # ( !\A_SPW_TOP|SPW|RX|data~0_combout & ( !\A_SPW_TOP|SPW|RX|data [1] & ( (\A_SPW_TOP|SPW|RX|dta_timec_p [1] & !\A_SPW_TOP|SPW|RX|ready_control_p_r~q ) ) ) ).dataa(!\A_SPW_TOP|SPW|RX|dta_timec_p [1]),.datab(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),.datac(gnd),.datad(gnd),.datae(!\A_SPW_TOP|SPW|RX|data~0_combout ),.dataf(!\A_SPW_TOP|SPW|RX|data [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|data~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|data~7 .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|data~7 .lut_mask = 64'h444400007777FFFF;defparam \A_SPW_TOP|SPW|RX|data~7 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y2_N41dffeas \A_SPW_TOP|SPW|RX|data[1] (.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),.d(gnd),.asdata(\A_SPW_TOP|SPW|RX|data~7_combout ),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|data [1]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|data[1] .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|data[1] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X47_Y2_N48cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|always16~1 (// Equation(s):// \A_SPW_TOP|SPW|RX|always16~1_combout = ( \A_SPW_TOP|SPW|RX|data [1] & ( !\A_SPW_TOP|SPW|RX|data [0] ) ) # ( !\A_SPW_TOP|SPW|RX|data [1] & ( \A_SPW_TOP|SPW|RX|data [0] ) ).dataa(gnd),.datab(gnd),.datac(!\A_SPW_TOP|SPW|RX|data [0]),.datad(gnd),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|RX|data [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|always16~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|always16~1 .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|always16~1 .lut_mask = 64'h0F0F0F0FF0F0F0F0;defparam \A_SPW_TOP|SPW|RX|always16~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X50_Y2_N6cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_error_d~1 (// Equation(s):// \A_SPW_TOP|SPW|RX|rx_error_d~1_combout = ( \A_SPW_TOP|SPW|RX|always16~0_combout & ( \A_SPW_TOP|SPW|RX|always16~1_combout & ( (((!\A_SPW_TOP|SPW|RX|always15~0_combout & \A_SPW_TOP|SPW|RX|rx_error_c~0_combout )) # (\A_SPW_TOP|SPW|RX|rx_error_d~0_combout// )) # (\A_SPW_TOP|SPW|RX|rx_error_d~q ) ) ) ) # ( !\A_SPW_TOP|SPW|RX|always16~0_combout & ( \A_SPW_TOP|SPW|RX|always16~1_combout & ( (((\A_SPW_TOP|SPW|RX|always15~0_combout & \A_SPW_TOP|SPW|RX|rx_error_c~0_combout )) #// (\A_SPW_TOP|SPW|RX|rx_error_d~0_combout )) # (\A_SPW_TOP|SPW|RX|rx_error_d~q ) ) ) ) # ( \A_SPW_TOP|SPW|RX|always16~0_combout & ( !\A_SPW_TOP|SPW|RX|always16~1_combout & ( (((\A_SPW_TOP|SPW|RX|always15~0_combout & \A_SPW_TOP|SPW|RX|rx_error_c~0_combout// )) # (\A_SPW_TOP|SPW|RX|rx_error_d~0_combout )) # (\A_SPW_TOP|SPW|RX|rx_error_d~q ) ) ) ) # ( !\A_SPW_TOP|SPW|RX|always16~0_combout & ( !\A_SPW_TOP|SPW|RX|always16~1_combout & ( (((!\A_SPW_TOP|SPW|RX|always15~0_combout &// \A_SPW_TOP|SPW|RX|rx_error_c~0_combout )) # (\A_SPW_TOP|SPW|RX|rx_error_d~0_combout )) # (\A_SPW_TOP|SPW|RX|rx_error_d~q ) ) ) ).dataa(!\A_SPW_TOP|SPW|RX|always15~0_combout ),.datab(!\A_SPW_TOP|SPW|RX|rx_error_c~0_combout ),.datac(!\A_SPW_TOP|SPW|RX|rx_error_d~q ),.datad(!\A_SPW_TOP|SPW|RX|rx_error_d~0_combout ),.datae(!\A_SPW_TOP|SPW|RX|always16~0_combout ),.dataf(!\A_SPW_TOP|SPW|RX|always16~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|rx_error_d~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|rx_error_d~1 .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|rx_error_d~1 .lut_mask = 64'h2FFF1FFF1FFF2FFF;defparam \A_SPW_TOP|SPW|RX|rx_error_d~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X49_Y2_N50dffeas \A_SPW_TOP|SPW|RX|rx_error_d (.clk(\A_SPW_TOP|SPW|RX|ready_data_p~combout ),.d(gnd),.asdata(\A_SPW_TOP|SPW|RX|rx_error_d~1_combout ),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|rx_error_d~q ),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|rx_error_d .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|rx_error_d .power_up = "low";// synopsys translate_on// Location: FF_X49_Y3_N34dffeas \A_SPW_TOP|SPW|RX|bit_c_3 (.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),.d(gnd),.asdata(\A_SPW_TOP|SPW|RX|bit_c_1~q ),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|bit_c_3~q ),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|bit_c_3 .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|bit_c_3 .power_up = "low";// synopsys translate_on// Location: FF_X50_Y3_N26dffeas \A_SPW_TOP|SPW|RX|parity_rec_c (.clk(\A_SPW_TOP|SPW|RX|always1~0_combout ),.d(gnd),.asdata(\A_SPW_TOP|SPW|RX|bit_c_3~q ),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|parity_rec_c~q ),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|parity_rec_c .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|parity_rec_c .power_up = "low";// synopsys translate_on// Location: MLABCELL_X50_Y3_N45cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|always16~2 (// Equation(s):// \A_SPW_TOP|SPW|RX|always16~2_combout = ( \A_SPW_TOP|SPW|RX|parity_rec_c~q & ( !\A_SPW_TOP|SPW|RX|control_r [2] ) ) # ( !\A_SPW_TOP|SPW|RX|parity_rec_c~q & ( \A_SPW_TOP|SPW|RX|control_r [2] ) ).dataa(!\A_SPW_TOP|SPW|RX|control_r [2]),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|RX|parity_rec_c~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|always16~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|always16~2 .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|always16~2 .lut_mask = 64'h55555555AAAAAAAA;defparam \A_SPW_TOP|SPW|RX|always16~2 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X50_Y3_N9cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_error_c~1 (// Equation(s):// \A_SPW_TOP|SPW|RX|rx_error_c~1_combout = ( \A_SPW_TOP|SPW|RX|control [1] & ( \A_SPW_TOP|SPW|RX|parity_rec_c~q & ( (\A_SPW_TOP|SPW|RX|last_is_control~q & (!\A_SPW_TOP|SPW|RX|control_r [2] $ (\A_SPW_TOP|SPW|RX|control [0]))) ) ) ) # (// !\A_SPW_TOP|SPW|RX|control [1] & ( \A_SPW_TOP|SPW|RX|parity_rec_c~q & ( (\A_SPW_TOP|SPW|RX|last_is_control~q & (!\A_SPW_TOP|SPW|RX|control_r [2] $ (!\A_SPW_TOP|SPW|RX|control [0]))) ) ) ) # ( \A_SPW_TOP|SPW|RX|control [1] & (// !\A_SPW_TOP|SPW|RX|parity_rec_c~q & ( (\A_SPW_TOP|SPW|RX|last_is_control~q & (!\A_SPW_TOP|SPW|RX|control_r [2] $ (!\A_SPW_TOP|SPW|RX|control [0]))) ) ) ) # ( !\A_SPW_TOP|SPW|RX|control [1] & ( !\A_SPW_TOP|SPW|RX|parity_rec_c~q & (// (\A_SPW_TOP|SPW|RX|last_is_control~q & (!\A_SPW_TOP|SPW|RX|control_r [2] $ (\A_SPW_TOP|SPW|RX|control [0]))) ) ) ).dataa(!\A_SPW_TOP|SPW|RX|control_r [2]),.datab(gnd),.datac(!\A_SPW_TOP|SPW|RX|last_is_control~q ),.datad(!\A_SPW_TOP|SPW|RX|control [0]),.datae(!\A_SPW_TOP|SPW|RX|control [1]),.dataf(!\A_SPW_TOP|SPW|RX|parity_rec_c~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|rx_error_c~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|rx_error_c~1 .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|rx_error_c~1 .lut_mask = 64'h0A05050A050A0A05;defparam \A_SPW_TOP|SPW|RX|rx_error_c~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X50_Y3_N21cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_error_c~2 (// Equation(s):// \A_SPW_TOP|SPW|RX|rx_error_c~2_combout = ( \A_SPW_TOP|SPW|RX|always16~1_combout & ( \A_SPW_TOP|SPW|RX|rx_error_c~1_combout ) ) # ( !\A_SPW_TOP|SPW|RX|always16~1_combout & ( \A_SPW_TOP|SPW|RX|rx_error_c~1_combout ) ) # (// \A_SPW_TOP|SPW|RX|always16~1_combout & ( !\A_SPW_TOP|SPW|RX|rx_error_c~1_combout & ( ((\A_SPW_TOP|SPW|RX|rx_error_c~0_combout & (!\A_SPW_TOP|SPW|RX|always16~2_combout $ (!\A_SPW_TOP|SPW|RX|always16~0_combout )))) # (\A_SPW_TOP|SPW|RX|rx_error_c~q ) )// ) ) # ( !\A_SPW_TOP|SPW|RX|always16~1_combout & ( !\A_SPW_TOP|SPW|RX|rx_error_c~1_combout & ( ((\A_SPW_TOP|SPW|RX|rx_error_c~0_combout & (!\A_SPW_TOP|SPW|RX|always16~2_combout $ (\A_SPW_TOP|SPW|RX|always16~0_combout )))) #// (\A_SPW_TOP|SPW|RX|rx_error_c~q ) ) ) ).dataa(!\A_SPW_TOP|SPW|RX|rx_error_c~q ),.datab(!\A_SPW_TOP|SPW|RX|always16~2_combout ),.datac(!\A_SPW_TOP|SPW|RX|rx_error_c~0_combout ),.datad(!\A_SPW_TOP|SPW|RX|always16~0_combout ),.datae(!\A_SPW_TOP|SPW|RX|always16~1_combout ),.dataf(!\A_SPW_TOP|SPW|RX|rx_error_c~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|rx_error_c~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|rx_error_c~2 .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|rx_error_c~2 .lut_mask = 64'h5D57575DFFFFFFFF;defparam \A_SPW_TOP|SPW|RX|rx_error_c~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X50_Y3_N2dffeas \A_SPW_TOP|SPW|RX|rx_error_c (.clk(\A_SPW_TOP|SPW|RX|always2~0_combout ),.d(gnd),.asdata(\A_SPW_TOP|SPW|RX|rx_error_c~2_combout ),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|rx_error_c~q ),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|rx_error_c .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|rx_error_c .power_up = "low";// synopsys translate_on// Location: MLABCELL_X47_Y3_N42cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|last_is_timec~0 (// Equation(s):// \A_SPW_TOP|SPW|RX|last_is_timec~0_combout = ( \A_SPW_TOP|SPW|RX|control [2] & ( \A_SPW_TOP|SPW|RX|control [1] & ( (!\A_SPW_TOP|SPW|RX|ready_control_p_r~q & ((!\A_SPW_TOP|SPW|RX|ready_data_p_r~q & ((\A_SPW_TOP|SPW|RX|last_is_timec~q ))) #// (\A_SPW_TOP|SPW|RX|ready_data_p_r~q & (\A_SPW_TOP|SPW|RX|control [0])))) ) ) ) # ( !\A_SPW_TOP|SPW|RX|control [2] & ( \A_SPW_TOP|SPW|RX|control [1] & ( (\A_SPW_TOP|SPW|RX|last_is_timec~q & (!\A_SPW_TOP|SPW|RX|ready_data_p_r~q &// !\A_SPW_TOP|SPW|RX|ready_control_p_r~q )) ) ) ) # ( \A_SPW_TOP|SPW|RX|control [2] & ( !\A_SPW_TOP|SPW|RX|control [1] & ( (\A_SPW_TOP|SPW|RX|last_is_timec~q & (!\A_SPW_TOP|SPW|RX|ready_data_p_r~q & !\A_SPW_TOP|SPW|RX|ready_control_p_r~q )) ) ) ) # (// !\A_SPW_TOP|SPW|RX|control [2] & ( !\A_SPW_TOP|SPW|RX|control [1] & ( (\A_SPW_TOP|SPW|RX|last_is_timec~q & (!\A_SPW_TOP|SPW|RX|ready_data_p_r~q & !\A_SPW_TOP|SPW|RX|ready_control_p_r~q )) ) ) ).dataa(!\A_SPW_TOP|SPW|RX|control [0]),.datab(!\A_SPW_TOP|SPW|RX|last_is_timec~q ),.datac(!\A_SPW_TOP|SPW|RX|ready_data_p_r~q ),.datad(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),.datae(!\A_SPW_TOP|SPW|RX|control [2]),.dataf(!\A_SPW_TOP|SPW|RX|control [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|last_is_timec~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|last_is_timec~0 .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|last_is_timec~0 .lut_mask = 64'h3000300030003500;defparam \A_SPW_TOP|SPW|RX|last_is_timec~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y3_N47dffeas \A_SPW_TOP|SPW|RX|last_is_timec (.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),.d(gnd),.asdata(\A_SPW_TOP|SPW|RX|last_is_timec~0_combout ),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(!\A_SPW_TOP|SPW|RX|state_data_process.01~q ),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|last_is_timec~q ),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|last_is_timec .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|last_is_timec .power_up = "low";// synopsys translate_on// Location: MLABCELL_X47_Y3_N51cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_got_null~0 (// Equation(s):// \A_SPW_TOP|SPW|RX|rx_got_null~0_combout = ( \A_SPW_TOP|SPW|RX|last_is_control~q & ( (!\A_SPW_TOP|SPW|RX|last_is_timec~q ) # (\A_SPW_TOP|SPW|RX|rx_got_null~q ) ) ) # ( !\A_SPW_TOP|SPW|RX|last_is_control~q & ( (\A_SPW_TOP|SPW|RX|rx_got_null~q &// \A_SPW_TOP|SPW|RX|last_is_timec~q ) ) ).dataa(!\A_SPW_TOP|SPW|RX|rx_got_null~q ),.datab(gnd),.datac(!\A_SPW_TOP|SPW|RX|last_is_timec~q ),.datad(gnd),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|RX|last_is_control~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|rx_got_null~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|rx_got_null~0 .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|rx_got_null~0 .lut_mask = 64'h05050505F5F5F5F5;defparam \A_SPW_TOP|SPW|RX|rx_got_null~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y3_N56dffeas \A_SPW_TOP|SPW|RX|rx_got_null (.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),.d(gnd),.asdata(\A_SPW_TOP|SPW|RX|rx_got_null~0_combout ),.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(!\A_SPW_TOP|SPW|RX|last_is_data~q ),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|RX|rx_got_null~q ),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|rx_got_null .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|RX|rx_got_null .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y25_N30cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal20~0 (// Equation(s):// \u0|mm_interconnect_0|router|Equal20~0_combout = ( \u0|mm_interconnect_0|router|Equal7~1_combout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout &// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout &// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ))) ) ).dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~3_combout ),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|router|Equal7~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router|Equal20~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router|Equal20~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|router|Equal20~0 .lut_mask = 64'h0000000000040004;defparam \u0|mm_interconnect_0|router|Equal20~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y31_N9cyclonev_lcell_comb \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder (// Equation(s):// \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder .extended_lut = "off";defparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder .shared_arith = "off";// synopsys translate_on// Location: HPSINTERFACECLOCKSRESETS_X32_Y50_N111cyclonev_hps_interface_clocks_resets \u0|hps_0|fpga_interfaces|clocks_resets (.f2h_cold_rst_req_n(vcc),.f2h_dbg_rst_req_n(vcc),.f2h_pending_rst_ack(vcc),.f2h_periph_ref_clk(gnd),.f2h_sdram_ref_clk(gnd),.f2h_warm_rst_req_n(vcc),.ptp_ref_clk(gnd),.h2f_cold_rst_n(\u0|hps_0|fpga_interfaces|clocks_resets~h2f_cold_rst_n ),.h2f_pending_rst_req_n(),.h2f_rst_n(\u0|hps_0|fpga_interfaces|h2f_rst_n [0]),.h2f_user0_clk(),.h2f_user1_clk(),.h2f_user2_clk());// synopsys translate_offdefparam \u0|hps_0|fpga_interfaces|clocks_resets .h2f_user0_clk_freq = 100;defparam \u0|hps_0|fpga_interfaces|clocks_resets .h2f_user1_clk_freq = 100;defparam \u0|hps_0|fpga_interfaces|clocks_resets .h2f_user2_clk_freq = 100;// synopsys translate_on// Location: CLKCTRL_G10cyclonev_clkena \u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0 (.inclk(\u0|hps_0|fpga_interfaces|h2f_rst_n [0]),.ena(vcc),.outclk(\u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0_outclk ),.enaout());// synopsys translate_offdefparam \u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0 .clock_type = "global clock";defparam \u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0 .disable_mode = "low";defparam \u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0 .ena_register_mode = "always enabled";defparam \u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0 .ena_register_power_up = "high";defparam \u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0 .test_syn = "high";// synopsys translate_on// Location: FF_X28_Y31_N10dffeas \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout ),.asdata(vcc),.clrn(\u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [1]),.prn(vcc));// synopsys translate_offdefparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] .is_wysiwyg = "true";defparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] .power_up = "low";// synopsys translate_on// Location: FF_X28_Y31_N2dffeas \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [1]),.clrn(\u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [0]),.prn(vcc));// synopsys translate_offdefparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] .is_wysiwyg = "true";defparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] .power_up = "low";// synopsys translate_on// Location: FF_X28_Y31_N23dffeas \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [0]),.clrn(\u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.prn(vcc));// synopsys translate_offdefparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out .is_wysiwyg = "true";defparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out .power_up = "low";// synopsys translate_on// Location: FF_X28_Y25_N32dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[14] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|router|Equal20~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [14]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[14] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[14] .power_up = "low";// synopsys translate_on// Location: FF_X28_Y15_N56dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~5_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][5]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y14_N54cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~2 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~2_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~0_combout & (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0] $ (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [1]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0]),.datac(gnd),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~2 .lut_mask = 64'h0000000033CC33CC;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y14_N56dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y14_N36cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~q & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [1] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0 .lut_mask = 64'h00000000FF00FF00;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y18_N9cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~4 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~4_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~0_combout ) # ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1])) ) ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~0_combout &// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~0_combout ),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout ),.datad(gnd),.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0]),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~4 .lut_mask = 64'h000000004040BFBF;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~4 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y18_N0cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y18_N2dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y18_N39cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~1 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~1_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0] $ (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~0_combout )) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout ))) ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0]),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout ),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~1 .lut_mask = 64'h0C0C0C0C4C8C4C8C;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y15_N20dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~6_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][6]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][6] .power_up = "low";// synopsys translate_on// Location: FF_X22_Y18_N2dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y18_N0cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~0 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~0_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][129]~q & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~0_combout & (// (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0_combout )) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1])) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][129]~q & (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~0_combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout &// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0_combout )) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ))) ) ) ) # (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][129]~q & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~0_combout & ( ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout &// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0_combout )) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][129]~q & (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~0_combout & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout ),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0_combout ),.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][129]~q ),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h00300F3F50705F7F;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y17_N47dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y18_N6cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~1_combout & (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h000000000F0F0F0F;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y17_N45cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y17_N47dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y17_N42cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout = (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout $// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(gnd),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h55AA55AA44EE44EE;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y17_N44dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y17_N57cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout = (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] $// (((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h0AF50AF50CFC0CFC;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y17_N59dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";// synopsys translate_on// Location: FF_X17_Y17_N26dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";// synopsys translate_on// Location: FF_X17_Y17_N2dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y17_N0cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout = (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h0E04F4FE0404FEFE;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y17_N30cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout = (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout &// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .lut_mask = 64'hC0C0C0C000000000;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y18_N51cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout = (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q )) ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q $// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ))) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q )) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .lut_mask = 64'hA05AA05A00A000A0;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y18_N18cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout &// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h0003333300000000;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y17_N27cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] &// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datab(gnd),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h00000000A000A000;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y17_N9cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout = (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] $// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .lut_mask = 64'h5A5A5A5A77447744;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y17_N5dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";// synopsys translate_on// Location: FF_X17_Y17_N50dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y17_N48cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout = (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) ) # (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [5]) ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout// & !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .lut_mask = 64'h3030CFCF5500FFAA;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y18_N9cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h000000000000FF00;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y17_N15cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout & (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout & (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout & (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) ) ) # ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout// & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout & (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout & (// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ))) ) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.datac(gnd),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h2233FFFF3333FFFF;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y17_N17dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y17_N24cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][75]~q ))) ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][75]~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][75]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h000F000F303F303F;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y17_N56dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";// synopsys translate_on// Location: FF_X17_Y17_N31dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y17_N54cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][74]~q ))) ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][74]~q ))) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][74]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h303F303F505F505F;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y17_N53dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y17_N6cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q )) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q & (// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q )) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q )) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q & (// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q )) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q ),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h2320202313101013;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y17_N8dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y17_N21cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] $ (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h3C3C3C3CCCCCCCCC;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y17_N20dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y17_N18cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][76]~q ))) ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][76]~q ) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),.datac(gnd),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][76]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h0033003344774477;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y17_N59dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y17_N42cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0_combout & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ) ) ) )// # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q & (// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ) ) ) ) # (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0_combout & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ) ) ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q & (// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q $ (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0_combout ),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q ),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q ),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h00C300AA003300AA;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y17_N44dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";// synopsys translate_on// Location: FF_X17_Y17_N35dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y17_N33cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][78]~q ) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][78]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h005500550A5F0A5F;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y17_N35dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";// synopsys translate_on// Location: FF_X17_Y17_N8dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y17_N6cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][77]~q ))) ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][77]~q ) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datab(gnd),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][77]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h000F000F505F505F;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y17_N29dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y17_N48cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q &// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q & !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q )) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q ),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q ),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hC000C00000000000;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y17_N54cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2_combout = !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $// (((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] &// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3])))).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h7F807F807F807F80;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y17_N51cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q &// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q & !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q )) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q & (// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q )) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q ) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q ),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q ),.datac(gnd),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h77FF77FF88008800;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y17_N36cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1_combout & (// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2_combout )) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1_combout & (// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ) #// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2_combout ))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h3330333003000300;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y17_N38dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y17_N57cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout = (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]))).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1 .lut_mask = 64'h8000800080008000;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y17_N0cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout &// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q $// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q $// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout )) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout & (// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q $ (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout )) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout &// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q $// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout )))) ) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q ),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout ),.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h1020132313231020;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y17_N2dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y17_N18cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] &// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hC000C00000000000;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y17_N24cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] &// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ) ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout &// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout )) ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout &// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout )) ) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q ),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout ),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h00220000002200F0;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y17_N13dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y17_N27cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy~q &// (((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1_combout ) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [7])) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy~q ),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1_combout ),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h3133313331333133;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y17_N39cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q & (// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout &// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout )) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q & (// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout ) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),.datac(gnd),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h3300330011001100;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y17_N41dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y17_N48cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy~q & (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h000000000F0F0F0F;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y17_N30cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0_combout = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy~q & (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q &// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q & !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q ),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q ),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q ),.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy~q ),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h2000000000000000;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y17_N54cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0] ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0]) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129]~q ))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0]),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129]~q ),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0 .lut_mask = 64'h0333033333333333;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y18_N44dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y18_N42cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3_combout = (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66])) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][66]~q ))).dataa(gnd),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][66]~q ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h0C3F0C3F0C3F0C3F;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y17_N8dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y17_N18cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~q & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0_combout & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout ) #// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~q ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0_combout ),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1_combout ),.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout ),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00000000FFFFF0A0;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y17_N36cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout &// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0] ).dataa(gnd),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hFFFFFFFF30303030;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y17_N53dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~0_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y17_N51cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0] &// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129]~q ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0]) #// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0] & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129]~q )) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0]),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0]),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0 .lut_mask = 64'hF0F3F0F300330033;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y17_N57cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~1 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~1_combout = (\u0|mm_interconnect_0|rsp_demux_010|WideOr0~0_combout & !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0_combout ).dataa(!\u0|mm_interconnect_0|rsp_demux_010|WideOr0~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0_combout ),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~1 .lut_mask = 64'h5050505050505050;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y17_N33cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[0]~0 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~1_combout & ( ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0] &// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~1_combout & (// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1])) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0]),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h30FF30FF0F3F0F3F;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y17_N35dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y17_N9cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout = (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0] & \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0]).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0]),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0 .lut_mask = 64'h00AA00AA00AA00AA;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y16_N44dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][9] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~9_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][9]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][9] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][9] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y33_N0cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout = ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0] ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0 .lut_mask = 64'h3333333300000000;defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X45_Y4_N39cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|enable_tx~0 (// Equation(s):// \A_SPW_TOP|SPW|FSM|enable_tx~0_combout = ( \A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q & ( !\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q ) ).dataa(gnd),.datab(gnd),.datac(!\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q ),.datad(gnd),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|FSM|enable_tx~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|FSM|enable_tx~0 .extended_lut = "off";defparam \A_SPW_TOP|SPW|FSM|enable_tx~0 .lut_mask = 64'h00000000F0F0F0F0;defparam \A_SPW_TOP|SPW|FSM|enable_tx~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X45_Y4_N41dffeas \A_SPW_TOP|SPW|FSM|enable_tx (.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),.d(\A_SPW_TOP|SPW|FSM|enable_tx~0_combout ),.asdata(vcc),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|SPW|FSM|enable_tx~q ),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|SPW|FSM|enable_tx .is_wysiwyg = "true";defparam \A_SPW_TOP|SPW|FSM|enable_tx .power_up = "low";// synopsys translate_on// Location: LABCELL_X36_Y10_N27cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add2~0 (// Equation(s):// \A_SPW_TOP|tx_data|Add2~0_combout = ( \A_SPW_TOP|tx_data|counter_reader [1] & ( !\A_SPW_TOP|tx_data|counter_reader [0] ) ) # ( !\A_SPW_TOP|tx_data|counter_reader [1] & ( \A_SPW_TOP|tx_data|counter_reader [0] ) ).dataa(gnd),.datab(gnd),.datac(!\A_SPW_TOP|tx_data|counter_reader [0]),.datad(gnd),.datae(gnd),.dataf(!\A_SPW_TOP|tx_data|counter_reader [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|tx_data|Add2~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|tx_data|Add2~0 .extended_lut = "off";defparam \A_SPW_TOP|tx_data|Add2~0 .lut_mask = 64'h0F0F0F0FF0F0F0F0;defparam \A_SPW_TOP|tx_data|Add2~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X36_Y10_N41dffeas \A_SPW_TOP|tx_data|counter_reader[1] (.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),.d(gnd),.asdata(\A_SPW_TOP|tx_data|Add2~0_combout ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\A_SPW_TOP|tx_data|always3~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|tx_data|counter_reader [1]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|tx_data|counter_reader[1] .is_wysiwyg = "true";defparam \A_SPW_TOP|tx_data|counter_reader[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X36_Y10_N42cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add2~1 (// Equation(s):// \A_SPW_TOP|tx_data|Add2~1_combout = ( \A_SPW_TOP|tx_data|counter_reader [0] & ( \A_SPW_TOP|tx_data|counter_reader [2] & ( !\A_SPW_TOP|tx_data|counter_reader [1] ) ) ) # ( !\A_SPW_TOP|tx_data|counter_reader [0] & ( \A_SPW_TOP|tx_data|counter_reader [2] )// ) # ( \A_SPW_TOP|tx_data|counter_reader [0] & ( !\A_SPW_TOP|tx_data|counter_reader [2] & ( \A_SPW_TOP|tx_data|counter_reader [1] ) ) ).dataa(gnd),.datab(!\A_SPW_TOP|tx_data|counter_reader [1]),.datac(gnd),.datad(gnd),.datae(!\A_SPW_TOP|tx_data|counter_reader [0]),.dataf(!\A_SPW_TOP|tx_data|counter_reader [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|tx_data|Add2~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|tx_data|Add2~1 .extended_lut = "off";defparam \A_SPW_TOP|tx_data|Add2~1 .lut_mask = 64'h00003333FFFFCCCC;defparam \A_SPW_TOP|tx_data|Add2~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X36_Y10_N53dffeas \A_SPW_TOP|tx_data|counter_reader[2] (.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),.d(gnd),.asdata(\A_SPW_TOP|tx_data|Add2~1_combout ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\A_SPW_TOP|tx_data|always3~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|tx_data|counter_reader [2]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|tx_data|counter_reader[2] .is_wysiwyg = "true";defparam \A_SPW_TOP|tx_data|counter_reader[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X36_Y10_N0cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add3~1 (// Equation(s):// \A_SPW_TOP|tx_data|Add3~1_sumout = SUM(( !\A_SPW_TOP|tx_data|counter_writer [0] $ (!\A_SPW_TOP|tx_data|counter_reader [0]) ) + ( !VCC ) + ( !VCC ))// \A_SPW_TOP|tx_data|Add3~2 = CARRY(( !\A_SPW_TOP|tx_data|counter_writer [0] $ (!\A_SPW_TOP|tx_data|counter_reader [0]) ) + ( !VCC ) + ( !VCC ))// \A_SPW_TOP|tx_data|Add3~3 = SHARE((!\A_SPW_TOP|tx_data|counter_reader [0]) # (\A_SPW_TOP|tx_data|counter_writer [0])).dataa(gnd),.datab(!\A_SPW_TOP|tx_data|counter_writer [0]),.datac(gnd),.datad(!\A_SPW_TOP|tx_data|counter_reader [0]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(),.sumout(\A_SPW_TOP|tx_data|Add3~1_sumout ),.cout(\A_SPW_TOP|tx_data|Add3~2 ),.shareout(\A_SPW_TOP|tx_data|Add3~3 ));// synopsys translate_offdefparam \A_SPW_TOP|tx_data|Add3~1 .extended_lut = "off";defparam \A_SPW_TOP|tx_data|Add3~1 .lut_mask = 64'h0000FF33000033CC;defparam \A_SPW_TOP|tx_data|Add3~1 .shared_arith = "on";// synopsys translate_on// Location: LABCELL_X36_Y10_N3cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add3~5 (// Equation(s):// \A_SPW_TOP|tx_data|Add3~5_sumout = SUM(( !\A_SPW_TOP|tx_data|counter_writer [1] $ (\A_SPW_TOP|tx_data|counter_reader [1]) ) + ( \A_SPW_TOP|tx_data|Add3~3 ) + ( \A_SPW_TOP|tx_data|Add3~2 ))// \A_SPW_TOP|tx_data|Add3~6 = CARRY(( !\A_SPW_TOP|tx_data|counter_writer [1] $ (\A_SPW_TOP|tx_data|counter_reader [1]) ) + ( \A_SPW_TOP|tx_data|Add3~3 ) + ( \A_SPW_TOP|tx_data|Add3~2 ))// \A_SPW_TOP|tx_data|Add3~7 = SHARE((\A_SPW_TOP|tx_data|counter_writer [1] & !\A_SPW_TOP|tx_data|counter_reader [1])).dataa(!\A_SPW_TOP|tx_data|counter_writer [1]),.datab(gnd),.datac(!\A_SPW_TOP|tx_data|counter_reader [1]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\A_SPW_TOP|tx_data|Add3~2 ),.sharein(\A_SPW_TOP|tx_data|Add3~3 ),.combout(),.sumout(\A_SPW_TOP|tx_data|Add3~5_sumout ),.cout(\A_SPW_TOP|tx_data|Add3~6 ),.shareout(\A_SPW_TOP|tx_data|Add3~7 ));// synopsys translate_offdefparam \A_SPW_TOP|tx_data|Add3~5 .extended_lut = "off";defparam \A_SPW_TOP|tx_data|Add3~5 .lut_mask = 64'h000050500000A5A5;defparam \A_SPW_TOP|tx_data|Add3~5 .shared_arith = "on";// synopsys translate_on// Location: LABCELL_X36_Y10_N6cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add3~9 (// Equation(s):// \A_SPW_TOP|tx_data|Add3~9_sumout = SUM(( !\A_SPW_TOP|tx_data|counter_writer [2] $ (\A_SPW_TOP|tx_data|counter_reader [2]) ) + ( \A_SPW_TOP|tx_data|Add3~7 ) + ( \A_SPW_TOP|tx_data|Add3~6 ))// \A_SPW_TOP|tx_data|Add3~10 = CARRY(( !\A_SPW_TOP|tx_data|counter_writer [2] $ (\A_SPW_TOP|tx_data|counter_reader [2]) ) + ( \A_SPW_TOP|tx_data|Add3~7 ) + ( \A_SPW_TOP|tx_data|Add3~6 ))// \A_SPW_TOP|tx_data|Add3~11 = SHARE((\A_SPW_TOP|tx_data|counter_writer [2] & !\A_SPW_TOP|tx_data|counter_reader [2])).dataa(gnd),.datab(!\A_SPW_TOP|tx_data|counter_writer [2]),.datac(!\A_SPW_TOP|tx_data|counter_reader [2]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\A_SPW_TOP|tx_data|Add3~6 ),.sharein(\A_SPW_TOP|tx_data|Add3~7 ),.combout(),.sumout(\A_SPW_TOP|tx_data|Add3~9_sumout ),.cout(\A_SPW_TOP|tx_data|Add3~10 ),.shareout(\A_SPW_TOP|tx_data|Add3~11 ));// synopsys translate_offdefparam \A_SPW_TOP|tx_data|Add3~9 .extended_lut = "off";defparam \A_SPW_TOP|tx_data|Add3~9 .lut_mask = 64'h000030300000C3C3;defparam \A_SPW_TOP|tx_data|Add3~9 .shared_arith = "on";// synopsys translate_on// Location: FF_X36_Y10_N8dffeas \A_SPW_TOP|tx_data|counter[2] (.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),.d(\A_SPW_TOP|tx_data|Add3~9_sumout ),.asdata(vcc),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|tx_data|counter [2]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|tx_data|counter[2] .is_wysiwyg = "true";defparam \A_SPW_TOP|tx_data|counter[2] .power_up = "low";// synopsys translate_on// Location: FF_X36_Y10_N2dffeas \A_SPW_TOP|tx_data|counter[0] (.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),.d(\A_SPW_TOP|tx_data|Add3~1_sumout ),.asdata(vcc),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|tx_data|counter [0]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|tx_data|counter[0] .is_wysiwyg = "true";defparam \A_SPW_TOP|tx_data|counter[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X36_Y10_N9cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add3~13 (// Equation(s):// \A_SPW_TOP|tx_data|Add3~13_sumout = SUM(( !\A_SPW_TOP|tx_data|counter_reader [3] $ (\A_SPW_TOP|tx_data|counter_writer [3]) ) + ( \A_SPW_TOP|tx_data|Add3~11 ) + ( \A_SPW_TOP|tx_data|Add3~10 ))// \A_SPW_TOP|tx_data|Add3~14 = CARRY(( !\A_SPW_TOP|tx_data|counter_reader [3] $ (\A_SPW_TOP|tx_data|counter_writer [3]) ) + ( \A_SPW_TOP|tx_data|Add3~11 ) + ( \A_SPW_TOP|tx_data|Add3~10 ))// \A_SPW_TOP|tx_data|Add3~15 = SHARE((!\A_SPW_TOP|tx_data|counter_reader [3] & \A_SPW_TOP|tx_data|counter_writer [3])).dataa(!\A_SPW_TOP|tx_data|counter_reader [3]),.datab(gnd),.datac(gnd),.datad(!\A_SPW_TOP|tx_data|counter_writer [3]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\A_SPW_TOP|tx_data|Add3~10 ),.sharein(\A_SPW_TOP|tx_data|Add3~11 ),.combout(),.sumout(\A_SPW_TOP|tx_data|Add3~13_sumout ),.cout(\A_SPW_TOP|tx_data|Add3~14 ),.shareout(\A_SPW_TOP|tx_data|Add3~15 ));// synopsys translate_offdefparam \A_SPW_TOP|tx_data|Add3~13 .extended_lut = "off";defparam \A_SPW_TOP|tx_data|Add3~13 .lut_mask = 64'h000000AA0000AA55;defparam \A_SPW_TOP|tx_data|Add3~13 .shared_arith = "on";// synopsys translate_on// Location: FF_X36_Y10_N11dffeas \A_SPW_TOP|tx_data|counter[3] (.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),.d(\A_SPW_TOP|tx_data|Add3~13_sumout ),.asdata(vcc),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|tx_data|counter [3]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|tx_data|counter[3] .is_wysiwyg = "true";defparam \A_SPW_TOP|tx_data|counter[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X36_Y10_N30cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add1~4 (// Equation(s):// \A_SPW_TOP|tx_data|Add1~4_combout = ( \A_SPW_TOP|tx_data|counter_writer [5] & ( \A_SPW_TOP|tx_data|counter_writer [1] & ( (!\A_SPW_TOP|tx_data|counter_writer [4]) # ((!\A_SPW_TOP|tx_data|counter_writer [0]) # ((!\A_SPW_TOP|tx_data|counter_writer [3]) #// (!\A_SPW_TOP|tx_data|counter_writer [2]))) ) ) ) # ( !\A_SPW_TOP|tx_data|counter_writer [5] & ( \A_SPW_TOP|tx_data|counter_writer [1] & ( (\A_SPW_TOP|tx_data|counter_writer [4] & (\A_SPW_TOP|tx_data|counter_writer [0] & (\A_SPW_TOP|tx_data|counter_writer// [3] & \A_SPW_TOP|tx_data|counter_writer [2]))) ) ) ) # ( \A_SPW_TOP|tx_data|counter_writer [5] & ( !\A_SPW_TOP|tx_data|counter_writer [1] ) ).dataa(!\A_SPW_TOP|tx_data|counter_writer [4]),.datab(!\A_SPW_TOP|tx_data|counter_writer [0]),.datac(!\A_SPW_TOP|tx_data|counter_writer [3]),.datad(!\A_SPW_TOP|tx_data|counter_writer [2]),.datae(!\A_SPW_TOP|tx_data|counter_writer [5]),.dataf(!\A_SPW_TOP|tx_data|counter_writer [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|tx_data|Add1~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|tx_data|Add1~4 .extended_lut = "off";defparam \A_SPW_TOP|tx_data|Add1~4 .lut_mask = 64'h0000FFFF0001FFFE;defparam \A_SPW_TOP|tx_data|Add1~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X37_Y10_N5dffeas \A_SPW_TOP|tx_data|counter_writer[5] (.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),.d(gnd),.asdata(\A_SPW_TOP|tx_data|Add1~4_combout ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\A_SPW_TOP|tx_data|state_data_write.10~q ),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|tx_data|counter_writer [5]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|tx_data|counter_writer[5] .is_wysiwyg = "true";defparam \A_SPW_TOP|tx_data|counter_writer[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X36_Y10_N54cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add2~4 (// Equation(s):// \A_SPW_TOP|tx_data|Add2~4_combout = ( \A_SPW_TOP|tx_data|counter_reader [4] & ( \A_SPW_TOP|tx_data|counter_reader [1] & ( !\A_SPW_TOP|tx_data|counter_reader [5] $ (((!\A_SPW_TOP|tx_data|counter_reader [2]) # ((!\A_SPW_TOP|tx_data|counter_reader [0]) #// (!\A_SPW_TOP|tx_data|counter_reader [3])))) ) ) ) # ( !\A_SPW_TOP|tx_data|counter_reader [4] & ( \A_SPW_TOP|tx_data|counter_reader [1] & ( \A_SPW_TOP|tx_data|counter_reader [5] ) ) ) # ( \A_SPW_TOP|tx_data|counter_reader [4] & (// !\A_SPW_TOP|tx_data|counter_reader [1] & ( \A_SPW_TOP|tx_data|counter_reader [5] ) ) ) # ( !\A_SPW_TOP|tx_data|counter_reader [4] & ( !\A_SPW_TOP|tx_data|counter_reader [1] & ( \A_SPW_TOP|tx_data|counter_reader [5] ) ) ).dataa(!\A_SPW_TOP|tx_data|counter_reader [2]),.datab(!\A_SPW_TOP|tx_data|counter_reader [0]),.datac(!\A_SPW_TOP|tx_data|counter_reader [3]),.datad(!\A_SPW_TOP|tx_data|counter_reader [5]),.datae(!\A_SPW_TOP|tx_data|counter_reader [4]),.dataf(!\A_SPW_TOP|tx_data|counter_reader [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|tx_data|Add2~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|tx_data|Add2~4 .extended_lut = "off";defparam \A_SPW_TOP|tx_data|Add2~4 .lut_mask = 64'h00FF00FF00FF01FE;defparam \A_SPW_TOP|tx_data|Add2~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X36_Y10_N59dffeas \A_SPW_TOP|tx_data|counter_reader[5] (.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),.d(gnd),.asdata(\A_SPW_TOP|tx_data|Add2~4_combout ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\A_SPW_TOP|tx_data|always3~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|tx_data|counter_reader [5]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|tx_data|counter_reader[5] .is_wysiwyg = "true";defparam \A_SPW_TOP|tx_data|counter_reader[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X36_Y10_N12cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add3~17 (// Equation(s):// \A_SPW_TOP|tx_data|Add3~17_sumout = SUM(( !\A_SPW_TOP|tx_data|counter_writer [4] $ (\A_SPW_TOP|tx_data|counter_reader [4]) ) + ( \A_SPW_TOP|tx_data|Add3~15 ) + ( \A_SPW_TOP|tx_data|Add3~14 ))// \A_SPW_TOP|tx_data|Add3~18 = CARRY(( !\A_SPW_TOP|tx_data|counter_writer [4] $ (\A_SPW_TOP|tx_data|counter_reader [4]) ) + ( \A_SPW_TOP|tx_data|Add3~15 ) + ( \A_SPW_TOP|tx_data|Add3~14 ))// \A_SPW_TOP|tx_data|Add3~19 = SHARE((\A_SPW_TOP|tx_data|counter_writer [4] & !\A_SPW_TOP|tx_data|counter_reader [4])).dataa(gnd),.datab(gnd),.datac(!\A_SPW_TOP|tx_data|counter_writer [4]),.datad(!\A_SPW_TOP|tx_data|counter_reader [4]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\A_SPW_TOP|tx_data|Add3~14 ),.sharein(\A_SPW_TOP|tx_data|Add3~15 ),.combout(),.sumout(\A_SPW_TOP|tx_data|Add3~17_sumout ),.cout(\A_SPW_TOP|tx_data|Add3~18 ),.shareout(\A_SPW_TOP|tx_data|Add3~19 ));// synopsys translate_offdefparam \A_SPW_TOP|tx_data|Add3~17 .extended_lut = "off";defparam \A_SPW_TOP|tx_data|Add3~17 .lut_mask = 64'h00000F000000F00F;defparam \A_SPW_TOP|tx_data|Add3~17 .shared_arith = "on";// synopsys translate_on// Location: LABCELL_X36_Y10_N15cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add3~21 (// Equation(s):// \A_SPW_TOP|tx_data|Add3~21_sumout = SUM(( !\A_SPW_TOP|tx_data|counter_writer [5] $ (\A_SPW_TOP|tx_data|counter_reader [5]) ) + ( \A_SPW_TOP|tx_data|Add3~19 ) + ( \A_SPW_TOP|tx_data|Add3~18 )).dataa(!\A_SPW_TOP|tx_data|counter_writer [5]),.datab(gnd),.datac(!\A_SPW_TOP|tx_data|counter_reader [5]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\A_SPW_TOP|tx_data|Add3~18 ),.sharein(\A_SPW_TOP|tx_data|Add3~19 ),.combout(),.sumout(\A_SPW_TOP|tx_data|Add3~21_sumout ),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|tx_data|Add3~21 .extended_lut = "off";defparam \A_SPW_TOP|tx_data|Add3~21 .lut_mask = 64'h000000000000A5A5;defparam \A_SPW_TOP|tx_data|Add3~21 .shared_arith = "on";// synopsys translate_on// Location: FF_X36_Y10_N17dffeas \A_SPW_TOP|tx_data|counter[5] (.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),.d(\A_SPW_TOP|tx_data|Add3~21_sumout ),.asdata(vcc),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|tx_data|counter [5]),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|tx_data|counter[5] .is_wysiwyg = "true";defparam \A_SPW_TOP|tx_data|counter[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X36_Y10_N36cyclonev_lcell_comb \A_SPW_TOP|tx_data|LessThan0~0 (// Equation(s):// \A_SPW_TOP|tx_data|LessThan0~0_combout = ( !\A_SPW_TOP|tx_data|counter [1] & ( !\A_SPW_TOP|tx_data|counter [5] & ( (!\A_SPW_TOP|tx_data|counter [4] & (!\A_SPW_TOP|tx_data|counter [2] & (!\A_SPW_TOP|tx_data|counter [0] & !\A_SPW_TOP|tx_data|counter [3])))// ) ) ).dataa(!\A_SPW_TOP|tx_data|counter [4]),.datab(!\A_SPW_TOP|tx_data|counter [2]),.datac(!\A_SPW_TOP|tx_data|counter [0]),.datad(!\A_SPW_TOP|tx_data|counter [3]),.datae(!\A_SPW_TOP|tx_data|counter [1]),.dataf(!\A_SPW_TOP|tx_data|counter [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|tx_data|LessThan0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|tx_data|LessThan0~0 .extended_lut = "off";defparam \A_SPW_TOP|tx_data|LessThan0~0 .lut_mask = 64'h8000000000000000;defparam \A_SPW_TOP|tx_data|LessThan0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X36_Y10_N23dffeas \A_SPW_TOP|tx_data|f_empty (.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),.d(gnd),.asdata(\A_SPW_TOP|tx_data|LessThan0~0_combout ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|tx_data|f_empty~q ),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|tx_data|f_empty .is_wysiwyg = "true";defparam \A_SPW_TOP|tx_data|f_empty .power_up = "low";// synopsys translate_on// Location: LABCELL_X51_Y6_N57cyclonev_lcell_comb \A_SPW_TOP|tx_data|state_data_read~10 (// Equation(s):// \A_SPW_TOP|tx_data|state_data_read~10_combout = ( \A_SPW_TOP|tx_data|state_data_read.00~0_combout & ( \A_SPW_TOP|tx_data|state_data_read.00~q & ( (\A_SPW_TOP|tx_data|state_data_read.01~q & ((!\A_SPW_TOP|SPW|TX|ready_tx_data~q ) #// (\A_SPW_TOP|tx_data|f_empty~q ))) ) ) ) # ( \A_SPW_TOP|tx_data|state_data_read.00~0_combout & ( !\A_SPW_TOP|tx_data|state_data_read.00~q & ( (!\A_SPW_TOP|tx_data|LessThan0~0_combout ) # ((\A_SPW_TOP|tx_data|state_data_read.01~q &// ((!\A_SPW_TOP|SPW|TX|ready_tx_data~q ) # (\A_SPW_TOP|tx_data|f_empty~q )))) ) ) ).dataa(!\A_SPW_TOP|tx_data|f_empty~q ),.datab(!\A_SPW_TOP|tx_data|state_data_read.01~q ),.datac(!\A_SPW_TOP|tx_data|LessThan0~0_combout ),.datad(!\A_SPW_TOP|SPW|TX|ready_tx_data~q ),.datae(!\A_SPW_TOP|tx_data|state_data_read.00~0_combout ),.dataf(!\A_SPW_TOP|tx_data|state_data_read.00~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|tx_data|state_data_read~10_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|tx_data|state_data_read~10 .extended_lut = "off";defparam \A_SPW_TOP|tx_data|state_data_read~10 .lut_mask = 64'h0000F3F100003311;defparam \A_SPW_TOP|tx_data|state_data_read~10 .shared_arith = "off";// synopsys translate_on// Location: FF_X51_Y6_N11dffeas \A_SPW_TOP|tx_data|state_data_read.01 (.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),.d(gnd),.asdata(\A_SPW_TOP|tx_data|state_data_read~10_combout ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|tx_data|state_data_read.01~q ),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|tx_data|state_data_read.01 .is_wysiwyg = "true";defparam \A_SPW_TOP|tx_data|state_data_read.01 .power_up = "low";// synopsys translate_on// Location: LABCELL_X51_Y6_N45cyclonev_lcell_comb \A_SPW_TOP|tx_data|state_data_read.00~0 (// Equation(s):// \A_SPW_TOP|tx_data|state_data_read.00~0_combout = ( \A_SPW_TOP|tx_data|state_data_read.01~q & ( (\A_SPW_TOP|tx_data|state_data_read.00~q & (!\A_SPW_TOP|tx_data|state_data_read.10~q & !\A_SPW_TOP|tx_data|state_data_read.11~q )) ) ) # (// !\A_SPW_TOP|tx_data|state_data_read.01~q & ( (!\A_SPW_TOP|tx_data|state_data_read.00~q & (!\A_SPW_TOP|tx_data|state_data_read.10~q & !\A_SPW_TOP|tx_data|state_data_read.11~q )) # (\A_SPW_TOP|tx_data|state_data_read.00~q &// (!\A_SPW_TOP|tx_data|state_data_read.10~q $ (!\A_SPW_TOP|tx_data|state_data_read.11~q ))) ) ).dataa(!\A_SPW_TOP|tx_data|state_data_read.00~q ),.datab(gnd),.datac(!\A_SPW_TOP|tx_data|state_data_read.10~q ),.datad(!\A_SPW_TOP|tx_data|state_data_read.11~q ),.datae(gnd),.dataf(!\A_SPW_TOP|tx_data|state_data_read.01~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|tx_data|state_data_read.00~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|tx_data|state_data_read.00~0 .extended_lut = "off";defparam \A_SPW_TOP|tx_data|state_data_read.00~0 .lut_mask = 64'hA550A55050005000;defparam \A_SPW_TOP|tx_data|state_data_read.00~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X51_Y6_N42cyclonev_lcell_comb \A_SPW_TOP|tx_data|state_data_read~11 (// Equation(s):// \A_SPW_TOP|tx_data|state_data_read~11_combout = ( \A_SPW_TOP|tx_data|LessThan0~0_combout & ( (\A_SPW_TOP|tx_data|state_data_read.00~q & (!\A_SPW_TOP|tx_data|state_data_read.11~q & \A_SPW_TOP|tx_data|state_data_read.00~0_combout )) ) ) # (// !\A_SPW_TOP|tx_data|LessThan0~0_combout & ( (!\A_SPW_TOP|tx_data|state_data_read.11~q & \A_SPW_TOP|tx_data|state_data_read.00~0_combout ) ) ).dataa(!\A_SPW_TOP|tx_data|state_data_read.00~q ),.datab(gnd),.datac(!\A_SPW_TOP|tx_data|state_data_read.11~q ),.datad(!\A_SPW_TOP|tx_data|state_data_read.00~0_combout ),.datae(gnd),.dataf(!\A_SPW_TOP|tx_data|LessThan0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|tx_data|state_data_read~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|tx_data|state_data_read~11 .extended_lut = "off";defparam \A_SPW_TOP|tx_data|state_data_read~11 .lut_mask = 64'h00F000F000500050;defparam \A_SPW_TOP|tx_data|state_data_read~11 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X51_Y6_N48cyclonev_lcell_comb \A_SPW_TOP|tx_data|state_data_read.00~feeder (// Equation(s):// \A_SPW_TOP|tx_data|state_data_read.00~feeder_combout = ( \A_SPW_TOP|tx_data|state_data_read~11_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\A_SPW_TOP|tx_data|state_data_read~11_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|tx_data|state_data_read.00~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|tx_data|state_data_read.00~feeder .extended_lut = "off";defparam \A_SPW_TOP|tx_data|state_data_read.00~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \A_SPW_TOP|tx_data|state_data_read.00~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X51_Y6_N50dffeas \A_SPW_TOP|tx_data|state_data_read.00 (.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),.d(\A_SPW_TOP|tx_data|state_data_read.00~feeder_combout ),.asdata(vcc),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|tx_data|state_data_read.00~q ),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|tx_data|state_data_read.00 .is_wysiwyg = "true";defparam \A_SPW_TOP|tx_data|state_data_read.00 .power_up = "low";// synopsys translate_on// Location: FF_X51_Y6_N5dffeas \A_SPW_TOP|tx_data|write_tx (.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),.d(gnd),.asdata(\A_SPW_TOP|tx_data|state_data_read.00~q ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\A_SPW_TOP|tx_data|write_tx~q ),.prn(vcc));// synopsys translate_offdefparam \A_SPW_TOP|tx_data|write_tx .is_wysiwyg = "true";defparam \A_SPW_TOP|tx_data|write_tx .power_up = "low";// synopsys translate_on// Location: LABCELL_X58_Y6_N12cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|LessThan3~0 (// Equation(s):// \A_SPW_TOP|SPW|TX|LessThan3~0_combout = ( \A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & !\A_SPW_TOP|SPW|TX|global_counter_transfer [3]) ) ) # ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & (// (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]) # (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]))) ) ).dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),.datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),.datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),.datad(gnd),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|TX|LessThan3~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|TX|LessThan3~0 .extended_lut = "off";defparam \A_SPW_TOP|SPW|TX|LessThan3~0 .lut_mask = 64'hC8C8C8C888888888;defparam \A_SPW_TOP|SPW|TX|LessThan3~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X54_Y5_N46dffeas \m_x|control_bit_found (.clk(!\m_x|always3~0_combout ),.d(gnd),.asdata(\A_SPW_TOP|SPW|TX|tx_dout_e~q ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\m_x|control_bit_found~q ),.prn(vcc));// synopsys translate_offdefparam \m_x|control_bit_found .is_wysiwyg = "true";defparam \m_x|control_bit_found .power_up = "low";// synopsys translate_on// Location: LABCELL_X53_Y5_N24cyclonev_lcell_comb \m_x|counter_neg[0]~feeder (// Equation(s):// \m_x|counter_neg[0]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|counter_neg[0]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|counter_neg[0]~feeder .extended_lut = "off";defparam \m_x|counter_neg[0]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \m_x|counter_neg[0]~feeder .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X54_Y5_N54cyclonev_lcell_comb \m_x|Selector2~0 (// Equation(s):// \m_x|Selector2~0_combout = (!\m_x|counter_neg [2] & (!\m_x|counter_neg [5] & (\m_x|counter_neg [0] & !\m_x|counter_neg [1]))).dataa(!\m_x|counter_neg [2]),.datab(!\m_x|counter_neg [5]),.datac(!\m_x|counter_neg [0]),.datad(!\m_x|counter_neg [1]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|Selector2~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|Selector2~0 .extended_lut = "off";defparam \m_x|Selector2~0 .lut_mask = 64'h0800080008000800;defparam \m_x|Selector2~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X54_Y5_N12cyclonev_lcell_comb \m_x|Selector2~1 (// Equation(s):// \m_x|Selector2~1_combout = (!\m_x|Selector2~0_combout & (\m_x|counter_neg [4])) # (\m_x|Selector2~0_combout & ((\m_x|counter_neg [3]))).dataa(!\m_x|counter_neg [4]),.datab(!\m_x|counter_neg [3]),.datac(gnd),.datad(!\m_x|Selector2~0_combout ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|Selector2~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|Selector2~1 .extended_lut = "off";defparam \m_x|Selector2~1 .lut_mask = 64'h5533553355335533;defparam \m_x|Selector2~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X54_Y5_N53dffeas \m_x|counter_neg[4] (.clk(!\m_x|always3~0_combout ),.d(gnd),.asdata(\m_x|Selector2~1_combout ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\m_x|counter_neg [4]),.prn(vcc));// synopsys translate_offdefparam \m_x|counter_neg[4] .is_wysiwyg = "true";defparam \m_x|counter_neg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X53_Y5_N33cyclonev_lcell_comb \m_x|WideOr7~0 (// Equation(s):// \m_x|WideOr7~0_combout = ( !\m_x|counter_neg [2] & ( \m_x|counter_neg [5] & ( (\m_x|counter_neg [0] & (!\m_x|counter_neg [3] & (!\m_x|counter_neg [1] & !\m_x|counter_neg [4]))) ) ) ) # ( \m_x|counter_neg [2] & ( !\m_x|counter_neg [5] & (// (\m_x|counter_neg [0] & (!\m_x|counter_neg [3] & (!\m_x|counter_neg [1] & !\m_x|counter_neg [4]))) ) ) ) # ( !\m_x|counter_neg [2] & ( !\m_x|counter_neg [5] & ( (!\m_x|counter_neg [0] & (!\m_x|counter_neg [3] & (!\m_x|counter_neg [1] & !\m_x|counter_neg// [4]))) # (\m_x|counter_neg [0] & ((!\m_x|counter_neg [3] & (!\m_x|counter_neg [1] $ (!\m_x|counter_neg [4]))) # (\m_x|counter_neg [3] & (!\m_x|counter_neg [1] & !\m_x|counter_neg [4])))) ) ) ).dataa(!\m_x|counter_neg [0]),.datab(!\m_x|counter_neg [3]),.datac(!\m_x|counter_neg [1]),.datad(!\m_x|counter_neg [4]),.datae(!\m_x|counter_neg [2]),.dataf(!\m_x|counter_neg [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|WideOr7~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|WideOr7~0 .extended_lut = "off";defparam \m_x|WideOr7~0 .lut_mask = 64'h9440400040000000;defparam \m_x|WideOr7~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X53_Y5_N26dffeas \m_x|counter_neg[0] (.clk(!\m_x|always3~0_combout ),.d(\m_x|counter_neg[0]~feeder_combout ),.asdata(vcc),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\m_x|WideOr7~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\m_x|counter_neg [0]),.prn(vcc));// synopsys translate_offdefparam \m_x|counter_neg[0] .is_wysiwyg = "true";defparam \m_x|counter_neg[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X54_Y5_N21cyclonev_lcell_comb \m_x|Selector3~0 (// Equation(s):// \m_x|Selector3~0_combout = ( !\m_x|counter_neg [1] & ( (!\m_x|is_control~q & \m_x|counter_neg [2]) ) ).dataa(!\m_x|is_control~q ),.datab(gnd),.datac(gnd),.datad(!\m_x|counter_neg [2]),.datae(gnd),.dataf(!\m_x|counter_neg [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|Selector3~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|Selector3~0 .extended_lut = "off";defparam \m_x|Selector3~0 .lut_mask = 64'h00AA00AA00000000;defparam \m_x|Selector3~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X54_Y5_N0cyclonev_lcell_comb \m_x|Selector3~1 (// Equation(s):// \m_x|Selector3~1_combout = ( \m_x|Selector2~0_combout & ( \m_x|counter_neg [3] & ( ((\m_x|counter_neg [0] & (!\m_x|counter_neg [5] & \m_x|Selector3~0_combout ))) # (\m_x|counter_neg [4]) ) ) ) # ( !\m_x|Selector2~0_combout & ( \m_x|counter_neg [3] ) )// # ( \m_x|Selector2~0_combout & ( !\m_x|counter_neg [3] & ( (\m_x|counter_neg [0] & (!\m_x|counter_neg [5] & (!\m_x|counter_neg [4] & \m_x|Selector3~0_combout ))) ) ) ) # ( !\m_x|Selector2~0_combout & ( !\m_x|counter_neg [3] & ( (\m_x|counter_neg [0] &// (!\m_x|counter_neg [5] & (!\m_x|counter_neg [4] & \m_x|Selector3~0_combout ))) ) ) ).dataa(!\m_x|counter_neg [0]),.datab(!\m_x|counter_neg [5]),.datac(!\m_x|counter_neg [4]),.datad(!\m_x|Selector3~0_combout ),.datae(!\m_x|Selector2~0_combout ),.dataf(!\m_x|counter_neg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|Selector3~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|Selector3~1 .extended_lut = "off";defparam \m_x|Selector3~1 .lut_mask = 64'h00400040FFFF0F4F;defparam \m_x|Selector3~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X54_Y5_N44dffeas \m_x|counter_neg[3] (.clk(!\m_x|always3~0_combout ),.d(gnd),.asdata(\m_x|Selector3~1_combout ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\m_x|counter_neg [3]),.prn(vcc));// synopsys translate_offdefparam \m_x|counter_neg[3] .is_wysiwyg = "true";defparam \m_x|counter_neg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X54_Y5_N36cyclonev_lcell_comb \m_x|Selector1~0 (// Equation(s):// \m_x|Selector1~0_combout = ( !\m_x|counter_neg [2] & ( \m_x|counter_neg [0] & ( (!\m_x|counter_neg [1] & !\m_x|counter_neg [3]) ) ) ).dataa(gnd),.datab(gnd),.datac(!\m_x|counter_neg [1]),.datad(!\m_x|counter_neg [3]),.datae(!\m_x|counter_neg [2]),.dataf(!\m_x|counter_neg [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|Selector1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|Selector1~0 .extended_lut = "off";defparam \m_x|Selector1~0 .lut_mask = 64'h00000000F0000000;defparam \m_x|Selector1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X53_Y5_N27cyclonev_lcell_comb \m_x|Selector1~1 (// Equation(s):// \m_x|Selector1~1_combout = ( \m_x|counter_neg [4] & ( (\m_x|counter_neg [5]) # (\m_x|Selector1~0_combout ) ) ) # ( !\m_x|counter_neg [4] & ( (!\m_x|Selector1~0_combout & \m_x|counter_neg [5]) ) ).dataa(gnd),.datab(!\m_x|Selector1~0_combout ),.datac(!\m_x|counter_neg [5]),.datad(gnd),.datae(gnd),.dataf(!\m_x|counter_neg [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|Selector1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|Selector1~1 .extended_lut = "off";defparam \m_x|Selector1~1 .lut_mask = 64'h0C0C0C0C3F3F3F3F;defparam \m_x|Selector1~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X53_Y5_N11dffeas \m_x|counter_neg[5] (.clk(!\m_x|always3~0_combout ),.d(gnd),.asdata(\m_x|Selector1~1_combout ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\m_x|counter_neg [5]),.prn(vcc));// synopsys translate_offdefparam \m_x|counter_neg[5] .is_wysiwyg = "true";defparam \m_x|counter_neg[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X54_Y5_N57cyclonev_lcell_comb \m_x|Selector5~0 (// Equation(s):// \m_x|Selector5~0_combout = ( \m_x|counter_neg [1] & ( (\m_x|counter_neg [2] & (!\m_x|counter_neg [5] & (\m_x|counter_neg [0] & \m_x|is_control~q ))) ) ) # ( !\m_x|counter_neg [1] & ( (!\m_x|counter_neg [2] & (!\m_x|counter_neg [5] $ ((\m_x|counter_neg// [0])))) # (\m_x|counter_neg [2] & (!\m_x|counter_neg [5] & (\m_x|counter_neg [0] & \m_x|is_control~q ))) ) ).dataa(!\m_x|counter_neg [2]),.datab(!\m_x|counter_neg [5]),.datac(!\m_x|counter_neg [0]),.datad(!\m_x|is_control~q ),.datae(gnd),.dataf(!\m_x|counter_neg [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|Selector5~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|Selector5~0 .extended_lut = "off";defparam \m_x|Selector5~0 .lut_mask = 64'h8286828600040004;defparam \m_x|Selector5~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X53_Y5_N57cyclonev_lcell_comb \m_x|Selector0~1 (// Equation(s):// \m_x|Selector0~1_combout = ( !\m_x|counter_neg [2] & ( (\m_x|counter_neg [0] & (!\m_x|counter_neg [3] & (!\m_x|counter_neg [5] & !\m_x|counter_neg [4]))) ) ).dataa(!\m_x|counter_neg [0]),.datab(!\m_x|counter_neg [3]),.datac(!\m_x|counter_neg [5]),.datad(!\m_x|counter_neg [4]),.datae(!\m_x|counter_neg [2]),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|Selector0~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|Selector0~1 .extended_lut = "off";defparam \m_x|Selector0~1 .lut_mask = 64'h4000000040000000;defparam \m_x|Selector0~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X54_Y5_N42cyclonev_lcell_comb \m_x|Selector5~1 (// Equation(s):// \m_x|Selector5~1_combout = ( \m_x|counter_neg [4] & ( (\m_x|counter_neg [1] & !\m_x|Selector0~1_combout ) ) ) # ( !\m_x|counter_neg [4] & ( (!\m_x|counter_neg [1] & (\m_x|Selector5~0_combout & ((!\m_x|counter_neg [3])))) # (\m_x|counter_neg [1] &// ((!\m_x|Selector0~1_combout ) # ((\m_x|Selector5~0_combout & !\m_x|counter_neg [3])))) ) ).dataa(!\m_x|counter_neg [1]),.datab(!\m_x|Selector5~0_combout ),.datac(!\m_x|Selector0~1_combout ),.datad(!\m_x|counter_neg [3]),.datae(gnd),.dataf(!\m_x|counter_neg [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|Selector5~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|Selector5~1 .extended_lut = "off";defparam \m_x|Selector5~1 .lut_mask = 64'h7350735050505050;defparam \m_x|Selector5~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X54_Y5_N56dffeas \m_x|counter_neg[1] (.clk(!\m_x|always3~0_combout ),.d(gnd),.asdata(\m_x|Selector5~1_combout ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\m_x|counter_neg [1]),.prn(vcc));// synopsys translate_offdefparam \m_x|counter_neg[1] .is_wysiwyg = "true";defparam \m_x|counter_neg[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X54_Y5_N15cyclonev_lcell_comb \m_x|Selector0~0 (// Equation(s):// \m_x|Selector0~0_combout = ( !\m_x|counter_neg [5] & ( (!\m_x|counter_neg [4] & (!\m_x|counter_neg [3] & \m_x|counter_neg [0])) ) ).dataa(!\m_x|counter_neg [4]),.datab(gnd),.datac(!\m_x|counter_neg [3]),.datad(!\m_x|counter_neg [0]),.datae(gnd),.dataf(!\m_x|counter_neg [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|Selector0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|Selector0~0 .extended_lut = "off";defparam \m_x|Selector0~0 .lut_mask = 64'h00A000A000000000;defparam \m_x|Selector0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X54_Y5_N45cyclonev_lcell_comb \m_x|Selector4~0 (// Equation(s):// \m_x|Selector4~0_combout = ( \m_x|Selector0~0_combout & ( \m_x|counter_neg [1] ) ) # ( !\m_x|Selector0~0_combout & ( \m_x|counter_neg [2] ) ).dataa(!\m_x|counter_neg [1]),.datab(gnd),.datac(!\m_x|counter_neg [2]),.datad(gnd),.datae(gnd),.dataf(!\m_x|Selector0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|Selector4~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|Selector4~0 .extended_lut = "off";defparam \m_x|Selector4~0 .lut_mask = 64'h0F0F0F0F55555555;defparam \m_x|Selector4~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X54_Y5_N23dffeas \m_x|counter_neg[2] (.clk(!\m_x|always3~0_combout ),.d(gnd),.asdata(\m_x|Selector4~0_combout ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\m_x|counter_neg [2]),.prn(vcc));// synopsys translate_offdefparam \m_x|counter_neg[2] .is_wysiwyg = "true";defparam \m_x|counter_neg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X54_Y5_N48cyclonev_lcell_comb \m_x|Selector0~2 (// Equation(s):// \m_x|Selector0~2_combout = ( \m_x|counter_neg [1] & ( !\m_x|counter_neg [3] & ( (!\m_x|counter_neg [2] & (\m_x|counter_neg [0] & (!\m_x|counter_neg [4] & !\m_x|counter_neg [5]))) ) ) ) # ( !\m_x|counter_neg [1] & ( !\m_x|counter_neg [3] & (// (\m_x|counter_neg [0] & (!\m_x|counter_neg [4] & (!\m_x|counter_neg [2] $ (!\m_x|counter_neg [5])))) ) ) ).dataa(!\m_x|counter_neg [2]),.datab(!\m_x|counter_neg [0]),.datac(!\m_x|counter_neg [4]),.datad(!\m_x|counter_neg [5]),.datae(!\m_x|counter_neg [1]),.dataf(!\m_x|counter_neg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|Selector0~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|Selector0~2 .extended_lut = "off";defparam \m_x|Selector0~2 .lut_mask = 64'h1020200000000000;defparam \m_x|Selector0~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X54_Y5_N27cyclonev_lcell_comb \m_x|Selector0~3 (// Equation(s):// \m_x|Selector0~3_combout = ( \m_x|Selector0~1_combout & ( (!\m_x|Selector0~2_combout & (\m_x|is_control~q )) # (\m_x|Selector0~2_combout & (((\m_x|control_bit_found~q & \m_x|counter_neg [1])))) ) ) # ( !\m_x|Selector0~1_combout & (// (\m_x|is_control~q & !\m_x|Selector0~2_combout ) ) ).dataa(!\m_x|is_control~q ),.datab(!\m_x|control_bit_found~q ),.datac(!\m_x|Selector0~2_combout ),.datad(!\m_x|counter_neg [1]),.datae(gnd),.dataf(!\m_x|Selector0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|Selector0~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|Selector0~3 .extended_lut = "off";defparam \m_x|Selector0~3 .lut_mask = 64'h5050505050535053;defparam \m_x|Selector0~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X54_Y5_N29dffeas \m_x|is_control (.clk(!\m_x|always3~0_combout ),.d(\m_x|Selector0~3_combout ),.asdata(vcc),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\m_x|is_control~q ),.prn(vcc));// synopsys translate_offdefparam \m_x|is_control .is_wysiwyg = "true";defparam \m_x|is_control .power_up = "low";// synopsys translate_on// Location: LABCELL_X54_Y5_N6cyclonev_lcell_comb \m_x|always1~0 (// Equation(s):// \m_x|always1~0_combout = LCELL(( !\m_x|always3~0_combout & ( (!\m_x|counter_neg [1] & (\m_x|Selector0~0_combout & \m_x|counter_neg [2])) ) )).dataa(!\m_x|counter_neg [1]),.datab(!\m_x|Selector0~0_combout ),.datac(gnd),.datad(!\m_x|counter_neg [2]),.datae(gnd),.dataf(!\m_x|always3~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|always1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|always1~0 .extended_lut = "off";defparam \m_x|always1~0 .lut_mask = 64'h0022002200000000;defparam \m_x|always1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X54_Y5_N9cyclonev_lcell_comb \m_x|always2~0 (// Equation(s):// \m_x|always2~0_combout = LCELL(( \m_x|always3~0_combout & ( (!\m_x|counter_neg [1] & (\m_x|Selector0~0_combout & \m_x|counter_neg [2])) ) )).dataa(!\m_x|counter_neg [1]),.datab(gnd),.datac(!\m_x|Selector0~0_combout ),.datad(!\m_x|counter_neg [2]),.datae(gnd),.dataf(!\m_x|always3~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|always2~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|always2~0 .extended_lut = "off";defparam \m_x|always2~0 .lut_mask = 64'h00000000000A000A;defparam \m_x|always2~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X54_Y5_N24cyclonev_lcell_comb \m_x|ready_control_p_r~0 (// Equation(s):// \m_x|ready_control_p_r~0_combout = ( \m_x|always2~0_combout & ( (\m_x|ready_control_p_r~q ) # (\m_x|is_control~q ) ) ) # ( !\m_x|always2~0_combout & ( (\m_x|always1~0_combout & ((\m_x|ready_control_p_r~q ) # (\m_x|is_control~q ))) ) ).dataa(!\m_x|is_control~q ),.datab(gnd),.datac(!\m_x|ready_control_p_r~q ),.datad(!\m_x|always1~0_combout ),.datae(gnd),.dataf(!\m_x|always2~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|ready_control_p_r~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|ready_control_p_r~0 .extended_lut = "off";defparam \m_x|ready_control_p_r~0 .lut_mask = 64'h005F005F5F5F5F5F;defparam \m_x|ready_control_p_r~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X54_Y5_N38dffeas \m_x|ready_control_p_r (.clk(!\m_x|always3~0_combout ),.d(gnd),.asdata(\m_x|ready_control_p_r~0_combout ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\m_x|ready_control_p_r~q ),.prn(vcc));// synopsys translate_offdefparam \m_x|ready_control_p_r .is_wysiwyg = "true";defparam \m_x|ready_control_p_r .power_up = "low";// synopsys translate_on// Location: LABCELL_X51_Y5_N15cyclonev_lcell_comb \m_x|bit_c_1~feeder (// Equation(s):// \m_x|bit_c_1~feeder_combout = ( \A_SPW_TOP|SPW|TX|tx_dout_e~q ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|TX|tx_dout_e~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|bit_c_1~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|bit_c_1~feeder .extended_lut = "off";defparam \m_x|bit_c_1~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \m_x|bit_c_1~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X51_Y5_N17dffeas \m_x|bit_c_1 (.clk(\m_x|always3~0_combout ),.d(\m_x|bit_c_1~feeder_combout ),.asdata(vcc),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\m_x|bit_c_1~q ),.prn(vcc));// synopsys translate_offdefparam \m_x|bit_c_1 .is_wysiwyg = "true";defparam \m_x|bit_c_1 .power_up = "low";// synopsys translate_on// Location: FF_X55_Y5_N26dffeas \m_x|control_r[1] (.clk(\m_x|always1~0_combout ),.d(gnd),.asdata(\m_x|bit_c_1~q ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\m_x|control_r [1]),.prn(vcc));// synopsys translate_offdefparam \m_x|control_r[1] .is_wysiwyg = "true";defparam \m_x|control_r[1] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X55_Y5_N36cyclonev_lcell_comb \m_x|control_p_r[1]~feeder (// Equation(s):// \m_x|control_p_r[1]~feeder_combout = ( \m_x|control_r [1] ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\m_x|control_r [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|control_p_r[1]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|control_p_r[1]~feeder .extended_lut = "off";defparam \m_x|control_p_r[1]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \m_x|control_p_r[1]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X55_Y5_N37dffeas \m_x|control_p_r[1] (.clk(\m_x|always2~0_combout ),.d(\m_x|control_p_r[1]~feeder_combout ),.asdata(vcc),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\m_x|control_p_r [1]),.prn(vcc));// synopsys translate_offdefparam \m_x|control_p_r[1] .is_wysiwyg = "true";defparam \m_x|control_p_r[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X53_Y9_N45cyclonev_lcell_comb \m_x|control~1 (// Equation(s):// \m_x|control~1_combout = ( \m_x|control [1] & ( \m_x|control_p_r [1] ) ) # ( !\m_x|control [1] & ( \m_x|control_p_r [1] & ( \m_x|ready_control_p_r~q ) ) ) # ( \m_x|control [1] & ( !\m_x|control_p_r [1] & ( !\m_x|ready_control_p_r~q ) ) ).dataa(gnd),.datab(gnd),.datac(!\m_x|ready_control_p_r~q ),.datad(gnd),.datae(!\m_x|control [1]),.dataf(!\m_x|control_p_r [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|control~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|control~1 .extended_lut = "off";defparam \m_x|control~1 .lut_mask = 64'h0000F0F00F0FFFFF;defparam \m_x|control~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X53_Y5_N36cyclonev_lcell_comb \m_x|ready_data (// Equation(s):// \m_x|ready_data~combout = LCELL(( \m_x|Selector1~0_combout & ( !\m_x|always3~0_combout & ( (!\m_x|always1~0_combout & (!\m_x|counter_neg [4] & \m_x|counter_neg [5])) ) ) )).dataa(!\m_x|always1~0_combout ),.datab(gnd),.datac(!\m_x|counter_neg [4]),.datad(!\m_x|counter_neg [5]),.datae(!\m_x|Selector1~0_combout ),.dataf(!\m_x|always3~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|ready_data~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|ready_data .extended_lut = "off";defparam \m_x|ready_data .lut_mask = 64'h000000A000000000;defparam \m_x|ready_data .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X54_Y5_N33cyclonev_lcell_comb \m_x|ready_data_p (// Equation(s):// \m_x|ready_data_p~combout = LCELL(( \m_x|Selector1~0_combout & ( \m_x|always3~0_combout & ( (\m_x|counter_neg [5] & (!\m_x|always2~0_combout & !\m_x|counter_neg [4])) ) ) )).dataa(gnd),.datab(!\m_x|counter_neg [5]),.datac(!\m_x|always2~0_combout ),.datad(!\m_x|counter_neg [4]),.datae(!\m_x|Selector1~0_combout ),.dataf(!\m_x|always3~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|ready_data_p~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|ready_data_p .extended_lut = "off";defparam \m_x|ready_data_p .lut_mask = 64'h0000000000003000;defparam \m_x|ready_data_p .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X54_Y5_N18cyclonev_lcell_comb \m_x|ready_data_p_r~0 (// Equation(s):// \m_x|ready_data_p_r~0_combout = ( \m_x|ready_data_p~combout & ( (!\m_x|is_control~q ) # (\m_x|ready_data_p_r~q ) ) ) # ( !\m_x|ready_data_p~combout & ( (\m_x|ready_data~combout & ((!\m_x|is_control~q ) # (\m_x|ready_data_p_r~q ))) ) ).dataa(!\m_x|is_control~q ),.datab(gnd),.datac(!\m_x|ready_data_p_r~q ),.datad(!\m_x|ready_data~combout ),.datae(gnd),.dataf(!\m_x|ready_data_p~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|ready_data_p_r~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|ready_data_p_r~0 .extended_lut = "off";defparam \m_x|ready_data_p_r~0 .lut_mask = 64'h00AF00AFAFAFAFAF;defparam \m_x|ready_data_p_r~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X54_Y5_N35dffeas \m_x|ready_data_p_r (.clk(!\m_x|always3~0_combout ),.d(gnd),.asdata(\m_x|ready_data_p_r~0_combout ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\m_x|ready_data_p_r~q ),.prn(vcc));// synopsys translate_offdefparam \m_x|ready_data_p_r .is_wysiwyg = "true";defparam \m_x|ready_data_p_r .power_up = "low";// synopsys translate_on// Location: LABCELL_X54_Y9_N3cyclonev_lcell_comb \m_x|next_state_data_process.01~0 (// Equation(s):// \m_x|next_state_data_process.01~0_combout = ( \m_x|ready_data_p_r~q & ( \m_x|ready_control_p_r~q & ( !\m_x|state_data_process.01~q ) ) ) # ( !\m_x|ready_data_p_r~q & ( \m_x|ready_control_p_r~q & ( !\m_x|state_data_process.01~q ) ) ) # (// \m_x|ready_data_p_r~q & ( !\m_x|ready_control_p_r~q & ( !\m_x|state_data_process.01~q ) ) ).dataa(!\m_x|state_data_process.01~q ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\m_x|ready_data_p_r~q ),.dataf(!\m_x|ready_control_p_r~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|next_state_data_process.01~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|next_state_data_process.01~0 .extended_lut = "off";defparam \m_x|next_state_data_process.01~0 .lut_mask = 64'h0000AAAAAAAAAAAA;defparam \m_x|next_state_data_process.01~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X54_Y9_N56dffeas \m_x|state_data_process.01 (.clk(!\m_x|always3~0_combout ),.d(gnd),.asdata(\m_x|next_state_data_process.01~0_combout ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\m_x|state_data_process.01~q ),.prn(vcc));// synopsys translate_offdefparam \m_x|state_data_process.01 .is_wysiwyg = "true";defparam \m_x|state_data_process.01 .power_up = "low";// synopsys translate_on// Location: FF_X53_Y9_N23dffeas \m_x|control[1] (.clk(!\m_x|always3~0_combout ),.d(gnd),.asdata(\m_x|control~1_combout ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(!\m_x|state_data_process.01~q ),.devclrn(devclrn),.devpor(devpor),.q(\m_x|control [1]),.prn(vcc));// synopsys translate_offdefparam \m_x|control[1] .is_wysiwyg = "true";defparam \m_x|control[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X53_Y9_N21cyclonev_lcell_comb \m_x|control_l_r~1 (// Equation(s):// \m_x|control_l_r~1_combout = ( \m_x|control [1] & ( \m_x|control_l_r [1] ) ) # ( !\m_x|control [1] & ( \m_x|control_l_r [1] & ( !\m_x|ready_control_p_r~q ) ) ) # ( \m_x|control [1] & ( !\m_x|control_l_r [1] & ( \m_x|ready_control_p_r~q ) ) ).dataa(gnd),.datab(gnd),.datac(!\m_x|ready_control_p_r~q ),.datad(gnd),.datae(!\m_x|control [1]),.dataf(!\m_x|control_l_r [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|control_l_r~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|control_l_r~1 .extended_lut = "off";defparam \m_x|control_l_r~1 .lut_mask = 64'h00000F0FF0F0FFFF;defparam \m_x|control_l_r~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X53_Y9_N20dffeas \m_x|control_l_r[1] (.clk(!\m_x|always3~0_combout ),.d(gnd),.asdata(\m_x|control_l_r~1_combout ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(!\m_x|state_data_process.01~q ),.devclrn(devclrn),.devpor(devpor),.q(\m_x|control_l_r [1]),.prn(vcc));// synopsys translate_offdefparam \m_x|control_l_r[1] .is_wysiwyg = "true";defparam \m_x|control_l_r[1] .power_up = "low";// synopsys translate_on// Location: FF_X53_Y9_N11dffeas \m_x|info[11] (.clk(!\m_x|always3~0_combout ),.d(gnd),.asdata(\m_x|control_l_r [1]),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\m_x|state_data_process.01~q ),.devclrn(devclrn),.devpor(devpor),.q(\m_x|info [11]),.prn(vcc));// synopsys translate_offdefparam \m_x|info[11] .is_wysiwyg = "true";defparam \m_x|info[11] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y37_N21cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~13 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_017|src_payload~13_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout & ( \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~13_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~13 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~13 .lut_mask = 64'h0F0F0F0F00000000;defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~13 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y33_N39cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y33_N41dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y33_N45cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout = !\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1].dataa(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hAAAAAAAAAAAAAAAA;defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y33_N47dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y33_N36cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y33_N38dffeas \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y33_N45cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout ) ) # (// !\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout & ( (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout & \u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout ),.datab(!\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h1111111155555555;defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y32_N5dffeas \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y37_N42cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y37_N44dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y33_N48cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = ( \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout & (// (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout & (// (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & \u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout )) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datad(!\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h000A000A0A0A0A0A;defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y33_N51cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2] & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) )// # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))// ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h33CF33CF30CC30CC;defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y33_N53dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y33_N15cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout = (// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))// # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) #// ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))// # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h54BA54BA10FE10FE;defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y33_N17dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";// synopsys translate_on// Location: FF_X21_Y33_N26dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y33_N24cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout = (// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) #// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]// & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]// & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h0000FFFFE2222EEE;defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y33_N14dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y33_N48cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))// ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h3000300000000000;defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y33_N12cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout// & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [5])))) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])))) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))// # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .lut_mask = 64'h10FE10FEDC32DC32;defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y33_N19dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y33_N18cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout = (// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))))// # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )))) ) ) ) # (// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [5])))) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ))) ) ) ) # (// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # (// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .lut_mask = 64'h0202FEFECE0232FE;defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y33_N6cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout = (// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout & (// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout & (// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout &// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout &// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout )) ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .lut_mask = 64'hC000000000000000;defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y33_N15cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (// ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) ) # (// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & ( (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout &// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h004400440F4F0F4F;defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y33_N17dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y33_N18cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout = ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'hFFFF000000000000;defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y33_N12cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & (// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout )) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h0101010100000000;defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y33_N27cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) ) ) ) # (// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (// ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout )) #// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0F0F0FCF000000CC;defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y33_N29dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";// synopsys translate_on// Location: FF_X21_Y33_N35dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y33_N33cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~6 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][75]~q ) ) # (// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][75]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h0303030300FF00FF;defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y33_N12cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0]) #// (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0] ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hAAAAAAAAFAFAFAFA;defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y32_N41dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~6_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";// synopsys translate_on// Location: FF_X21_Y33_N47dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y33_N45cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~3 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #// (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # (// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][78]~q ) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][78]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h005500550A5F0A5F;defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y32_N53dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~3_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";// synopsys translate_on// Location: FF_X21_Y33_N32dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y33_N30cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~5 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][76]~q ) ) # (// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][76]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h0303030300FF00FF;defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y32_N44dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~5_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";// synopsys translate_on// Location: FF_X21_Y33_N59dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y33_N57cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~4 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~4_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][77]~q & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] ) ) # (// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][77]~q & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & (// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])// ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][77]~q & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & (// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])// ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datad(gnd),.datae(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][77]~q ),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h030303030000FFFF;defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y32_N47dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~4_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";// synopsys translate_on// Location: FF_X21_Y33_N38dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~7_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y33_N36cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~7 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][74]~q & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] ) ) # (// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][74]~q & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & (// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [2])) ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][74]~q & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & (// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [2])) ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datae(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][74]~q ),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h03CF03CF0000FFFF;defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y32_N11dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~7_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y32_N48cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~0 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~0_combout = ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77]~q & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q & (// (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy~q & (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q & (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78]~q &// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76]~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy~q ),.datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q ),.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78]~q ),.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76]~q ),.datae(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77]~q ),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0000000080000000;defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y32_N39cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0_combout = ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76]~q &// (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77]~q & !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q )) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76]~q ),.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77]~q ),.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hC000C00000000000;defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y32_N54cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q $// (((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q ))))) # (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (((\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q $// (((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q ))))) # (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (((!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q ),.datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q ),.datae(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h00000000D8728D27;defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y32_N56dffeas \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y32_N42cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77]~q ) ) # (// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77]~q $ (((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q &// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76]~q ))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77]~q ),.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q ),.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h3CCC3CCCCCCCCCCC;defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y32_N51cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~0 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]// & !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (// (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) # (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datad(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h0FFF0FFFF000F000;defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y32_N24cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q & ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout & (// (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76]~q ))) #// (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~0_combout )) ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q & (// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76]~q $// (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q )))) # (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~0_combout ),.datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76]~q ),.datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q ),.datae(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q ),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h00000000CA3A3A3A;defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y32_N26dffeas \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y32_N33cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~2 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5]// ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $// (((!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]))) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datab(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h78787878F0F0F0F0;defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~2 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y32_N30cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout & (// (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~1_combout )) #// (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~2_combout ))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~1_combout ),.datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~2_combout ),.datad(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h00000000CCF0CCF0;defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y32_N32dffeas \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y32_N30cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter// [3] & (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datad(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hC000C00000000000;defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y32_N12cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78]~q $// ((!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0_combout )))) # (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (((!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1_combout ))))// ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout & (// (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78]~q $ ((!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0_combout )))) #// (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (((\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1_combout )))) ) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78]~q ),.datab(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0_combout ),.datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datad(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1_combout ),.datae(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h00000000606F6F60;defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y32_N14dffeas \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y32_N0cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1_combout & ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout &// ( (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78]~q & \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0_combout )))) #// (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6])) ) ) ) # (// !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1_combout & ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout// & (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78]~q & \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datab(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78]~q ),.datad(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0_combout ),.datae(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1_combout ),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h0000000000A044E4;defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y32_N2dffeas \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y32_N33cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5] &// !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3])) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datad(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hA000A00000000000;defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y32_N36cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy~q ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy~q & ((!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1_combout ) # (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter// [7]))) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1_combout ),.datad(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00F500F500FF00FF;defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y32_N21cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout & (// (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2_combout & ((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q ) # (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )))// ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2_combout ),.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q ),.datad(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h00000000C0CCC0CC;defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y32_N23dffeas \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y32_N45cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2_combout = (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy~q & \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]).dataa(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h0505050505050505;defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y33_N23dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";// synopsys translate_on// Location: FF_X21_Y33_N2dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y33_N0cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~2 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~2_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][66]~q & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] ) ) # (// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][66]~q & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] ) ) )// # ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][66]~q & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] )// ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datad(gnd),.datae(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][66]~q ),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h0F0F0F0F0000FFFF;defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y32_N8dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~2_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y32_N18cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][66]~q & ( (!\u0|mm_interconnect_0|data_info_s1_agent|comb~0_combout ) #// ((!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~0_combout & ((!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2_combout ) #// (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1_combout )))) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~0_combout ),.datab(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2_combout ),.datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1_combout ),.datad(!\u0|mm_interconnect_0|data_info_s1_agent|comb~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][66]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00000000FFA8FFA8;defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y33_N33cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[0]~1 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout & ( (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0]) #// (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0_combout ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout & ( ((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0] &// ((!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ),.datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0_combout ),.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h33BF33BF33FF33FF;defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y33_N35dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: FF_X22_Y33_N13dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~1_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y33_N9cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~1 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout &// \u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout )) # (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][129]~q ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & (// (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout & \u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout ),.datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][129]~q ),.datac(!\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h0505050537373737;defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y33_N23dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~1_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y33_N15cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|comb~0 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0] ) ) # (// !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129]~q ) #// (\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0]))) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0]),.datab(!\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0]),.datac(gnd),.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent|comb~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent|comb~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent|comb~0 .lut_mask = 64'h1155115555555555;defparam \u0|mm_interconnect_0|data_info_s1_agent|comb~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y33_N21cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout = ( \u0|mm_interconnect_0|data_info_s1_agent|comb~0_combout & ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datad(gnd),.datae(!\u0|mm_interconnect_0|data_info_s1_agent|comb~0_combout ),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0 .lut_mask = 64'h00000F0F00000F0F;defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y33_N30cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[1]~0 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0_combout &// ((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0_combout & (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0])) ) ) # (// !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout & ((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0_combout &// ((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0_combout & (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0])))) #// (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout & (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0_combout & ((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1])))) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ),.datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0_combout ),.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[1]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h029B029B03CF03CF;defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y33_N32dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[1]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";// synopsys translate_on// Location: FF_X22_Y33_N56dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y33_N54cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] &// ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h000000000CCC0CCC;defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y33_N51cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter~0 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter~0_combout = ( \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~q & ( (!\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout &// (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout & !\u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter [0])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ),.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout ),.datad(!\u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter~0 .lut_mask = 64'h000000000C000C00;defparam \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y33_N53dffeas \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y33_N6cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout = ( \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter [0] & ( \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~q ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0 .lut_mask = 64'h000000000F0F0F0F;defparam \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y33_N20dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y33_N21cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & (// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & (// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #// ((!\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & !\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ))) )// ) ) # ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) ) ) ) # (// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & ( (!\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout &// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q &// !\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ))) ) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout ),.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.datad(!\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ),.datae(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h02000303CECCCFCF;defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y33_N9cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = ( \u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout & (// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout// & ( (\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]))// ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout ),.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h1010101030303030;defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y33_N45cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) # (// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .lut_mask = 64'hFF00FF00F000F000;defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y33_N33cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// ((\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & \u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout ))) #// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & \u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout )) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.datad(!\u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h001100110F1F0F1F;defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y33_N35dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y33_N21cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & (// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & (// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout )) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datab(!\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout ),.datac(!\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hBFBFBFBFAAAAAAAA;defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y33_N42cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (// (\u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout & (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout ),.datab(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),.datac(gnd),.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h0000000000110011;defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y33_N57cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & (// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) #// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ))) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & (// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & (((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q )) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ))) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h0545054505550555;defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y33_N59dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y33_N33cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) ) # (// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q &// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))// # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q $// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .lut_mask = 64'hC330C33030003000;defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y33_N54cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # (// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ( (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout &// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h0055005550505050;defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y33_N56dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";// synopsys translate_on// Location: FF_X23_Y33_N29dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";// synopsys translate_on// Location: FF_X23_Y33_N1dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";// synopsys translate_on// Location: FF_X23_Y33_N14dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y33_N0cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~1 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~1_combout = ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] &// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1])) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~1 .lut_mask = 64'hA000A00000000000;defparam \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X54_Y5_N5dffeas \m_x|bit_c_0 (.clk(!\m_x|always3~0_combout ),.d(gnd),.asdata(\A_SPW_TOP|SPW|TX|tx_dout_e~q ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\m_x|bit_c_0~q ),.prn(vcc));// synopsys translate_offdefparam \m_x|bit_c_0 .is_wysiwyg = "true";defparam \m_x|bit_c_0 .power_up = "low";// synopsys translate_on// Location: FF_X54_Y5_N31dffeas \m_x|bit_c_2 (.clk(!\m_x|always3~0_combout ),.d(gnd),.asdata(\m_x|bit_c_0~q ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\m_x|bit_c_2~q ),.prn(vcc));// synopsys translate_offdefparam \m_x|bit_c_2 .is_wysiwyg = "true";defparam \m_x|bit_c_2 .power_up = "low";// synopsys translate_on// Location: MLABCELL_X55_Y5_N0cyclonev_lcell_comb \m_x|control_r[2]~feeder (// Equation(s):// \m_x|control_r[2]~feeder_combout = ( \m_x|bit_c_2~q ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\m_x|bit_c_2~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|control_r[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|control_r[2]~feeder .extended_lut = "off";defparam \m_x|control_r[2]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \m_x|control_r[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X55_Y5_N2dffeas \m_x|control_r[2] (.clk(\m_x|always1~0_combout ),.d(\m_x|control_r[2]~feeder_combout ),.asdata(vcc),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\m_x|control_r [2]),.prn(vcc));// synopsys translate_offdefparam \m_x|control_r[2] .is_wysiwyg = "true";defparam \m_x|control_r[2] .power_up = "low";// synopsys translate_on// Location: FF_X55_Y5_N31dffeas \m_x|control_p_r[2] (.clk(\m_x|always2~0_combout ),.d(gnd),.asdata(\m_x|control_r [2]),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\m_x|control_p_r [2]),.prn(vcc));// synopsys translate_offdefparam \m_x|control_p_r[2] .is_wysiwyg = "true";defparam \m_x|control_p_r[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X53_Y9_N15cyclonev_lcell_comb \m_x|control~2 (// Equation(s):// \m_x|control~2_combout = (!\m_x|ready_control_p_r~q & ((\m_x|control [2]))) # (\m_x|ready_control_p_r~q & (\m_x|control_p_r [2])).dataa(!\m_x|control_p_r [2]),.datab(!\m_x|ready_control_p_r~q ),.datac(!\m_x|control [2]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|control~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|control~2 .extended_lut = "off";defparam \m_x|control~2 .lut_mask = 64'h1D1D1D1D1D1D1D1D;defparam \m_x|control~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X53_Y9_N29dffeas \m_x|control[2] (.clk(!\m_x|always3~0_combout ),.d(gnd),.asdata(\m_x|control~2_combout ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(!\m_x|state_data_process.01~q ),.devclrn(devclrn),.devpor(devpor),.q(\m_x|control [2]),.prn(vcc));// synopsys translate_offdefparam \m_x|control[2] .is_wysiwyg = "true";defparam \m_x|control[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X53_Y9_N27cyclonev_lcell_comb \m_x|control_l_r~2 (// Equation(s):// \m_x|control_l_r~2_combout = ( \m_x|control_l_r [2] & ( (!\m_x|ready_control_p_r~q ) # (\m_x|control [2]) ) ) # ( !\m_x|control_l_r [2] & ( (\m_x|ready_control_p_r~q & \m_x|control [2]) ) ).dataa(gnd),.datab(gnd),.datac(!\m_x|ready_control_p_r~q ),.datad(!\m_x|control [2]),.datae(gnd),.dataf(!\m_x|control_l_r [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|control_l_r~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|control_l_r~2 .extended_lut = "off";defparam \m_x|control_l_r~2 .lut_mask = 64'h000F000FF0FFF0FF;defparam \m_x|control_l_r~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X53_Y9_N26dffeas \m_x|control_l_r[2] (.clk(!\m_x|always3~0_combout ),.d(gnd),.asdata(\m_x|control_l_r~2_combout ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(!\m_x|state_data_process.01~q ),.devclrn(devclrn),.devpor(devpor),.q(\m_x|control_l_r [2]),.prn(vcc));// synopsys translate_offdefparam \m_x|control_l_r[2] .is_wysiwyg = "true";defparam \m_x|control_l_r[2] .power_up = "low";// synopsys translate_on// Location: FF_X53_Y9_N13dffeas \m_x|info[12] (.clk(!\m_x|always3~0_combout ),.d(gnd),.asdata(\m_x|control_l_r [2]),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\m_x|state_data_process.01~q ),.devclrn(devclrn),.devpor(devpor),.q(\m_x|info [12]),.prn(vcc));// synopsys translate_offdefparam \m_x|info[12] .is_wysiwyg = "true";defparam \m_x|info[12] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y16_N18cyclonev_lcell_comb \u0|data_info|read_mux_out[12] (// Equation(s):// \u0|data_info|read_mux_out [12] = ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & (// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & \m_x|info [12]) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),.datab(gnd),.datac(!\m_x|info [12]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|data_info|read_mux_out [12]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|data_info|read_mux_out[12] .extended_lut = "off";defparam \u0|data_info|read_mux_out[12] .lut_mask = 64'h0A0A0A0A00000000;defparam \u0|data_info|read_mux_out[12] .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y16_N19dffeas \u0|data_info|readdata[12] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|data_info|read_mux_out [12]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|data_info|readdata [12]),.prn(vcc));// synopsys translate_offdefparam \u0|data_info|readdata[12] .is_wysiwyg = "true";defparam \u0|data_info|readdata[12] .power_up = "low";// synopsys translate_on// Location: FF_X31_Y16_N14dffeas \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[12] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|data_info|readdata [12]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [12]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[12] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[12] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y33_N39cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout = ( \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used// [0]) # (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129]~q ))) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0] &// (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129]~q )))) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0]),.datab(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]),.datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h030203020F0A0F0A;defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y33_N27cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[1]~1 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0] &// \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0]),.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h05FF05FF00000000;defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y33_N29dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";// synopsys translate_on// Location: FF_X31_Y16_N35dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][12] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~12_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][12]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][12] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][12] .power_up = "low";// synopsys translate_on// Location: LABCELL_X31_Y16_N33cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~12 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~12_combout = (!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [12])) #// (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][12]~q ))).dataa(gnd),.datab(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [12]),.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][12]~q ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~12_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~12 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~12 .lut_mask = 64'h0C3F0C3F0C3F0C3F;defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~12 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y33_N18cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout & (// !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hF0F0F0F0FFFFFFFF;defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X31_Y16_N41dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][12] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~12_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][12]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][12] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][12] .power_up = "low";// synopsys translate_on// Location: LABCELL_X31_Y16_N39cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~32 (// Equation(s):// \u0|mm_interconnect_0|rsp_mux_001|src_payload~32_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][12]~q & ( (\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout &// ((!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ) # (\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [12]))) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][12]~q & (// (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout & (\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [12] & \u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout )) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [12]),.datad(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),.datae(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][12]~q ),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~32_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~32 .extended_lut = "off";defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~32 .lut_mask = 64'h000500AF000500AF;defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~32 .shared_arith = "off";// synopsys translate_on// Location: FF_X54_Y5_N17dffeas \m_x|bit_c_3 (.clk(\m_x|always3~0_combout ),.d(gnd),.asdata(\m_x|bit_c_1~q ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\m_x|bit_c_3~q ),.prn(vcc));// synopsys translate_offdefparam \m_x|bit_c_3 .is_wysiwyg = "true";defparam \m_x|bit_c_3 .power_up = "low";// synopsys translate_on// Location: MLABCELL_X55_Y5_N45cyclonev_lcell_comb \m_x|control_r[3]~feeder (// Equation(s):// \m_x|control_r[3]~feeder_combout = ( \m_x|bit_c_3~q ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\m_x|bit_c_3~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|control_r[3]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|control_r[3]~feeder .extended_lut = "off";defparam \m_x|control_r[3]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \m_x|control_r[3]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X55_Y5_N47dffeas \m_x|control_r[3] (.clk(\m_x|always1~0_combout ),.d(\m_x|control_r[3]~feeder_combout ),.asdata(vcc),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\m_x|control_r [3]),.prn(vcc));// synopsys translate_offdefparam \m_x|control_r[3] .is_wysiwyg = "true";defparam \m_x|control_r[3] .power_up = "low";// synopsys translate_on// Location: FF_X55_Y5_N35dffeas \m_x|control_p_r[3] (.clk(\m_x|always2~0_combout ),.d(gnd),.asdata(\m_x|control_r [3]),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\m_x|control_p_r [3]),.prn(vcc));// synopsys translate_offdefparam \m_x|control_p_r[3] .is_wysiwyg = "true";defparam \m_x|control_p_r[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X53_Y9_N33cyclonev_lcell_comb \m_x|control~3 (// Equation(s):// \m_x|control~3_combout = ( \m_x|control_p_r [3] & ( (\m_x|ready_control_p_r~q ) # (\m_x|control [3]) ) ) # ( !\m_x|control_p_r [3] & ( (\m_x|control [3] & !\m_x|ready_control_p_r~q ) ) ).dataa(!\m_x|control [3]),.datab(gnd),.datac(!\m_x|ready_control_p_r~q ),.datad(gnd),.datae(!\m_x|control_p_r [3]),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|control~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|control~3 .extended_lut = "off";defparam \m_x|control~3 .lut_mask = 64'h50505F5F50505F5F;defparam \m_x|control~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X53_Y9_N50dffeas \m_x|control[3] (.clk(!\m_x|always3~0_combout ),.d(gnd),.asdata(\m_x|control~3_combout ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(!\m_x|state_data_process.01~q ),.devclrn(devclrn),.devpor(devpor),.q(\m_x|control [3]),.prn(vcc));// synopsys translate_offdefparam \m_x|control[3] .is_wysiwyg = "true";defparam \m_x|control[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X53_Y9_N48cyclonev_lcell_comb \m_x|control_l_r~3 (// Equation(s):// \m_x|control_l_r~3_combout = ( \m_x|control [3] & ( (\m_x|control_l_r [3]) # (\m_x|ready_control_p_r~q ) ) ) # ( !\m_x|control [3] & ( (!\m_x|ready_control_p_r~q & \m_x|control_l_r [3]) ) ).dataa(gnd),.datab(!\m_x|ready_control_p_r~q ),.datac(!\m_x|control_l_r [3]),.datad(gnd),.datae(!\m_x|control [3]),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|control_l_r~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|control_l_r~3 .extended_lut = "off";defparam \m_x|control_l_r~3 .lut_mask = 64'h0C0C3F3F0C0C3F3F;defparam \m_x|control_l_r~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X53_Y9_N53dffeas \m_x|control_l_r[3] (.clk(!\m_x|always3~0_combout ),.d(gnd),.asdata(\m_x|control_l_r~3_combout ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(!\m_x|state_data_process.01~q ),.devclrn(devclrn),.devpor(devpor),.q(\m_x|control_l_r [3]),.prn(vcc));// synopsys translate_offdefparam \m_x|control_l_r[3] .is_wysiwyg = "true";defparam \m_x|control_l_r[3] .power_up = "low";// synopsys translate_on// Location: FF_X53_Y9_N31dffeas \m_x|info[13] (.clk(!\m_x|always3~0_combout ),.d(gnd),.asdata(\m_x|control_l_r [3]),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\m_x|state_data_process.01~q ),.devclrn(devclrn),.devpor(devpor),.q(\m_x|info [13]),.prn(vcc));// synopsys translate_offdefparam \m_x|info[13] .is_wysiwyg = "true";defparam \m_x|info[13] .power_up = "low";// synopsys translate_on// Location: LABCELL_X31_Y13_N21cyclonev_lcell_comb \u0|data_info|read_mux_out[13] (// Equation(s):// \u0|data_info|read_mux_out [13] = ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( (\m_x|info [13] &// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]) ) ).dataa(!\m_x|info [13]),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|data_info|read_mux_out [13]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|data_info|read_mux_out[13] .extended_lut = "off";defparam \u0|data_info|read_mux_out[13] .lut_mask = 64'h5050505000000000;defparam \u0|data_info|read_mux_out[13] .shared_arith = "off";// synopsys translate_on// Location: FF_X31_Y13_N23dffeas \u0|data_info|readdata[13] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|data_info|read_mux_out [13]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|data_info|readdata [13]),.prn(vcc));// synopsys translate_offdefparam \u0|data_info|readdata[13] .is_wysiwyg = "true";defparam \u0|data_info|readdata[13] .power_up = "low";// synopsys translate_on// Location: FF_X31_Y13_N20dffeas \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[13] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|data_info|readdata [13]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [13]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[13] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[13] .power_up = "low";// synopsys translate_on// Location: FF_X30_Y16_N50dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][13] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][13]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][13] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][13] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y16_N48cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][13]~q & ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] ) ) # (// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][13]~q & ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [13] ) ) ) # (// !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][13]~q & ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [13] ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [13]),.datad(gnd),.datae(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][13]~q ),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13 .lut_mask = 64'h0F0F0F0F0000FFFF;defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y16_N35dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][13] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][13]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][13] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][13] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y16_N33cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~33 (// Equation(s):// \u0|mm_interconnect_0|rsp_mux_001|src_payload~33_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout & ( (\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [13] &// \u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout & ( (\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout &// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][13]~q ) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [13]),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][13]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~33_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~33 .extended_lut = "off";defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~33 .lut_mask = 64'h000F000F05050505;defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~33 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y37_N11dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y36_N15cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y35_N15cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y35_N17dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y35_N21cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter [0] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~q ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0 .lut_mask = 64'h000000000F0F0F0F;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y35_N0cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y35_N2dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y31_N21cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal2~2 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal2~2_combout = ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( \u0|mm_interconnect_0|router_001|Equal2~0_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] &// (\u0|mm_interconnect_0|router_001|Equal1~1_combout & \u0|mm_interconnect_0|router_001|Equal1~0_combout ))) ) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),.datac(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),.datad(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),.datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),.dataf(!\u0|mm_interconnect_0|router_001|Equal2~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal2~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal2~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal2~2 .lut_mask = 64'h0000000000040000;defparam \u0|mm_interconnect_0|router_001|Equal2~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y31_N42cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal2~1 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal2~1_combout = (\u0|mm_interconnect_0|router_001|Equal2~0_combout & (\u0|mm_interconnect_0|router_001|Equal1~0_combout & \u0|mm_interconnect_0|router_001|Equal1~1_combout )).dataa(gnd),.datab(!\u0|mm_interconnect_0|router_001|Equal2~0_combout ),.datac(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),.datad(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal2~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal2~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal2~1 .lut_mask = 64'h0003000300030003;defparam \u0|mm_interconnect_0|router_001|Equal2~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y31_N48cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal1~3 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal1~3_combout = ( \u0|mm_interconnect_0|router_001|Equal1~1_combout & ( (\u0|mm_interconnect_0|router_001|Equal1~0_combout & \u0|mm_interconnect_0|router_001|Equal1~2_combout ) ) ).dataa(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal1~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal1~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal1~3 .lut_mask = 64'h0000000005050505;defparam \u0|mm_interconnect_0|router_001|Equal1~3 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y30_N54cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|src_data[102]~0 (// Equation(s):// \u0|mm_interconnect_0|router_001|src_data[102]~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( \u0|mm_interconnect_0|router_001|Equal1~3_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & ((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16])// # ((!\u0|mm_interconnect_0|router_001|Equal2~1_combout )))) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & ((!\u0|mm_interconnect_0|router_001|Equal2~1_combout ) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR// [16])))) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( \u0|mm_interconnect_0|router_001|Equal1~3_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] $// (((\u0|mm_interconnect_0|router_001|Equal2~1_combout & \u0|hps_0|fpga_interfaces|h2f_ARADDR [18]))))) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (!\u0|mm_interconnect_0|router_001|Equal2~1_combout & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] &// \u0|hps_0|fpga_interfaces|h2f_ARADDR [19]))) ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( !\u0|mm_interconnect_0|router_001|Equal1~3_combout & ( (!\u0|mm_interconnect_0|router_001|Equal2~1_combout ) # (!\u0|hps_0|fpga_interfaces|h2f_ARADDR// [16] $ (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18])) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( !\u0|mm_interconnect_0|router_001|Equal1~3_combout & ( (!\u0|mm_interconnect_0|router_001|Equal2~1_combout ) #// ((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [18])) ) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),.datab(!\u0|mm_interconnect_0|router_001|Equal2~1_combout ),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),.datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),.dataf(!\u0|mm_interconnect_0|router_001|Equal1~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|src_data[102]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|src_data[102]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|src_data[102]~0 .lut_mask = 64'hECECEDEDA842EDE0;defparam \u0|mm_interconnect_0|router_001|src_data[102]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y30_N56dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|router_001|src_data[102]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y30_N24cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|src_data[100]~1 (// Equation(s):// \u0|mm_interconnect_0|router_001|src_data[100]~1_combout = ( \u0|mm_interconnect_0|router_001|Equal2~1_combout & ( \u0|mm_interconnect_0|router_001|Equal1~3_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] &// ((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16])) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & ((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]))))) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] &// (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] $ (((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [19]))))) ) ) ) # ( !\u0|mm_interconnect_0|router_001|Equal2~1_combout & (// \u0|mm_interconnect_0|router_001|Equal1~3_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] $ (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19])))) #// (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] $ (((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [19]))))) ) ) ) # ( \u0|mm_interconnect_0|router_001|Equal2~1_combout & (// !\u0|mm_interconnect_0|router_001|Equal1~3_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]))) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] &// ((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]))) ) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),.datae(!\u0|mm_interconnect_0|router_001|Equal2~1_combout ),.dataf(!\u0|mm_interconnect_0|router_001|Equal1~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|src_data[100]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|src_data[100]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|src_data[100]~1 .lut_mask = 64'h00007C7C26527C52;defparam \u0|mm_interconnect_0|router_001|src_data[100]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y30_N25dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|router_001|src_data[100]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y30_N42cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|src_data[101]~2 (// Equation(s):// \u0|mm_interconnect_0|router_001|src_data[101]~2_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( \u0|mm_interconnect_0|router_001|Equal1~3_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & ((!\u0|hps_0|fpga_interfaces|h2f_ARADDR// [19]))) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18])) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( \u0|mm_interconnect_0|router_001|Equal1~3_combout & (// (!\u0|mm_interconnect_0|router_001|Equal2~1_combout & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]))) # (\u0|mm_interconnect_0|router_001|Equal2~1_combout & ((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] &// (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16])) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & ((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]))))) ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( !\u0|mm_interconnect_0|router_001|Equal1~3_combout & (// (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (\u0|mm_interconnect_0|router_001|Equal2~1_combout & \u0|hps_0|fpga_interfaces|h2f_ARADDR [18])) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( !\u0|mm_interconnect_0|router_001|Equal1~3_combout &// ( (\u0|mm_interconnect_0|router_001|Equal2~1_combout & ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]))) ) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),.datab(!\u0|mm_interconnect_0|router_001|Equal2~1_combout ),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),.datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),.dataf(!\u0|mm_interconnect_0|router_001|Equal1~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|src_data[101]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|src_data[101]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|src_data[101]~2 .lut_mask = 64'h131302021B18AF05;defparam \u0|mm_interconnect_0|router_001|src_data[101]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y30_N43dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|router_001|src_data[101]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y30_N9cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0 (// Equation(s):// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0_combout = ( \u0|mm_interconnect_0|router_001|src_data[100]~1_combout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [0] &// (!\u0|mm_interconnect_0|router_001|src_data[101]~2_combout $ (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [1]))) ) ) # ( !\u0|mm_interconnect_0|router_001|src_data[100]~1_combout & (// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [0] & (!\u0|mm_interconnect_0|router_001|src_data[101]~2_combout $ (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [1]))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [0]),.datac(!\u0|mm_interconnect_0|router_001|src_data[101]~2_combout ),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|router_001|src_data[100]~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0 .lut_mask = 64'hC00CC00C30033003;defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y30_N36cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|src_data[103]~3 (// Equation(s):// \u0|mm_interconnect_0|router_001|src_data[103]~3_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( \u0|mm_interconnect_0|router_001|Equal1~3_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & ((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] &// (!\u0|mm_interconnect_0|router_001|Equal2~1_combout & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [18])) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]))))) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & (// \u0|mm_interconnect_0|router_001|Equal1~3_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & ((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] $ (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19])))) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] &// (((!\u0|mm_interconnect_0|router_001|Equal2~1_combout & \u0|hps_0|fpga_interfaces|h2f_ARADDR [18])) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]))) ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( !\u0|mm_interconnect_0|router_001|Equal1~3_combout// & ( (!\u0|mm_interconnect_0|router_001|Equal2~1_combout ) # ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [18])) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & (// !\u0|mm_interconnect_0|router_001|Equal1~3_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]) # (!\u0|mm_interconnect_0|router_001|Equal2~1_combout ) ) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),.datab(!\u0|mm_interconnect_0|router_001|Equal2~1_combout ),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),.datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),.dataf(!\u0|mm_interconnect_0|router_001|Equal1~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|src_data[103]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|src_data[103]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|src_data[103]~3 .lut_mask = 64'hEEEECDCDA45F8500;defparam \u0|mm_interconnect_0|router_001|src_data[103]~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y30_N37dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|router_001|src_data[103]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y30_N30cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|src_data[104]~4 (// Equation(s):// \u0|mm_interconnect_0|router_001|src_data[104]~4_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( \u0|mm_interconnect_0|router_001|Equal1~3_combout & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [19] ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR// [17] & ( \u0|mm_interconnect_0|router_001|Equal1~3_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & ((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]) # (\u0|mm_interconnect_0|router_001|Equal2~1_combout// )))) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( !\u0|mm_interconnect_0|router_001|Equal1~3_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (\u0|mm_interconnect_0|router_001|Equal2~1_combout & !\u0|hps_0|fpga_interfaces|h2f_ARADDR// [18])) ) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),.datab(!\u0|mm_interconnect_0|router_001|Equal2~1_combout ),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),.datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),.dataf(!\u0|mm_interconnect_0|router_001|Equal1~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|src_data[104]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|src_data[104]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|src_data[104]~4 .lut_mask = 64'h10100000501000FF;defparam \u0|mm_interconnect_0|router_001|src_data[104]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y30_N31dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|router_001|src_data[104]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y30_N6cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1 (// Equation(s):// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1_combout = ( \u0|mm_interconnect_0|router_001|src_data[104]~4_combout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [4] &// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [3] $ (\u0|mm_interconnect_0|router_001|src_data[103]~3_combout ))) ) ) # ( !\u0|mm_interconnect_0|router_001|src_data[104]~4_combout & (// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [4] & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [3] $ (\u0|mm_interconnect_0|router_001|src_data[103]~3_combout ))) ) ).dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [3]),.datab(gnd),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [4]),.datad(!\u0|mm_interconnect_0|router_001|src_data[103]~3_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|router_001|src_data[104]~4_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1 .lut_mask = 64'hA050A0500A050A05;defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y30_N48cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0 (// Equation(s):// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout = ( \u0|mm_interconnect_0|router_001|src_data[102]~0_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1_combout & (// (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) # ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [2] &// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|router_001|src_data[102]~0_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1_combout & (// (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) # ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [2] &// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0_combout )))) ) ) ) # ( \u0|mm_interconnect_0|router_001|src_data[102]~0_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1_combout & (// (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) ) ) ) # ( !\u0|mm_interconnect_0|router_001|src_data[102]~0_combout & (// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) ) ) ).dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [2]),.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0_combout ),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),.datae(!\u0|mm_interconnect_0|router_001|src_data[102]~0_combout ),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0 .lut_mask = 64'h0F000F000F020F01;defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y31_N37dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[16] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|router_001|Equal2~2_combout ),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [16]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[16] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[16] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y36_N51cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|last_cycle~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout = ( \u0|mm_interconnect_0|router_001|Equal2~2_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) #// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [16]))) ) ).dataa(gnd),.datab(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [16]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|router_001|Equal2~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_016|last_cycle~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_016|last_cycle~0 .lut_mask = 64'h0000000030333033;defparam \u0|mm_interconnect_0|cmd_mux_016|last_cycle~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y36_N0cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & (// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout &// \u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout )) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),.datad(!\u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000000000500050;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y36_N5dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y31_N18cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal9~0 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal9~0_combout = ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [18] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal9~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal9~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal9~0 .lut_mask = 64'h00000000FFFF0000;defparam \u0|mm_interconnect_0|router_001|Equal9~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y31_N36cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal9~1 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal9~1_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & ( \u0|mm_interconnect_0|router_001|Equal9~0_combout & ( (\u0|mm_interconnect_0|router_001|Equal1~1_combout &// (\u0|mm_interconnect_0|router_001|Equal1~2_combout & (\u0|mm_interconnect_0|router_001|Equal1~0_combout & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]))) ) ) ).dataa(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),.datab(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),.datac(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),.datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),.dataf(!\u0|mm_interconnect_0|router_001|Equal9~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal9~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal9~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal9~1 .lut_mask = 64'h0000000000000100;defparam \u0|mm_interconnect_0|router_001|Equal9~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y31_N26dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|router_001|Equal9~1_combout ),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y31_N24cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [5] & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & \u0|mm_interconnect_0|router_001|Equal9~1_combout ) ) ) # (// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [5] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q & (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & \u0|mm_interconnect_0|router_001|Equal9~1_combout// )) ) ).dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),.datab(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),.datac(gnd),.datad(!\u0|mm_interconnect_0|router_001|Equal9~1_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0 .lut_mask = 64'h0022002200330033;defparam \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X10_Y31_N3cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y31_N5dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: LABCELL_X10_Y31_N21cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y31_N23dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: LABCELL_X10_Y31_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout & ( (\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout & (\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] &// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ),.datac(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0003000300000000;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X9_Y31_N2dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";// synopsys translate_on// Location: FF_X9_Y31_N14dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";// synopsys translate_on// Location: FF_X9_Y31_N38dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X10_Y31_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0_combout = ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout & (// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~q & \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [0]) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [0]),.datad(gnd),.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0000000005050000;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y31_N56dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg[0] .power_up = "low";// synopsys translate_on// Location: FF_X10_Y31_N20dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";// synopsys translate_on// Location: LABCELL_X10_Y31_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout & ( ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][129]~q )) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout & (// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][129]~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][129]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h003300330F3F0F3F;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X9_Y31_N24cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout = (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'hF0F0F0F000000000;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X9_Y31_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & (// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout ) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h1515151500000000;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X8_Y31_N9cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X8_Y31_N11dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X10_Y32_N21cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]// $ (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]// $ (((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))))) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1])))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .lut_mask = 64'h278D278D22882288;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y32_N23dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y22_N57cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_payload[0] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_009|src_payload [0] = ( \u0|hps_0|fpga_interfaces|h2f_WLAST [0] & ( (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WLAST [0] &// ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),.datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_009|src_payload [0]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_009|src_payload[0] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_009|src_payload[0] .lut_mask = 64'h5555555577777777;defparam \u0|mm_interconnect_0|cmd_mux_009|src_payload[0] .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y31_N3cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal1~4 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal1~4_combout = ( \u0|mm_interconnect_0|router_001|Equal1~0_combout & ( \u0|mm_interconnect_0|router_001|Equal1~1_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] &// (\u0|mm_interconnect_0|router_001|Equal1~2_combout & \u0|hps_0|fpga_interfaces|h2f_ARADDR [16])) ) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),.datab(gnd),.datac(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),.datae(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),.dataf(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal1~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal1~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal1~4 .lut_mask = 64'h000000000000000A;defparam \u0|mm_interconnect_0|router_001|Equal1~4 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y27_N15cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal15~0 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal15~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & ( (\u0|mm_interconnect_0|router_001|Equal1~4_combout & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]) ) ).dataa(!\u0|mm_interconnect_0|router_001|Equal1~4_combout ),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),.datad(gnd),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal15~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal15~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal15~0 .lut_mask = 64'h0000000050505050;defparam \u0|mm_interconnect_0|router_001|Equal15~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y27_N17dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[9] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|router_001|Equal15~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [9]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[9] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[9] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y27_N33cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src9_valid~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_demux_001|src9_valid~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) #// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [9]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [9]),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_demux_001|src9_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_demux_001|src9_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_demux_001|src9_valid~0 .lut_mask = 64'h00000000FF0FFF0F;defparam \u0|mm_interconnect_0|cmd_demux_001|src9_valid~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y27_N30cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_valid~1 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout = ( \u0|mm_interconnect_0|router_001|Equal1~4_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] &// (\u0|mm_interconnect_0|cmd_demux_001|src9_valid~0_combout & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]))) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),.datac(!\u0|mm_interconnect_0|cmd_demux_001|src9_valid~0_combout ),.datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|router_001|Equal1~4_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_009|src_valid~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_009|src_valid~1 .lut_mask = 64'h0000000000020002;defparam \u0|mm_interconnect_0|cmd_mux_009|src_valid~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y25_N24cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~0_combout = !\u0|mm_interconnect_0|cmd_mux_009|update_grant~0_combout.dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_009|update_grant~0_combout ),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~0 .lut_mask = 64'hF0F0F0F0F0F0F0F0;defparam \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y25_N25dffeas \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y22_N36cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[33] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_009|src_data [33] = ((\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WSTRB [1])) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]).dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),.datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),.datac(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [1]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [33]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_009|src_data[33] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[33] .lut_mask = 64'h5757575757575757;defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[33] .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y22_N30cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout & (// !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] &// !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),.datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .lut_mask = 64'h88888888AAAAAAAA;defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y22_N32dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";// synopsys translate_on// Location: FF_X15_Y22_N59dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_009|src_payload [0]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y21_N45cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y21_N47dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y22_N3cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~2 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~2_combout = ( \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~0_combout & ( !\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0] $// (!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [1]) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0]),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~2 .lut_mask = 64'h0000000055AA55AA;defparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y22_N5dffeas \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y22_N30cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y22_N32dffeas \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y22_N54cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout = ( \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~q & ( !\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [1] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0 .lut_mask = 64'h00000000FF00FF00;defparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y22_N51cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y22_N53dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y25_N51cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_valid~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout = ( \u0|mm_interconnect_0|router|Equal7~1_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout & (// (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & (\u0|mm_interconnect_0|router|Equal14~0_combout & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout & \u0|mm_interconnect_0|cmd_demux|src9_valid~0_combout// ))) ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),.datab(!\u0|mm_interconnect_0|router|Equal14~0_combout ),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ),.datad(!\u0|mm_interconnect_0|cmd_demux|src9_valid~0_combout ),.datae(!\u0|mm_interconnect_0|router|Equal7~1_combout ),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_009|src_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_009|src_valid~0 .lut_mask = 64'h0000000100000000;defparam \u0|mm_interconnect_0|cmd_mux_009|src_valid~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y25_N54cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout = ( \u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout & (// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) ) # ( !\u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout & (// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) # (!\u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datad(!\u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .lut_mask = 64'hFFF0FFF0F0F0F0F0;defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y22_N24cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(gnd),.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'hFF33FF33FF00FF00;defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y22_N26dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";// synopsys translate_on// Location: FF_X17_Y22_N8dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y22_N51cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|local_write~0 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & (// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent|local_write~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent|local_write~0 .lut_mask = 64'h0000000000FF00FF;defparam \u0|mm_interconnect_0|link_disable_s1_agent|local_write~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y22_N18cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout &// \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0]) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout &// (!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0] $ (((!\u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout ) # (\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ))))) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout ),.datab(!\u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout ),.datac(!\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ),.datad(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4 .lut_mask = 64'h1045104500550055;defparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y22_N11dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";// synopsys translate_on// Location: FF_X17_Y22_N17dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y22_N6cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & (// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & (// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0 .lut_mask = 64'h030303030F0F0F0F;defparam \u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y22_N42cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout & (// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] &// ((\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4_combout ) # (\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout & (// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (\u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout &// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4_combout ) # (\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout )))) ) ) ) # (// \u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4_combout ) # (\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ))) ) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ),.datab(!\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4_combout ),.datac(!\u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout ),.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),.datae(!\u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout ),.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h0000770007007700;defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y22_N50dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][69] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][69]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][69] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][69] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y22_N48cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~1 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][69]~q ) ) # (// !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.datac(gnd),.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][69]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h3333333300FF00FF;defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y22_N8dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y22_N3cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout = (// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) ) # (// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & ( (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) ) # ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [3] & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) ) ) # (// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & ( (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h5500AAFF5050FAFA;defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y22_N5dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y22_N54cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [3] & \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h00C000C000000000;defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y22_N15cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout = (// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & (((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout )))) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # (// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout )))) #// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .lut_mask = 64'h10DC10DCFE32FE32;defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y22_N53dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y22_N24cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout = (// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ) ) ) # (// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ) ) ) # (// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) )// ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ( (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout &// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .lut_mask = 64'h5050AFAF00CCFFCC;defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y22_N26dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";// synopsys translate_on// Location: FF_X13_Y22_N59dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~9_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y22_N57cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~9 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~9_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6])) #// (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # (// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][78]~q ) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][78]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h000F000F505F505F;defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y22_N23dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~9_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";// synopsys translate_on// Location: FF_X13_Y22_N38dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~8_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y22_N36cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~8 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~8_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) #// (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][77]~q ))) ) ) # (// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][77]~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][77]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h003300330C3F0C3F;defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y22_N2dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~8_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";// synopsys translate_on// Location: FF_X13_Y22_N41dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y22_N39cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~5 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) #// (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][74]~q ))) ) ) # (// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] &// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] &// ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][74]~q ))) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][74]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h0C3F0C3F44774477;defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y22_N5dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~5_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";// synopsys translate_on// Location: FF_X13_Y22_N35dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~7_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y22_N33cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~7 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) #// (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][76]~q ))) ) ) # (// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][76]~q ) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][76]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h005500550A5F0A5F;defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y22_N17dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~7_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";// synopsys translate_on// Location: FF_X13_Y22_N32dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y22_N30cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~6 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) #// (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][75]~q ))) ) ) # (// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][75]~q ) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][75]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h005500550A5F0A5F;defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y22_N29dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~6_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";// synopsys translate_on// Location: FF_X10_Y22_N35dffeas \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";// synopsys translate_on// Location: LABCELL_X10_Y22_N12cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~0 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~0_combout = ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q & ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy~q & (// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q & (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77]~q & (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q &// !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q ),.datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77]~q ),.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q ),.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q ),.datae(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q ),.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0800000000000000;defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y22_N9cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0_combout = ( !\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout & ( (\u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout &// !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h5050505000000000;defparam \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X11_Y22_N18cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~1 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~1_combout = (\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4_combout & \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0_combout ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4_combout ),.datad(!\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0_combout ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h000F000F000F000F;defparam \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X11_Y22_N20dffeas \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg[0] .power_up = "low";// synopsys translate_on// Location: FF_X17_Y22_N38dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y22_N36cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~0 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~0_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][129]~q & ( \u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout & (// (((\u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout & \u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout )) #// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout )) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # (// !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][129]~q & ( \u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] &// (((\u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout & \u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout )) #// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][129]~q & (// !\u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout & ( ((\u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout & \u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout )) #// (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][129]~q & ( !\u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout & (// (\u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout & (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout ),.datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ),.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datae(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][129]~q ),.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h0404373704CC37FF;defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X11_Y22_N5dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~0_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";// synopsys translate_on// Location: LABCELL_X11_Y22_N9cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129]~q &// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0]) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0]) #// ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129]~q & \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0])) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129]~q ),.datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0]),.datac(!\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0 .lut_mask = 64'hF1F1F1F111111111;defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X11_Y22_N24cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~1 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~1_combout = ( !\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0_combout & ( \u0|mm_interconnect_0|rsp_demux_009|WideOr0~0_combout ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|rsp_demux_009|WideOr0~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~1 .lut_mask = 64'h0F0F0F0F00000000;defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X11_Y22_N30cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[1]~1 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( !\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~1_combout & ( ((\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0] &// \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [1]) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h05FF05FF00000000;defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X11_Y22_N32dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X11_Y22_N33cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[0]~0 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~1_combout & ( ((\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0] &// \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~1_combout & (// ((\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [1])) # (\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0]) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h50FF50FF0F5F0F5F;defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X11_Y22_N35dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X11_Y22_N39cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|comb~0 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0] ) ) # (// !\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129]~q ) #// (\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0]))) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0]),.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent|comb~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent|comb~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent|comb~0 .lut_mask = 64'h0555055555555555;defparam \u0|mm_interconnect_0|link_disable_s1_agent|comb~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X10_Y22_N0cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy~q & (// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2] ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h0000000033333333;defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X10_Y22_N42cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2_combout ) ) ) # (// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q &// (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2_combout )) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ),.datad(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h0A000A000F000F00;defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y22_N44dffeas \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X10_Y22_N45cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout = ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77]~q & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q &// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q & !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q )) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q ),.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hA000A00000000000;defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X10_Y22_N36cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~2 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [4]))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datad(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h3FC03FC0FF00FF00;defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X10_Y22_N3cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77]~q & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q &// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q & !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q )) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77]~q & (// ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q ) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q )) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q ) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q ),.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h5FFF5FFFA000A000;defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X10_Y22_N39cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~1_combout & (// (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout & (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~2_combout )) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~1_combout & ( (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ) # (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~2_combout ))) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datad(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h5550555005000500;defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y22_N41dffeas \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X10_Y22_N24cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [4] &// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datad(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hC000C00000000000;defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X10_Y22_N54cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout &// (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q $ (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout )))) ) )// ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout & (// (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q $ (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout )) #// (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q $// (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout )) # (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # (// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout & (// (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q// $ (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout )))) ) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q ),.datab(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datad(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout ),.datae(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h1020132313231020;defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y22_N56dffeas \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X10_Y22_N30cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout & ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout & (// (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q ))) # (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [6])))) ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout & (// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [6] &// (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout )) ) ) ) # (// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout & ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout// & (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q & \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout )) ) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datab(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q ),.datad(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ),.datae(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout ),.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h000000C0002200E2;defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y22_N32dffeas \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";// synopsys translate_on// Location: LABCELL_X10_Y22_N27cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy~q & (// (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1_combout ) # ((\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [7]) #// (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2])) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1_combout ),.datab(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00000000BFBFBFBF;defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X10_Y22_N6cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q $ ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q )))) # (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (((\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q $ ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q )))) # (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (((!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q ),.datab(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q ),.datad(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datae(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h00000000B78484B7;defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y22_N8dffeas \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X10_Y22_N21cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~0 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [4] $ (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datab(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h66666666AAAAAAAA;defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X10_Y22_N48cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout & (// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~0_combout ) ) ) # (// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q $ (((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q ) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q ),.datab(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~0_combout ),.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q ),.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q ),.datae(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ),.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h0000A05F0000CCCC;defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y22_N50dffeas \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X10_Y22_N18cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (// (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [6])) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datab(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datac(gnd),.datad(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'h8800880000000000;defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y22_N29dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y22_N27cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~3 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~3_combout = (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg// [66])) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][66]~q ))).dataa(gnd),.datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][66]~q ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h0C3F0C3F0C3F0C3F;defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X11_Y22_N44dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~3_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X11_Y22_N12cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66]~q & ( (!\u0|mm_interconnect_0|link_disable_s1_agent|comb~0_combout ) #// ((!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~0_combout & ((!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1_combout ) #// (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2_combout )))) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~0_combout ),.datab(!\u0|mm_interconnect_0|link_disable_s1_agent|comb~0_combout ),.datac(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1_combout ),.datad(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00000000EEECEEEC;defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X11_Y22_N21cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[0]~1 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout & ( (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0]) #// (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0_combout ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout & ( ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0] &// ((!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0_combout ),.datac(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ),.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h33F733F733FF33FF;defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X11_Y22_N23dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X11_Y22_N3cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0] ) ) # (// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0]) # (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hAFAFAFAFAAAAAAAA;defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X11_Y22_N25dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][69] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~1_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][69]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][69] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][69] .power_up = "low";// synopsys translate_on// Location: FF_X11_Y22_N37dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][68] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~2_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][68]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][68] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][68] .power_up = "low";// synopsys translate_on// Location: LABCELL_X11_Y22_N0cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~2 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~2_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used// [1]) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][68]~q ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & (// (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][68]~q & \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][68]~q ),.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h03030303F3F3F3F3;defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X11_Y22_N10dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][68] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~2_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][68]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][68] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][68] .power_up = "low";// synopsys translate_on// Location: LABCELL_X11_Y22_N15cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_009|src0_valid~0 (// Equation(s):// \u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout = ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66]~q & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][69]~q &// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][68]~q ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][69]~q ),.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][68]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|rsp_demux_009|src0_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|rsp_demux_009|src0_valid~0 .lut_mask = 64'h00F000F000000000;defparam \u0|mm_interconnect_0|rsp_demux_009|src0_valid~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X11_Y22_N36cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_009|WideOr0~0 (// Equation(s):// \u0|mm_interconnect_0|rsp_demux_009|WideOr0~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( (!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout ) # (\u0|hps_0|fpga_interfaces|h2f_BREADY [0]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_RREADY// [0] & ( (\u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout & \u0|hps_0|fpga_interfaces|h2f_BREADY [0]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout ),.datac(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),.datad(gnd),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|rsp_demux_009|WideOr0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|rsp_demux_009|WideOr0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|rsp_demux_009|WideOr0~0 .lut_mask = 64'h03030303CFCFCFCF;defparam \u0|mm_interconnect_0|rsp_demux_009|WideOr0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X11_Y22_N6cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|comb~0_combout & ( \u0|mm_interconnect_0|rsp_demux_009|WideOr0~0_combout ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|rsp_demux_009|WideOr0~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|comb~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0 .lut_mask = 64'h000000000F0F0F0F;defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X11_Y22_N54cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[1]~0 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0_combout &// ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0_combout & (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0])) ) ) # (// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0_combout & (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout &// ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0_combout & ((!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout &// (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout & ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]))))) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0_combout ),.datab(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ),.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[1]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h049D049D05AF05AF;defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X11_Y22_N56dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[1]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y22_N33cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|m0_write (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent|m0_write~combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout & ( (!\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout &// !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent|m0_write~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent|m0_write .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent|m0_write .lut_mask = 64'h00000000A0A0A0A0;defparam \u0|mm_interconnect_0|link_disable_s1_agent|m0_write .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y22_N57cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~0 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~0_combout = ( \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0] & ( (\u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~q &// (((\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0_combout & \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [1])) # (\u0|mm_interconnect_0|link_disable_s1_agent|m0_write~combout ))) ) ) # (// !\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0] & ( (\u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~q & ((!\u0|mm_interconnect_0|link_disable_s1_agent|m0_write~combout &// (\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0_combout )) # (\u0|mm_interconnect_0|link_disable_s1_agent|m0_write~combout & ((\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [1]))))) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|m0_write~combout ),.datab(!\u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~q ),.datac(!\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0_combout ),.datad(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~0 .lut_mask = 64'h0213021311131113;defparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y22_N0cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~1 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~1_combout = ( \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~0_combout & ( !\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~0_combout ),.dataf(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~1 .lut_mask = 64'h0000FFFF00000000;defparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y22_N20dffeas \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~1_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y22_N24cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~1 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~1_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] &// (((!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0] & \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout )) # (\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ))) ) ) # (// !\u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0] &// \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout )) # (\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ))) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0]),.datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ),.datad(!\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|local_write~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~1 .lut_mask = 64'h0C4C0C4C0C8C0C8C;defparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y22_N3cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = (// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~1_combout ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~1_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h0000000000FF00FF;defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y22_N48cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout = (// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ) ) ) # (// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ) ) ) # (// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ) ) # (// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datad(gnd),.datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h0F0FF0F00C0CFCFC;defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y22_N50dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y22_N6cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout = (// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ) ) ) # (// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ) ) ) # (// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & ( ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [2]) ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [2] & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] &// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h00A0FF5F00CCFFCC;defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y22_N45cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout = (// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout & (// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout &// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .lut_mask = 64'hF000F00000000000;defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y22_N18cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout = ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout &// (((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// ))) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h010F010F00000000;defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y22_N39cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout = ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .lut_mask = 64'hF0F0F0F000000000;defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y22_N18cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (// \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) #// ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ) #// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) ) ) # (// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & (// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) )// # ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ( !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & (// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) )// # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ( !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & (// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.dataf(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .lut_mask = 64'h005500550055F0FD;defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y22_N36cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout = (!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] &// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout &// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ))).dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .lut_mask = 64'h0200020002000200;defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y22_N27cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout = (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )).dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h0500050005000500;defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y22_N54cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout & (// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout & (// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) ) # ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout & (// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout & (// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout & ( (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout &// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout &// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout &// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ))) ) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),.datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ),.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .lut_mask = 64'h0040FFFFFFFFFFFF;defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y22_N56dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y22_N0cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ) #// ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h0E0C0E0C00000000;defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y23_N30cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_payload[0] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_011|src_payload [0] = ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] ) # ( !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WLAST// [0]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),.datac(gnd),.datad(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_011|src_payload [0]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_011|src_payload[0] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_011|src_payload[0] .lut_mask = 64'h00330033FFFFFFFF;defparam \u0|mm_interconnect_0|cmd_mux_011|src_payload[0] .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y23_N21cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_valid~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_011|src_valid~0_combout = ( \u0|mm_interconnect_0|cmd_demux|src11_valid~0_combout & ( \u0|mm_interconnect_0|router|Equal7~1_combout & (// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout & (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & (\u0|mm_interconnect_0|router|Equal14~0_combout &// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ))) ) ) ).dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),.datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),.datac(!\u0|mm_interconnect_0|router|Equal14~0_combout ),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ),.datae(!\u0|mm_interconnect_0|cmd_demux|src11_valid~0_combout ),.dataf(!\u0|mm_interconnect_0|router|Equal7~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_011|src_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_011|src_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_011|src_valid~0 .lut_mask = 64'h0000000000000001;defparam \u0|mm_interconnect_0|cmd_mux_011|src_valid~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y23_N0cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~0_combout = !\u0|mm_interconnect_0|cmd_mux_011|update_grant~0_combout.dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_mux_011|update_grant~0_combout ),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~0 .lut_mask = 64'hCCCCCCCCCCCCCCCC;defparam \u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y23_N2dffeas \u0|mm_interconnect_0|cmd_mux_011|packet_in_progress (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_011|packet_in_progress .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|cmd_mux_011|packet_in_progress .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y20_N54cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0 (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout = ( !\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [1] & ( \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~q ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~q ),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0 .lut_mask = 64'h3333333300000000;defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y20_N36cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (// \u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] ) ) ) # (// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( \u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout ) ) # (// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] &// (\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] $ (!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter// [0])))) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout ) ).dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),.datac(!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0]),.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout ),.datae(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFFFF0028FFFFAAAA;defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y20_N33cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout & (// !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] &// !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),.datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .lut_mask = 64'h88888888AAAAAAAA;defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y23_N54cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y23_N56dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y23_N0cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h000000003F003F00;defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y27_N0cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal17~0 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal17~0_combout = (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & (\u0|mm_interconnect_0|router_001|Equal1~4_combout & \u0|hps_0|fpga_interfaces|h2f_ARADDR [17])).dataa(gnd),.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),.datac(!\u0|mm_interconnect_0|router_001|Equal1~4_combout ),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal17~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal17~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal17~0 .lut_mask = 64'h0003000300030003;defparam \u0|mm_interconnect_0|router_001|Equal17~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y27_N2dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[11] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|router_001|Equal17~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [11]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[11] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[11] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y27_N54cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src11_valid~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_demux_001|src11_valid~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) #// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [11]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [11]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_demux_001|src11_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_demux_001|src11_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_demux_001|src11_valid~0 .lut_mask = 64'h00000000F0FFF0FF;defparam \u0|mm_interconnect_0|cmd_demux_001|src11_valid~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y23_N39cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_valid~1 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout = ( \u0|mm_interconnect_0|router_001|Equal1~4_combout & ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]// & \u0|mm_interconnect_0|cmd_demux_001|src11_valid~0_combout )) ) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),.datac(!\u0|mm_interconnect_0|cmd_demux_001|src11_valid~0_combout ),.datad(gnd),.datae(!\u0|mm_interconnect_0|router_001|Equal1~4_combout ),.dataf(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_011|src_valid~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_011|src_valid~1 .lut_mask = 64'h0000000000000101;defparam \u0|mm_interconnect_0|cmd_mux_011|src_valid~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y23_N24cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout & (// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) #// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout & (// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (\u0|mm_interconnect_0|cmd_mux_011|src_valid~0_combout &// ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )))) )// ).dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datac(!\u0|mm_interconnect_0|cmd_mux_011|src_valid~0_combout ),.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0105010511551155;defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y20_N35dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y20_N9cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y20_N11dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: FF_X27_Y27_N14dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[2] .power_up = "low";// synopsys translate_on// Location: FF_X15_Y33_N8dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][110] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~14_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][110]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y33_N33cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~5 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_017|src_payload~5_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~5 .lut_mask = 64'h0000000055555555;defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y33_N34dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_017|src_payload~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y33_N6cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~14 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~14_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][110]~q & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] )// ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][110]~q & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used// [1] ) ) ) # ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][110]~q & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & (// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),.datad(gnd),.datae(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][110]~q ),.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~14_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h00000F0FF0F0FFFF;defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y33_N36cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110]~feeder (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110]~feeder_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~14_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~14_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y33_N37dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y31_N30cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~5 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_016|src_payload~5_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),.datad(gnd),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~5 .lut_mask = 64'h000000000F0F0F0F;defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y31_N50dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_016|src_payload~5_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";// synopsys translate_on// Location: FF_X19_Y31_N44dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][110] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~14_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][110]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y31_N42cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~14 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~14_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][110]~q ) ) # (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][110]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~14_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h0F0F0F0F00FF00FF;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y35_N9cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout &// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0] ).dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hFFFFFFFF50505050;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y31_N14dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][110] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~14_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][110]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y29_N0cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y29_N2dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y29_N36cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~2 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~2_combout = ( \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~0_combout & ( !\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] $// (!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0]),.datac(gnd),.datad(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~2 .lut_mask = 64'h0000000033CC33CC;defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y29_N38dffeas \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[1] .power_up = "low";// synopsys translate_on// Location: FF_X25_Y29_N14dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";// synopsys translate_on// Location: FF_X21_Y29_N35dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y29_N33cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|m0_read~0 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent|m0_read~0_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent|m0_read~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|m0_read~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent|m0_read~0 .lut_mask = 64'h000000000FFF0FFF;defparam \u0|mm_interconnect_0|link_start_s1_agent|m0_read~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y29_N51cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0_combout = (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (!\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout &// \u0|mm_interconnect_0|link_start_s1_agent|m0_read~0_combout )).dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ),.datac(!\u0|mm_interconnect_0|link_start_s1_agent|m0_read~0_combout ),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0808080808080808;defparam \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y29_N54cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|m0_write (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent|m0_write~combout = ( !\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout & ( (\u0|mm_interconnect_0|link_start_s1_agent|local_write~0_combout &// !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_start_s1_agent|local_write~0_combout ),.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent|m0_write~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|m0_write .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent|m0_write .lut_mask = 64'h0F000F0000000000;defparam \u0|mm_interconnect_0|link_start_s1_agent|m0_write .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y30_N9cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y30_N11dffeas \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y29_N24cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~0 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~0_combout = ( \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q & ( (!\u0|mm_interconnect_0|link_start_s1_agent|m0_write~combout &// (\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0_combout & ((!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0]) # (\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1])))) #// (\u0|mm_interconnect_0|link_start_s1_agent|m0_write~combout & (((\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0])) # (\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1]))) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1]),.datab(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0]),.datac(!\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0_combout ),.datad(!\u0|mm_interconnect_0|link_start_s1_agent|m0_write~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~0 .lut_mask = 64'h000000000D770D77;defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y29_N12cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~1 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~1_combout = ( \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~0_combout & ( !\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~1 .lut_mask = 64'h00000000FF00FF00;defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y29_N14dffeas \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y29_N45cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout = ( \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q & ( !\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0 .lut_mask = 64'h00000000FF00FF00;defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y29_N15cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|local_write~0_combout & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] &// (((!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] & \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout )) # (\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ))) ) ) # (// !\u0|mm_interconnect_0|link_start_s1_agent|local_write~0_combout & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] &// \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout )) # (\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ))) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0]),.datac(!\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ),.datad(!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|local_write~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1 .lut_mask = 64'h0A2A0A2A0A8A0A8A;defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y36_N15cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y36_N16dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y31_N45cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal19~0 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal19~0_combout = (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [19]).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),.datab(gnd),.datac(gnd),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal19~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal19~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal19~0 .lut_mask = 64'h0055005500550055;defparam \u0|mm_interconnect_0|router_001|Equal19~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y31_N39cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal19~1 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal19~1_combout = ( \u0|mm_interconnect_0|router_001|Equal19~0_combout & ( \u0|mm_interconnect_0|router_001|Equal1~0_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] &// (\u0|mm_interconnect_0|router_001|Equal1~2_combout & (\u0|mm_interconnect_0|router_001|Equal1~1_combout & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]))) ) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),.datab(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),.datac(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),.datae(!\u0|mm_interconnect_0|router_001|Equal19~0_combout ),.dataf(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal19~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal19~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal19~1 .lut_mask = 64'h0000000000000100;defparam \u0|mm_interconnect_0|router_001|Equal19~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y31_N36cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[13]~feeder (// Equation(s):// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[13]~feeder_combout = ( \u0|mm_interconnect_0|router_001|Equal19~1_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|router_001|Equal19~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[13]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[13]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[13]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[13]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y31_N37dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[13] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[13]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [13]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[13] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[13] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y38_N15cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout = ( \u0|mm_interconnect_0|router_001|Equal19~1_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) #// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [13]))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [13]),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|router_001|Equal19~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0 .lut_mask = 64'h000000000F030F03;defparam \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y21_N21cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y21_N15cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout & (// !\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] &// !\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),.datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .lut_mask = 64'hF000F000FF00FF00;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y22_N3cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y22_N5dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y23_N3cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_valid~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [15] & ( \u0|mm_interconnect_0|router_001|Equal21~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] &// \u0|hps_0|fpga_interfaces|h2f_ARVALID [0]) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [15] & ( \u0|mm_interconnect_0|router_001|Equal21~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] &// (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q )) ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),.datab(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),.datad(gnd),.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [15]),.dataf(!\u0|mm_interconnect_0|router_001|Equal21~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_015|src_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_015|src_valid~0 .lut_mask = 64'h0000000010101111;defparam \u0|mm_interconnect_0|cmd_mux_015|src_valid~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y23_N45cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout = ( \u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) # ((!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & !\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout )) ) ) # (// !\u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) # (!\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),.datac(gnd),.datad(!\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .lut_mask = 64'hFFAAFFAAEEAAEEAA;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y21_N42cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) #// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # (((!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & !\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0])) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ))) ) ) # ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q// & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) #// (((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout )))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.datag(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 .extended_lut = "on";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 .lut_mask = 64'hFFEAAAAAFFFFAAAF;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y21_N33cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout = (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .lut_mask = 64'hFFFFFFFF00000000;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y21_N35dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y21_N0cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q// & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .lut_mask = 64'hF0F0F0F000000000;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y21_N54cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout & (// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0])))) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0])) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ))) ) ) ) # (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout & (// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &// (((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0])) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0])))) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0])) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ))) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .lut_mask = 64'h0537050705370505;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y21_N51cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & (// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & (!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] &// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout )) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .lut_mask = 64'h0050005000000000;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y21_N0cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout &// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout &// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h0010001050505050;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y21_N51cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1_combout &// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h000F000F000F000F;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y21_N42cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout = (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h33CF33CF30CC30CC;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y21_N44dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: FF_X17_Y21_N59dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y21_N57cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout = (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ) # (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h0A0FF5FF0A00F5F0;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y21_N2dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y21_N0cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout = (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) ) ) ) # (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h3111DFFF2000CEEE;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y21_N27cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout = (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout &// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .lut_mask = 64'hF000F00000000000;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y21_N39cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] &// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h00000000A000A000;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y21_N8dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y21_N6cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout = (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] &// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout )) ) ) ) # (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout )// # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] &// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout )))) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .lut_mask = 64'h11B1FF5F00A0EE4E;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y21_N12cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout// & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h000000000F000F00;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y21_N24cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout = (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout & (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout & (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) ) # (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout & (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ) )// ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout & (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout & (// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout &// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout & \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ))) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .lut_mask = 64'h555D5555FFFFFFFF;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y21_N26dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y21_N39cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(gnd),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h0077000000770000;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y23_N36cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout & (// \u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout & (// \u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] &// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )))) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout & (// !\u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),.datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),.datae(!\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout ),.dataf(!\u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000151500151515;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y21_N17dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y23_N42cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_payload[0] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_015|src_payload [0] = ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] ) # ( !\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WLAST// [0]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),.datac(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_015|src_payload [0]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_015|src_payload[0] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_015|src_payload[0] .lut_mask = 64'h03030303FFFFFFFF;defparam \u0|mm_interconnect_0|cmd_mux_015|src_payload[0] .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y23_N44dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_015|src_payload [0]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y21_N39cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[87] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_015|src_data [87] = ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] ) ) # ( !\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & (// (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & ( !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]// & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & ( !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),.datab(gnd),.datac(gnd),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),.datae(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [87]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_015|src_data[87] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[87] .lut_mask = 64'h005500550055FFFF;defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[87] .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y21_N18cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[88] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_015|src_data [88] = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( ((\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) ) ) # (// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( (\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),.datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [88]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_015|src_data[88] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[88] .lut_mask = 64'h000F000F555F555F;defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[88] .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y21_N15cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_015|src_data [88] & ( !\u0|mm_interconnect_0|cmd_mux_015|src_data [87] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|cmd_mux_015|src_data [87]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_015|src_data [88]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFF00FF0000000000;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y21_N17dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y21_N42cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[33] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_015|src_data [33] = ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WSTRB [1])) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]).dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),.datac(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [1]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [33]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_015|src_data[33] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[33] .lut_mask = 64'h3737373737373737;defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[33] .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y21_N44dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_015|src_data [33]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y31_N0cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal12~0 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal12~0_combout = ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( (\u0|mm_interconnect_0|router_001|Equal1~0_combout & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] &// (\u0|mm_interconnect_0|router_001|Equal1~1_combout & \u0|mm_interconnect_0|router_001|Equal2~0_combout ))) ) ) ).dataa(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),.datac(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),.datad(!\u0|mm_interconnect_0|router_001|Equal2~0_combout ),.datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal12~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal12~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal12~0 .lut_mask = 64'h0000000000010000;defparam \u0|mm_interconnect_0|router_001|Equal12~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y31_N1dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[21] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|router_001|Equal12~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [21]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[21] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[21] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y31_N12cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|last_cycle~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout = (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & (\u0|mm_interconnect_0|router_001|Equal12~0_combout & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) #// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [21])))).dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),.datab(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),.datac(!\u0|mm_interconnect_0|router_001|Equal12~0_combout ),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [21]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_021|last_cycle~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_021|last_cycle~0 .lut_mask = 64'h0203020302030203;defparam \u0|mm_interconnect_0|cmd_mux_021|last_cycle~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y35_N39cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y35_N41dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y33_N42cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & (// \u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),.datad(gnd),.datae(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),.dataf(!\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000000000003030;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y33_N2dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";// synopsys translate_on// Location: FF_X27_Y33_N5dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y31_N33cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hFFFFFFFF00000000;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y31_N35dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";// synopsys translate_on// Location: FF_X27_Y33_N14dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y33_N15cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1])) ) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1])))) ) ) ) # ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout & (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1])) ) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q// & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1])))) ) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ),.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout ),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h11010101BBABABAB;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y32_N33cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y32_N35dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y32_N6cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout = (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// ( (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]) ) ) ) # (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] ) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q// & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),.datab(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(gnd),.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .lut_mask = 64'h0F0FF0F044444444;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y32_N8dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y32_N36cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout = (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// ( (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ) ) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// ( (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ) ) ) ) # (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]) ) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q// & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]) ) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datac(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .lut_mask = 64'h4444BBBB000F000F;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y32_N38dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y32_N27cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $// (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] &// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg// [4] ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hF0F0F0F078787878;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y32_N57cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout = (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1])) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1])) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),.datad(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .lut_mask = 64'hAAAFAAAF00050005;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y32_N59dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y32_N24cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] &// ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2] & !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h0C000C0000000000;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y32_N55dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y32_N54cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout $// (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))))) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1])))) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout &// ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout $// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.datac(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .lut_mask = 64'h22882288278D278D;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y33_N3cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout = (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout &// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(gnd),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h0044004400440044;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y33_N6cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) )// ) ) # ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout &// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )) ) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout &// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout & \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'hAAEA00C0AAFF00FF;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y33_N12cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout// ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datad(gnd),.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h000000000000F0F0;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y34_N30cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4]~feeder (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4]~feeder_combout = (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y34_N32dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y33_N27cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~1 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~1_combout = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout ) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~1 .lut_mask = 64'h5F5F5F5F00000000;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y33_N21cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~1_combout ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~1_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h0000000000FF00FF;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y34_N15cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout = (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h55AF55AF50AA50AA;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y34_N17dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y34_N6cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout = (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) ) # (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(gnd),.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h4444BBBB5050FAFA;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y34_N8dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y34_N21cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout = (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]// ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] ) ) ) # (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] $// (((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) ) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] ) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h3333C3333333AAAA;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y34_N54cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5]~feeder (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5]~feeder_combout = (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y34_N56dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y34_N12cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] &// ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h5000500000000000;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y34_N51cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout = (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout// & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .lut_mask = 64'h333A333AC3CAC3CA;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y34_N45cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout = (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout & (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0 .lut_mask = 64'hF0F0F0F000000000;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y34_N2dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y34_N0cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout = (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout// )))) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [5])) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout )) )// ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .lut_mask = 64'h00C0FF3F22E2EE2E;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y33_N36cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) ) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) ) ) ) # (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout & (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout & (// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout &// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout )))) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout// & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) ) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout ),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h7777577777777777;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y33_N38dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y33_N33cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout = ( \u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datad(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .lut_mask = 64'h0000000000030003;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y33_N30cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ))) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout &// (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ))// # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ))) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .lut_mask = 64'h0545054505550555;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y33_N32dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y33_N18cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q// & !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h0A0A0A0A08000800;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y33_N33cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = (!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]) # ((!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] &// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2])).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),.datad(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFFA0FFA0FFA0FFA0;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y33_N35dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";// synopsys translate_on// Location: FF_X27_Y33_N59dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";// synopsys translate_on// Location: FF_X27_Y33_N43dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";// synopsys translate_on// Location: FF_X27_Y33_N32dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y33_N42cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~2 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~2_combout = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] &// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~2 .lut_mask = 64'hC000C00000000000;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y33_N48cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~3 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~3_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~2_combout ) ) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~2_combout ),.datac(gnd),.datad(gnd),.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout ),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~3 .lut_mask = 64'h2222FFFF00000000;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~3 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y33_N45cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~3_combout & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) #// ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~3_combout & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h5050505055005500;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y33_N54cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & (// ((!\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout ) # ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) # (!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]))) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.datab(!\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datad(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hFFFD0000FFFD0000;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X11_Y22_N27cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|rp_valid (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent|rp_valid~combout = ( !\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0] &// ((!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129]~q ))) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent|rp_valid~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent|rp_valid .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent|rp_valid .lut_mask = 64'hAAA0AAA000000000;defparam \u0|mm_interconnect_0|link_disable_s1_agent|rp_valid .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y24_N48cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_009|src1_valid (// Equation(s):// \u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout = ( !\u0|mm_interconnect_0|link_disable_s1_agent|rp_valid~combout & ( !\u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\u0|mm_interconnect_0|link_disable_s1_agent|rp_valid~combout ),.dataf(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|rsp_demux_009|src1_valid .extended_lut = "off";defparam \u0|mm_interconnect_0|rsp_demux_009|src1_valid .lut_mask = 64'hFFFF000000000000;defparam \u0|mm_interconnect_0|rsp_demux_009|src1_valid .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y23_N35dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~21_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";// synopsys translate_on// Location: HPSINTERFACEHPS2FPGA_X32_Y24_N111cyclonev_hps_interface_hps2fpga \u0|hps_0|fpga_interfaces|hps2fpga (.arready(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|cmd_sink_ready~0_combout ),.awready(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~0_combout ),.bvalid(\u0|mm_interconnect_0|rsp_mux|WideOr1~combout ),.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.rlast(\u0|mm_interconnect_0|rsp_mux_001|src_payload [0]),.rvalid(\u0|mm_interconnect_0|rsp_mux_001|WideOr1~combout ),.wready(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),.bid({\u0|mm_interconnect_0|rsp_mux|src_data [116],\u0|mm_interconnect_0|rsp_mux|src_data [115],\u0|mm_interconnect_0|rsp_mux|src_data [114],\u0|mm_interconnect_0|rsp_mux|src_data [113],\u0|mm_interconnect_0|rsp_mux|src_data [112],\u0|mm_interconnect_0|rsp_mux|src_data [111],\u0|mm_interconnect_0|rsp_mux|src_data [110],\u0|mm_interconnect_0|rsp_mux|src_data [109],\u0|mm_interconnect_0|rsp_mux|src_data [108],\u0|mm_interconnect_0|rsp_mux|src_data [107],\u0|mm_interconnect_0|rsp_mux|src_data [106],\u0|mm_interconnect_0|rsp_mux|src_data [105]}),.bresp({gnd,gnd}),.port_size_config({gnd,gnd}),.rdata({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,\u0|mm_interconnect_0|rsp_mux_001|src_payload~33_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_payload~32_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_payload~31_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_payload~30_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_payload~29_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_data[8]~85_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~206_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~210_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~74_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~214_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~222_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~230_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~238_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~29_combout }),.rid({\u0|mm_interconnect_0|rsp_mux_001|src_data [116],\u0|mm_interconnect_0|rsp_mux_001|src_data [115],\u0|mm_interconnect_0|rsp_mux_001|src_data [114],\u0|mm_interconnect_0|rsp_mux_001|src_data [113],\u0|mm_interconnect_0|rsp_mux_001|src_data [112],\u0|mm_interconnect_0|rsp_mux_001|src_data [111],\u0|mm_interconnect_0|rsp_mux_001|src_data [110],\u0|mm_interconnect_0|rsp_mux_001|src_data [109],\u0|mm_interconnect_0|rsp_mux_001|src_data [108],\u0|mm_interconnect_0|rsp_mux_001|src_data [107],\u0|mm_interconnect_0|rsp_mux_001|src_data [106],\u0|mm_interconnect_0|rsp_mux_001|src_data [105]}),.rresp({gnd,gnd}),.arvalid(\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),.awvalid(\u0|hps_0|fpga_interfaces|h2f_AWVALID [0]),.bready(\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),.rready(\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.wlast(\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),.wvalid(\u0|hps_0|fpga_interfaces|h2f_WVALID [0]),.araddr(\u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus ),.arburst(\u0|hps_0|fpga_interfaces|hps2fpga_ARBURST_bus ),.arcache(),.arid(\u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus ),.arlen(\u0|hps_0|fpga_interfaces|hps2fpga_ARLEN_bus ),.arlock(),.arprot(),.arsize(\u0|hps_0|fpga_interfaces|hps2fpga_ARSIZE_bus ),.awaddr(\u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus ),.awburst(\u0|hps_0|fpga_interfaces|hps2fpga_AWBURST_bus ),.awcache(),.awid(\u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus ),.awlen(\u0|hps_0|fpga_interfaces|hps2fpga_AWLEN_bus ),.awlock(),.awprot(),.awsize(\u0|hps_0|fpga_interfaces|hps2fpga_AWSIZE_bus ),.wdata(\u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus ),.wid(),.wstrb(\u0|hps_0|fpga_interfaces|hps2fpga_WSTRB_bus ));// synopsys translate_offdefparam \u0|hps_0|fpga_interfaces|hps2fpga .data_width = 32;// synopsys translate_on// Location: LABCELL_X18_Y23_N24cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[116] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_011|src_data [116] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_ARID [11]) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) ) ) #// ( !\u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & (// \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),.datad(gnd),.datae(!\u0|hps_0|fpga_interfaces|h2f_AWID [11]),.dataf(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [116]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_011|src_data[116] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[116] .lut_mask = 64'h000033330F0F3F3F;defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[116] .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y23_N26dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_011|src_data [116]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y23_N33cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~21 (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~21_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][116]~q & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg// [116] ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][116]~q & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & (// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][116]~q & (// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),.datad(gnd),.datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][116]~q ),.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~21_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~21 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~21 .lut_mask = 64'h00000F0FF0F0FFFF;defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~21 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y18_N41dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_busy (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_busy~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";// synopsys translate_on// Location: FF_X18_Y20_N47dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: FF_X18_Y20_N53dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y20_N51cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~5 (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) #// (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][74]~q ))) ) ) # (// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] &// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] &// ((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][74]~q ))) ) ).dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][74]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h227722770A5F0A5F;defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y18_N23dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~5_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y20_N42cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout = (// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [3]))) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])))) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [3]))) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])))) ) ).dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h54BA54BA10FE10FE;defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y20_N44dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y20_N54cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout = (// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [3]) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) ) ) ) # (// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [3] & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) ) # (// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [3])) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) ) ) # (// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [3])) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h080FF7FF0800F7F0;defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y20_N56dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y20_N24cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [2] & \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ).dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datab(gnd),.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h00A000A000000000;defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y20_N15cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout = (// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout $// (((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))))) #// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) )// ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] $ (((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) #// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ).dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .lut_mask = 64'h44BB44BB74B874B8;defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y20_N59dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y20_N3cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout = (// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6])) #// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [6])) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2]))))) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6])))) #// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6])) #// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))))) ) ) ) # (// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6])) #// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [6])) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2]))))) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6])) #// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [6])) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2]))))) ) ) ).dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datae(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .lut_mask = 64'h37323732C7C23732;defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y20_N8dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";// synopsys translate_on// Location: FF_X18_Y20_N23dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~9_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y20_N21cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~9 (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~9_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6])) #// (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # (// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][78]~q ) ) ).dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][78]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h005500550A5F0A5F;defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y18_N35dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~9_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";// synopsys translate_on// Location: FF_X18_Y20_N50dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y20_N48cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~6 (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #// (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][75]~q ))) ) ) # (// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][75]~q ) ) ).dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][75]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h005500550A5F0A5F;defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y18_N32dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~6_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";// synopsys translate_on// Location: FF_X18_Y20_N20dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~8_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y20_N18cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~8 (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~8_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) #// (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][77]~q ))) ) ) # (// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][77]~q ) ) ).dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datac(gnd),.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][77]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h0055005522772277;defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y18_N27cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~feeder (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~feeder_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~8_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~8_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y18_N29dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";// synopsys translate_on// Location: FF_X18_Y20_N29dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~7_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y20_N27cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~7 (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) #// (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][76]~q ))) ) ) # (// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][76]~q ) ) ).dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datab(gnd),.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][76]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h000F000F505F505F;defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y18_N53dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~7_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y18_N9cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout = ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q &// (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q & !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~q )) ) ).dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ),.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q ),.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0 .lut_mask = 64'h8080808000000000;defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y18_N42cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout &// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout &// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) ) # ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q// $ (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q// $ (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ),.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q ),.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ),.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h4141414155000055;defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y18_N44dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y18_N33cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~0 (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (// (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) ) # (// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) #// (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h3F3F3F3FC0C0C0C0;defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y18_N24cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~0_combout & (// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # (// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~0_combout & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q $ (((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q ) #// (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ))))) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~0_combout & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout// & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q $ (((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q ) #// (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ))))) ) ) ).dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ),.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q ),.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q ),.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ),.datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~0_combout ),.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h0087008700FF0000;defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y18_N26dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y18_N0cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~2 (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h3FC03FC0FF00FF00;defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y18_N21cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~q ) ) # (// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~q $ (((!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q &// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ).dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q ),.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h5AAA5AAAAAAAAAAA;defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y18_N3cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~1_combout & (// (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout &// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~2_combout )) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~1_combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ) # (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~2_combout ))) ) ).dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ),.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h0F0A0F0A05000500;defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y18_N5dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y18_N57cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1 (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) ).dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datab(gnd),.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hA000A00000000000;defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y18_N12cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout &// (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q $ (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout )))) ) ) )// # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout & (// (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q $ (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout )) #// (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q $// (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout )) # (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # (// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout// & (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q $ (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout )))) ) )// ).dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q ),.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout ),.datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h1020132313231020;defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y18_N14dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y18_N36cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout & ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout & (// (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q// ))) # (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6])))) ) ) ) # (// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout & ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout &// (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) ) # (// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout &// (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q & !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ),.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q ),.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout ),.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h0000500000445044;defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y18_N37dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y18_N54cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1 (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) ).dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datac(gnd),.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'h8800880000000000;defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y18_N30cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_busy~q & (// ((!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1_combout ) # (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2])) #// (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]) ) ).dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_busy~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00000000F7F7F7F7;defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y18_N6cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2_combout & \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # (// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q &// (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2_combout & \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout )) ) ).dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2_combout ),.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h00A000A000F000F0;defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y18_N8dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y18_N18cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2 (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_busy~q ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_busy~q ),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h0000000033333333;defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y18_N48cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0 (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0_combout = ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~q & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q & (// (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q & (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_busy~q & (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q &// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ),.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_busy~q ),.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q ),.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q ),.datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~q ),.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h4000000000000000;defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y18_N18cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][66]~q & ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1_combout & (// (!\u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0_combout ) # ((!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2_combout & !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0_combout )) ) ) ) # (// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][66]~q & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1_combout & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0_combout ) #// (!\u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0_combout ) ) ) ).dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2_combout ),.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0_combout ),.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0_combout ),.datad(gnd),.datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][66]~q ),.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h0000FCFC0000F8F8;defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y18_N12cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0 (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0]) #// (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0] ) ).dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hAAAAAAAAFAFAFAFA;defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y23_N56dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~21_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y27_N57cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal20~0 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal20~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & \u0|mm_interconnect_0|router_001|Equal3~0_combout ) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),.datab(gnd),.datac(!\u0|mm_interconnect_0|router_001|Equal3~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal20~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal20~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal20~0 .lut_mask = 64'h0000000005050505;defparam \u0|mm_interconnect_0|router_001|Equal20~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y27_N59dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[14] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|router_001|Equal20~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [14]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[14] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[14] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y27_N42cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src14_valid~1 (// Equation(s):// \u0|mm_interconnect_0|cmd_demux_001|src14_valid~1_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [14] & ( \u0|mm_interconnect_0|router_001|Equal3~0_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] &// (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [19])) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [14] & ( \u0|mm_interconnect_0|router_001|Equal3~0_combout & (// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q & (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [19]))) ) ) ).dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),.datab(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [14]),.dataf(!\u0|mm_interconnect_0|router_001|Equal3~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_demux_001|src14_valid~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_demux_001|src14_valid~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_demux_001|src14_valid~1 .lut_mask = 64'h0000000000020003;defparam \u0|mm_interconnect_0|cmd_demux_001|src14_valid~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y22_N3cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0_combout = ( !\u0|mm_interconnect_0|cmd_demux_001|src14_valid~1_combout & ( !\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_demux_001|src14_valid~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0 .lut_mask = 64'hF0F0F0F000000000;defparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y22_N33cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_payload[0] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_014|src_payload [0] = ( \u0|hps_0|fpga_interfaces|h2f_WLAST [0] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WLAST [0] &// ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),.datac(gnd),.datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_014|src_payload [0]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_014|src_payload[0] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload[0] .lut_mask = 64'h3333333333FF33FF;defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload[0] .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y22_N3cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y22_N5dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y27_N12cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src14_valid~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_demux_001|src14_valid~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) #// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [14]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [14]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_demux_001|src14_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_demux_001|src14_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_demux_001|src14_valid~0 .lut_mask = 64'h00000000F0FFF0FF;defparam \u0|mm_interconnect_0|cmd_demux_001|src14_valid~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y27_N3cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_valid~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout = ( \u0|mm_interconnect_0|cmd_demux_001|src14_valid~0_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] &// (\u0|mm_interconnect_0|router_001|Equal3~0_combout & \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]))) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),.datac(!\u0|mm_interconnect_0|router_001|Equal3~0_combout ),.datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_demux_001|src14_valid~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_014|src_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_014|src_valid~0 .lut_mask = 64'h0000000000010001;defparam \u0|mm_interconnect_0|cmd_mux_014|src_valid~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y23_N54cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout = ( \u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout & ( \u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout & (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout & ( \u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout & (// (!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) # (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout & (// !\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout & (// !\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datad(gnd),.datae(!\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout ),.dataf(!\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .lut_mask = 64'hFFFFF0F0FCFCF0F0;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y19_N51cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[33] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_014|src_data [33] = ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [1] ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [1] & (// \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [1] ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),.dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [33]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_014|src_data[33] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[33] .lut_mask = 64'h0000FFFF5555FFFF;defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[33] .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y20_N15cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y20_N17dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: FF_X22_Y19_N17dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y19_N30cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout & (// !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] &// !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .lut_mask = 64'hA0A0A0A0AAAAAAAA;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y19_N32dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y19_N45cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[35] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_014|src_data [35] = ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]) # (\u0|hps_0|fpga_interfaces|h2f_WSTRB [3]) ) ) # (// !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [3]),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [35]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_014|src_data[35] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[35] .lut_mask = 64'h00FF00FF55FF55FF;defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[35] .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y19_N47dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_014|src_data [35]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y19_N57cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[34] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_014|src_data [34] = ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]) # (\u0|hps_0|fpga_interfaces|h2f_WSTRB [2]) ) ) # (// !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [2]),.datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [34]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_014|src_data[34] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[34] .lut_mask = 64'h00FF00FF0FFF0FFF;defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[34] .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y19_N59dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_014|src_data [34]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y19_N12cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[32] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_014|src_data [32] = ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] ) # ( !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_WSTRB [0] & \u0|mm_interconnect_0|cmd_mux_014|saved_grant// [0]) ) ).dataa(gnd),.datab(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [0]),.datac(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),.datad(gnd),.datae(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [32]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_014|src_data[32] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[32] .lut_mask = 64'h0303FFFF0303FFFF;defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[32] .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y19_N14dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_014|src_data [32]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y19_N42cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~2_combout = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] &// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~2 .lut_mask = 64'hC000C00000000000;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~2 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y19_N3cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y19_N5dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y19_N27cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout &// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0000000088888888;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y19_N12cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write~combout = (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout &// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout )).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write .lut_mask = 64'h0C000C000C000C00;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y19_N30cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write~combout & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q &// ((\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0]) # (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1]))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write~combout & (// (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q & (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0_combout & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter// [0]) # (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1])))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1]),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0]),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~0 .lut_mask = 64'h000D000D07070707;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y19_N42cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~1_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~0_combout & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter// [0] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~1 .lut_mask = 64'h00000000FF00FF00;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y19_N44dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[0] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y19_N33cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~2_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~0_combout & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter// [0] $ (!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0]),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~2 .lut_mask = 64'h000000000FF00FF0;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y19_N35dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[1] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y19_N57cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0 .lut_mask = 64'h00FF00FF00000000;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y20_N36cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[88] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_014|src_data [88] = ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( ((\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0])) # (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]) ) ) # (// !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),.datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [88]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_014|src_data[88] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[88] .lut_mask = 64'h111111111F1F1F1F;defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[88] .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y20_N27cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[87] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_014|src_data [87] = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1])) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) ) ) # (// !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),.datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),.datad(gnd),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [87]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_014|src_data[87] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[87] .lut_mask = 64'h0303030357575757;defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[87] .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y19_N39cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_014|src_data [88] & ( !\u0|mm_interconnect_0|cmd_mux_014|src_data [87] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\u0|mm_interconnect_0|cmd_mux_014|src_data [88]),.dataf(!\u0|mm_interconnect_0|cmd_mux_014|src_data [87]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFFFF000000000000;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y19_N41dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y19_N0cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~3 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~3_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~2_combout &// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout & (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout ))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~2_combout &// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ) # ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout &// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout )))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~2_combout &// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout & (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout ))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~2_combout &// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ) # ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout &// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout )))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~2_combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~3 .lut_mask = 64'h5703570375307530;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~3 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y19_N15cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~3_combout & (// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~3_combout & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q &// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h00AA00AA00CA00CA;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y19_N36cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout &// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ))) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & (// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout &// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout// )) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout// & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout// )))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout// & (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout// )))) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h0111455500114455;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y19_N38dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";// synopsys translate_on// Location: FF_X25_Y22_N35dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_014|src_payload [0]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y19_N12cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1_combout &// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1_combout &// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1_combout &// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1_combout &// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h00530053FF53FF53;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y19_N57cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) # (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout )// ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'hFF00FF00FFF0FFF0;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y19_N59dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";// synopsys translate_on// Location: FF_X27_Y19_N56dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";// synopsys translate_on// Location: FF_X27_Y19_N17dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y19_N54cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & (// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0 .lut_mask = 64'h000F000F0F0F0F0F;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y19_N48cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4_combout & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4_combout & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout & (// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout & (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout )))) ) ) ) # (// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4_combout & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4_combout & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout & (// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout & (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4_combout ),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h04040C0C04440CCC;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y19_N8dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y19_N6cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][129]~q & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout & (// (((\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout & \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout )) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout )) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][129]~q & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &// (((\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout & \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout )) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][129]~q & (// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout & ( ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout & \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout )) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][129]~q & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout & (// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout & (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][129]~q ),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h0404373704CC37FF;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y19_N53dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y19_N51cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~3 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][66]~q & (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][66]~q & (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] ) ) ) # (// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][66]~q & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & (// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][66]~q ),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h00005555AAAAFFFF;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y19_N33cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~feeder (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~feeder_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~3_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y19_N35dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";// synopsys translate_on// Location: FF_X21_Y19_N23dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][68] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][68]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][68] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][68] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y19_N21cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~2_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][68]~q & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] ) ) # (// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][68]~q & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][68]~q & (// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),.datad(gnd),.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][68]~q ),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h0F0F0F0F0000FFFF;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y19_N59dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][68] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~2_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][68]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][68] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][68] .power_up = "low";// synopsys translate_on// Location: FF_X21_Y19_N14dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][69] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][69]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][69] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][69] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y19_N12cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][69]~q & (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][69]~q & (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] ) ) ) # (// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][69]~q & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & (// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),.datad(gnd),.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][69]~q ),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h00000F0FF0F0FFFF;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y19_N24cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69]~feeder (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69]~feeder_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~1_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y19_N26dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y19_N39cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_014|src0_valid~0 (// Equation(s):// \u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][68]~q & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69]~q & (// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~q ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~q ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][68]~q ),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|rsp_demux_014|src0_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|rsp_demux_014|src0_valid~0 .lut_mask = 64'h0000AAAA00000000;defparam \u0|mm_interconnect_0|rsp_demux_014|src0_valid~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y18_N0cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_014|WideOr0~0 (// Equation(s):// \u0|mm_interconnect_0|rsp_demux_014|WideOr0~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_BREADY [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0]) # (\u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_BREADY// [0] & ( (!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout & \u0|hps_0|fpga_interfaces|h2f_RREADY [0]) ) ).dataa(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout ),.datab(gnd),.datac(gnd),.datad(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|rsp_demux_014|WideOr0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|rsp_demux_014|WideOr0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|rsp_demux_014|WideOr0~0 .lut_mask = 64'h00AA00AA55FF55FF;defparam \u0|mm_interconnect_0|rsp_demux_014|WideOr0~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y18_N48cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout & ( \u0|mm_interconnect_0|rsp_demux_014|WideOr0~0_combout ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|rsp_demux_014|WideOr0~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0 .lut_mask = 64'h000000000F0F0F0F;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y18_N33cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0]~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout ) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0] &// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout )))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout )// ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h51FF51FF55FF55FF;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y18_N35dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y18_N6cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]) #// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0] )// ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hF0F0F0F0FFF0FFF0;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y18_N41dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y18_N24cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0] ) ) # (// !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q ) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]),.datad(gnd),.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0 .lut_mask = 64'h07070F0F07070F0F;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y19_N50dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y19_N48cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~5 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &// (((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &// (((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][74]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h083B083B4C7F4C7F;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y18_N2dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~5_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y19_N57cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout = (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2]))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2]))) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datac(gnd),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h0000FFFFDD887722;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y19_N59dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y19_N24cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout = (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] &// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])))) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h0000FFFFD85072FA;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y19_N26dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";// synopsys translate_on// Location: FF_X22_Y19_N2dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~7_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y19_N0cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~7 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][76]~q ) ) # (// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][76]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h0505050500FF00FF;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y18_N5dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~7_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";// synopsys translate_on// Location: FF_X22_Y19_N53dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y19_N51cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~6 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][75]~q ) ) # (// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][75]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h0505050500FF00FF;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y18_N14dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~6_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y18_N42cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q )) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q & (// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q )) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q )) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q & (// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q )) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ),.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h00D8008D00720027;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y18_N44dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y18_N15cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [4] $ (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h5A5A5A5AAAAAAAAA;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y18_N0cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q & (// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q )) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout// & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q $// ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q )))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~0_combout )))) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q ),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~0_combout ),.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q ),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h000000009F905F50;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y18_N38dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y16_N15cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [4] &// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datad(gnd),.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hC0C0000000000000;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y19_N33cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] &// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h00000000A000A000;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y19_N42cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout = (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ))// # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout )) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .lut_mask = 64'h27222722DDD8DDD8;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y19_N29dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y19_N6cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout = (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout// )))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )))) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout// )))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )))) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .lut_mask = 64'h303ACFCA000AFFFA;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y19_N8dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";// synopsys translate_on// Location: FF_X22_Y19_N5dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~9_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y19_N3cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~9 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~9_combout = (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &// (((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][78]~q )))).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][78]~q ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h0437043704370437;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y18_N17dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~9_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";// synopsys translate_on// Location: FF_X22_Y19_N32dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~8_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y19_N30cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~8 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~8_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][77]~q ))) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][77]~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][77]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h003300330C3F0C3F;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y18_N35dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~8_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y18_N12cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0_combout = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77]~q & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q &// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q & !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q )) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hC000C00000000000;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y18_N24cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0_combout & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78]~q ))) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1_combout )))) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0_combout & (// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78]~q ))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1_combout )))) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0_combout & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78]~q ))) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1_combout )))) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0_combout & (// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78]~q ))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1_combout )))) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1_combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78]~q ),.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0131023231013202;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y18_N26dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y18_N6cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [6] &// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1_combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0_combout & !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78]~q ) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78]~q ),.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h000000000F002222;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y18_N7dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";// synopsys translate_on// Location: FF_X23_Y18_N11dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_busy (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_busy~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y18_N54cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_busy~q & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1_combout ) # ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [7]) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_busy~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00000000CFFFCFFF;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y18_N21cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2_combout = (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_busy~q &// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2]).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_busy~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h000F000F000F000F;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y18_N51cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2_combout & (// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q ) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h0A0F0A0F00000000;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y18_N53dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y16_N27cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~2_combout = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datad(gnd),.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h3F3FFFFFC0C00000;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y18_N48cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77]~q & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q &// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q & !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q )) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77]~q & (// ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q ) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q )) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q ),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h7F7F7F7F80808080;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y18_N21cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~2_combout ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout &// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~1_combout ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~2_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~1_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h3300330030303030;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y18_N50dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y18_N57cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [4])) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hA000A00000000000;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y18_N30cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~0_combout = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_busy~q// & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77]~q & (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78]~q & (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q &// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77]~q ),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78]~q ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q ),.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q ),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_busy~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0800000000000000;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y18_N18cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout &// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~0_combout & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~q &// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout ) # ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1_combout ) # (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2_combout// )))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00FE00FE00AA00AA;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y18_N18cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[1]~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout &// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout &// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout// & (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0])))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout &// ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout & (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0])) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[1]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h05AF05AF01670167;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y18_N20dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[1]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y19_N24cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &// (((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout & \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout )) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ))) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout &// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout )) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1 .lut_mask = 64'h444C444C44C444C4;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y19_N30cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1_combout ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h0000000000FF00FF;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y19_N15cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout = (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h00FF00FFFA50FA50;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y19_N12cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout = (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout &// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .lut_mask = 64'hC0C0C0C000000000;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y19_N33cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout &// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout &// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h0010001030303030;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y19_N18cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & (// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h000000000F000F00;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y19_N21cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) # (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout &// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ) #// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout )))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h00BF00BFFFFFFFFF;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y19_N23dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y19_N15cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h000000005F005F00;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y23_N24cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout & (// \u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout & ( \u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout// & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] &// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )))) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout & ( !\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout// & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout// ) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),.datae(!\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout ),.dataf(!\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000070700070707;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y19_N53dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_014|src_data [33]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y19_N9cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] &// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ) #// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )))) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0 .lut_mask = 64'hA080000000000000;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y19_N18cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & (// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0] &// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout ))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & (// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0] &// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout ))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0]),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout ),.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hF5F7F0F0F5FDF0F0;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y19_N18cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) #// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # (((!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1])) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ))) ) ) # ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q &// ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) #// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout// ))))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.datag(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 .extended_lut = "on";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 .lut_mask = 64'hFEEEAAAAFFFFABAB;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y19_N3cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .lut_mask = 64'hFFFFFFFF00000000;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y19_N5dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y19_N24cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout = (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q &// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q $// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ))) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q &// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .lut_mask = 64'hA50AA50A0A000A00;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y19_N45cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout = (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .lut_mask = 64'hFF00FF0000000000;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y19_N6cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout// & ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] &// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) # (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout )))) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) # (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] &// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .lut_mask = 64'h0000303055557775;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y19_N27cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & (// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout &// !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),.datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .lut_mask = 64'h0300030000000000;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y19_N54cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout = (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout &// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout )) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h04040404040C040C;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y19_N45cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout// & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h0505050500000000;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y19_N36cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout & (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ) ) # (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout & (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout & (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout & (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ) ) # (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout & (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout & (// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout &// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout &// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .lut_mask = 64'h5575FFFF5555FFFF;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y19_N38dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y19_N48cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = ( !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( (((!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] &// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ))))) ) ) # ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) # (((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q &// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datae(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datag(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "on";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h0000F1F3F0F0FFFF;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y22_N20dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y27_N0cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0 (// Equation(s):// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_AWLEN [1] & ( \u0|hps_0|fpga_interfaces|h2f_AWLEN [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWLEN [2] ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [2]),.datad(gnd),.datae(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [1]),.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0 .lut_mask = 64'h0000000000000F0F;defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y27_N24cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~2 (// Equation(s):// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~2_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout ) ) # (// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout $ (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout ),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~2 .lut_mask = 64'h0FF00FF000FF00FF;defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y27_N25dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y27_N27cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2 (// Equation(s):// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout = ( \u0|hps_0|fpga_interfaces|h2f_AWLEN [0] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (!\u0|hps_0|fpga_interfaces|h2f_AWLEN [2] $// ((!\u0|hps_0|fpga_interfaces|h2f_AWLEN [1])))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [4])))) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWLEN [0] & (// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWLEN [2])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [4]))) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [2]),.datab(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [1]),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [4]),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2 .lut_mask = 64'h550F550F660F660F;defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y27_N48cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~1 (// Equation(s):// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~1_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout ) ) # (// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout $ (((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout ) #// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout ))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout ),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout ),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~1 .lut_mask = 64'h3C0F3C0F0F0F0F0F;defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y27_N50dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y27_N54cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1 (// Equation(s):// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [5] & (// (!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3]) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount// [5] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ) # (\u0|hps_0|fpga_interfaces|h2f_AWLEN [3]) ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0_combout & (// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [5] & ( (!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ) ) ) ) # (// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [5] & ( (\u0|hps_0|fpga_interfaces|h2f_AWLEN [3] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ) ) )// ).dataa(gnd),.datab(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3]),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),.datad(gnd),.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0_combout ),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1 .lut_mask = 64'h3030C0C03F3FCFCF;defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y20_N3cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5_combout = ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]) #// ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout & \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & (// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout & \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout ),.datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5 .lut_mask = 64'h00F000F0AAFAAAFA;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y20_N51cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6_combout = (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5_combout ) ) # (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6 .lut_mask = 64'h0FF00FF055555555;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y20_N53dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y20_N12cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout = ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & (// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout & \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ) ) ) # (// !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout & \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) ) ).dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout ),.datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0 .lut_mask = 64'h000F000F555F555F;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y20_N24cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout = (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout & (// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q// ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout & (// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) ) # (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg// [2] & \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 .lut_mask = 64'h00A0AA0A55F5FF5F;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y20_N26dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y20_N48cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] &// ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) ) # (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $// (((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hCF30CF30FF00FF00;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y20_N36cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & (// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout )))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]))) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & (// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0])) ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ))) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1])) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & (// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout &// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),.datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .lut_mask = 64'hF000F055F033F077;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y20_N38dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y20_N45cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] )// # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4])) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'hF5FFF5FFFFFFFFFF;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y22_N18cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout = (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg// [5] $ ((((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout )))) ) ) # (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( ((!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & (((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] &// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout )))) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & (((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] &// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout )) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout )))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),.datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout ),.datag(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7 .extended_lut = "on";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7 .lut_mask = 64'hA5A50303A5A503FF;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y22_N56dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y22_N9cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout & (// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )) #// (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]))) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] &// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),.datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2 .lut_mask = 64'h0003000300570057;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y22_N54cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout = (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout ) # (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg// [6] $ (((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ))))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3 .lut_mask = 64'h802A802AFFFFFFFF;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y20_N0cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0_combout = (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6_combout & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout &// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout &// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout )) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0 .lut_mask = 64'h00000000C000C000;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y19_N42cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout// & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0_combout &// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout & ( ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout// ) # ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0_combout &// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ))) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'hDFDDDFDD0F000F00;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y19_N44dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y19_N36cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout = (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) ) # (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) #// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1_combout ))))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1_combout ),.datag(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .extended_lut = "on";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .lut_mask = 64'h0C00F0F00C00F5F5;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y22_N45cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout = (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'hF0F0F0F000000000;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y22_N0cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~0 .lut_mask = 64'hFFFFFFFF00000000;defparam \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y22_N2dffeas \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y22_N48cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|update_grant~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout = ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_014|src_payload [0] &// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout & (// (\u0|mm_interconnect_0|cmd_mux_014|src_payload [0] & !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & (// !\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout & ( (!\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout & (((!\u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~q )))) # (\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout &// (\u0|mm_interconnect_0|cmd_mux_014|src_payload [0] & (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & (// !\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout & ( !\u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~q ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_014|src_payload [0]),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.datac(!\u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~q ),.datad(!\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout ),.datae(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),.dataf(!\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_014|update_grant~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_014|update_grant~0 .lut_mask = 64'hF0F0F04444444444;defparam \u0|mm_interconnect_0|cmd_mux_014|update_grant~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y22_N0cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~2 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~2_combout = ( \u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0_combout &// (!\u0|mm_interconnect_0|cmd_mux_014|arb|grant[1]~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0_combout & ((\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [0]))) ) ) # (// !\u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout & ( \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [0] ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_014|arb|grant[1]~0_combout ),.datad(!\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~2 .lut_mask = 64'h00FF00FFA0F5A0F5;defparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y22_N2dffeas \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y22_N54cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~1 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~1_combout = ( \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [1] & ( \u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout & (// (\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0_combout ) # (\u0|mm_interconnect_0|cmd_mux_014|arb|grant[0]~1_combout ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [1] & (// \u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_014|arb|grant[0]~1_combout & !\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0_combout ) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg// [1] & ( !\u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_014|arb|grant[0]~1_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0_combout ),.datad(gnd),.datae(!\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [1]),.dataf(!\u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~1 .lut_mask = 64'h0000FFFF50505F5F;defparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y22_N56dffeas \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y22_N48cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|arb|grant[1]~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_014|arb|grant[1]~0_combout = ( \u0|mm_interconnect_0|cmd_demux_001|src14_valid~1_combout & ( ((!\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout & !\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [0])) #// (\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [1]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout ),.datac(!\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [0]),.datad(!\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_demux_001|src14_valid~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_014|arb|grant[1]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_014|arb|grant[1]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_014|arb|grant[1]~0 .lut_mask = 64'h00000000C0FFC0FF;defparam \u0|mm_interconnect_0|cmd_mux_014|arb|grant[1]~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y22_N42cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|saved_grant[1]~feeder (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_014|saved_grant[1]~feeder_combout = ( \u0|mm_interconnect_0|cmd_mux_014|arb|grant[1]~0_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_014|arb|grant[1]~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_014|saved_grant[1]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_014|saved_grant[1]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_014|saved_grant[1]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \u0|mm_interconnect_0|cmd_mux_014|saved_grant[1]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y22_N44dffeas \u0|mm_interconnect_0|cmd_mux_014|saved_grant[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_014|saved_grant[1]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_014|saved_grant[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|cmd_mux_014|saved_grant[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y23_N42cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[116] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_014|src_data [116] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [11])) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) ) ) # (// !\u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [11]) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),.datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),.datac(gnd),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [11]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [116]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_014|src_data[116] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[116] .lut_mask = 64'h0055005533773377;defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[116] .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y23_N44dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_014|src_data [116]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";// synopsys translate_on// Location: FF_X23_Y23_N17dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~21_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y23_N15cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~21 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~21_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][116]~q ) ) # (// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][116]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~21_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~21 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~21 .lut_mask = 64'h0F0F0F0F00FF00FF;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~21 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y23_N26dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~21_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y18_N51cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid~combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0] &// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q & !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0])) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0] & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0] & !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q ),.datac(gnd),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid .lut_mask = 64'hAA00AA0088008800;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y18_N3cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_014|src1_valid (// Equation(s):// \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid~combout & ( !\u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout ) ).dataa(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|rsp_demux_014|src1_valid .extended_lut = "off";defparam \u0|mm_interconnect_0|rsp_demux_014|src1_valid .lut_mask = 64'hAAAAAAAA00000000;defparam \u0|mm_interconnect_0|rsp_demux_014|src1_valid .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y23_N24cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~201 (// Equation(s):// \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~201_combout = ( \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout & ( ((\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout & \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][116]~q )) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][116]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout & ( (\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout &// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][116]~q ) ) ).dataa(!\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][116]~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][116]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~201_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~201 .extended_lut = "off";defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~201 .lut_mask = 64'h0505050505FF05FF;defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~201 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y24_N15cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[116] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_010|src_data [116] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( ((\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [11])) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]) ) ) # (// !\u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [11]) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),.datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),.datac(gnd),.datad(!\u0|hps_0|fpga_interfaces|h2f_AWID [11]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [116]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_010|src_data[116] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[116] .lut_mask = 64'h0055005533773377;defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[116] .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y24_N17dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_010|src_data [116]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";// synopsys translate_on// Location: FF_X22_Y24_N26dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~21_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y24_N24cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~21 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~21_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][116]~q ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.datac(gnd),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][116]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~21_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~21 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~21 .lut_mask = 64'h3333333300FF00FF;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~21 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y24_N26dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~21_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y24_N18cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[116] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_009|src_data [116] = ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( ((\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [11])) # (\u0|hps_0|fpga_interfaces|h2f_ARID [11]) ) ) # (// !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [11]) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),.datab(!\u0|hps_0|fpga_interfaces|h2f_AWID [11]),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [116]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_009|src_data[116] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[116] .lut_mask = 64'h111111111F1F1F1F;defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[116] .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y24_N20dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_009|src_data [116]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";// synopsys translate_on// Location: FF_X17_Y24_N2dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~21_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y24_N0cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~21 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~21_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][116]~q & ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] ) ) # (// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][116]~q & ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg// [116] ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][116]~q & ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & (// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.datad(gnd),.datae(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][116]~q ),.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~21_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~21 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~21 .lut_mask = 64'h0F0F0F0F0000FFFF;defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~21 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y24_N38dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~21_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y24_N45cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~200 (// Equation(s):// \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~200_combout = ( \u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout & ( ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][116]~q &// \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout )) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout & (// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][116]~q & \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][116]~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116]~q ),.datae(!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~200_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~200 .extended_lut = "off";defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~200 .lut_mask = 64'h050505FF050505FF;defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~200 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y33_N3cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y33_N5dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y33_N0cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~q & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0_combout &// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout & \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [0])) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0_combout ),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [0]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0000000004040404;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y33_N2dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg[0] .power_up = "low";// synopsys translate_on// Location: FF_X30_Y33_N38dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y33_N36cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~1 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout &// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0_combout )) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][129]~q ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout & \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0_combout ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0_combout ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][129]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h0303030303FF03FF;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y34_N38dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y34_N36cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][77]~q & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] ) ) # (// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][77]~q & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] &// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][77]~q & (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] &// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(gnd),.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][77]~q ),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h030303030000FFFF;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y34_N5dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";// synopsys translate_on// Location: FF_X27_Y34_N8dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y34_N9cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ) ) ) ) # ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] &// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] &// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ))) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] &// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] &// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ),.datad(gnd),.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h474747470303CFCF;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y34_N53dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";// synopsys translate_on// Location: FF_X27_Y34_N14dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y34_N12cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][75]~q & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][75]~q & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ) ) # (// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][75]~q & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(gnd),.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][75]~q ),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h000033330C0C3F3F;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y34_N38dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";// synopsys translate_on// Location: FF_X30_Y34_N35dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";// synopsys translate_on// Location: FF_X27_Y34_N59dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y34_N57cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][78]~q & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][78]~q & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # (// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][78]~q & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] ) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datad(gnd),.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][78]~q ),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h00000F0F50505F5F;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y34_N2dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";// synopsys translate_on// Location: FF_X27_Y34_N35dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y34_N33cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][76]~q & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][76]~q & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # (// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][76]~q & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] ) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datad(gnd),.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][76]~q ),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h00000F0F50505F5F;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y34_N11dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y34_N0cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q & (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q &// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ),.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h2000000000000000;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y34_N15cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q &// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q )) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hC000C00000000000;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y34_N48cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h0000000000FF00FF;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y34_N12cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout &// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h5050505000500050;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y34_N14dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y34_N24cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ))) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ))) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ))) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ))) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h5404510104540151;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y34_N26dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y34_N18cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h3FC03FC0FF00FF00;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y34_N51cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q $ (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q &// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h5AAA5AAAAAAAAAAA;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y34_N21cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1_combout & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2_combout & (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout &// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1_combout & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2_combout ) #// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h0F0A0F0A000A000A;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y34_N23dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y34_N39cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5] &// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hC000C00000000000;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y34_N42cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q $ (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout )))) ) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q $ (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout )) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q $// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout )) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout &// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q $ (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout )))) ) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout ),.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0220133113310220;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y34_N44dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y34_N30cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] &// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q & (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout &// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout )) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q & (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout &// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout ),.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h000A0000000A0C0C;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y34_N31dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y34_N36cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [7]))) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h0F0F0F0F07070707;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y34_N9cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4] $ (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h5A5A5A5AAAAAAAAA;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y34_N54cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q )) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0_combout ))))) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q )) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0_combout ))))) ) ) ) # ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q )) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0_combout ))))) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q )) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0_combout ))))) ) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0_combout ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h00D8007200720072;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y34_N56dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y34_N6cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hA000A00000000000;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y33_N56dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y33_N54cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][66]~q ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][66]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h0F0F0F0F00FF00FF;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y33_N50dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y33_N30cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~q & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout ) #// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ) #// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout )))) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout ),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00000000EEEAEEEA;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y33_N15cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0] ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hCFCFCFCFCCCCCCCC;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y33_N53dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~1_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y33_N42cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] &// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0])))) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]))) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),.datab(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h1133113310301030;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X31_Y15_N30cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1]~1 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1]~1_combout = (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout & (((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] &// \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1]))).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout ),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h0A2A0A2A0A2A0A2A;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X31_Y15_N20dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y33_N45cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0]~0 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] &// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout & (// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1])) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h50FF50FF0F5F0F5F;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y33_N47dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y33_N18cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0] & ( ((\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q )) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0 .lut_mask = 64'h000000003FFF3FFF;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y35_N18cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout & ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] ) ).dataa(gnd),.datab(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datac(gnd),.datad(gnd),.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout ),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0 .lut_mask = 64'h0000333300003333;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y33_N6cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0]~1 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0_combout ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0] &// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout )))) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0_combout ) )// ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0_combout ),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h55DF55DF55FF55FF;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y33_N8dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y33_N12cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0] &// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0])) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid .lut_mask = 64'hF000F000C000C000;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y34_N36cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y34_N38dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: FF_X23_Y35_N8dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y35_N30cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout &// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h0000000044444444;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y35_N57cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y35_N59dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y35_N15cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y35_N17dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y35_N42cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~q & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout & !\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter [0])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~0 .lut_mask = 64'h0000000030003000;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y35_N44dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y35_N51cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter [0] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~q ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0 .lut_mask = 64'h000000000F0F0F0F;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y35_N15cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1 .lut_mask = 64'h00AA00AAAAAAAAAA;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y35_N33cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1_combout &// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1_combout ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h000F000F000F000F;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y35_N6cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout = (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout $// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(gnd),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h33CC33CC22EE22EE;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y35_N8dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y35_N27cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout = (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] $// (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h30CF30CF22EE22EE;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y35_N29dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y35_N51cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout = (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2]) # (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) ) ) # (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2] & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) ) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h30002222CFFFEEEE;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y35_N50dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y35_N18cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] &// ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] &// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h3000300000000000;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y35_N21cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout = (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] $ (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) )// ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .lut_mask = 64'h0FF00FF02E2E2E2E;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y35_N59dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";// synopsys translate_on// Location: FF_X25_Y35_N55dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y35_N54cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout = (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2]) # (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]// & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ) ) ) # (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout &// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .lut_mask = 64'h0F00F0FF2222EEEE;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y35_N9cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout = (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0 .lut_mask = 64'hF0F0F0F000000000;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y35_N36cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) ) ) # (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout & (// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout &// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout ))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) ) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout ),.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h3373333333333333;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y35_N38dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y35_N33cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout = ( \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout & (// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datad(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .lut_mask = 64'h0000000000030003;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y35_N57cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hFFFFFFFF00000000;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y35_N38dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y35_N9cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q// & \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q// & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]))) ) ) ) # ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h0F0F0F0F44550055;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y35_N12cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1_combout & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ))) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1_combout & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .lut_mask = 64'hCCCCCCCCCCC0CCC0;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y35_N30cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & (// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )// # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout )))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout )// ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .lut_mask = 64'h0000000055DF55DF;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y35_N32dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y35_N48cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q $// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .lut_mask = 64'hC000C0003CC03CC0;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y35_N48cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ) ) # (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout &// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )) ) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'hFF080808FF0F0F0F;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y35_N24cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & (// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout// ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h000000000F000F00;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y35_N33cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q// & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout &// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h0000000044444444;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y35_N12cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout = (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout & (// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout & (// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) ) ) # (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout & (// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout & (// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout ) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout )))) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) ) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h45FF55FF55FF55FF;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y35_N14dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y35_N12cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ) #// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h00000000C888C888;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y34_N45cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( !\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] ) ) # (// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( (!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]) # (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),.datac(gnd),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFFCCFFCCCCCCCCCC;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y34_N47dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";// synopsys translate_on// Location: FF_X23_Y35_N23dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";// synopsys translate_on// Location: FF_X23_Y35_N32dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";// synopsys translate_on// Location: FF_X23_Y35_N41dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y35_N30cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~2 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~2_combout = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] &// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1])) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~2 .lut_mask = 64'hA000A00000000000;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y35_N18cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~3 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~3_combout = (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] &// (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~2_combout )) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ))).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~2_combout ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~3 .lut_mask = 64'h22A222A222A222A2;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~3 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y35_N3cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~3_combout & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) #// ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~3_combout & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h0F000F000A0A0A0A;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y35_N39cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (// \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & ((!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q// & ( \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ) ) # (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & ( !\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// ( !\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.dataf(!\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hFF00FF00FF00AF00;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y35_N15cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h000000003F303F30;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y35_N17dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y35_N51cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = ( \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout )))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// (((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout// )) # (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h0033003305370537;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y35_N53dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y35_N21cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]) # (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) #// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout )) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFF0AFF0AFFAAFFAA;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y35_N5dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y35_N54cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout = ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .lut_mask = 64'h30C030C03ACA3ACA;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y35_N56dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y35_N42cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout = (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )// # ((\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout )) ) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout )) ) ) ) # ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg// [3] & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ))) ) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q// & (((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ))) ) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .lut_mask = 64'h01ABAB010101ABAB;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y35_N44dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y35_N27cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $// (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2]))) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hA6A6A6A6AAAAAAAA;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y35_N3cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout = (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),.datac(gnd),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .lut_mask = 64'hAABBAABB00110011;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y35_N24cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] &// ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2] & !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h0C000C0000000000;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y35_N0cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout = (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ))) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ))) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .lut_mask = 64'h01AB01ABAB01AB01;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y35_N1dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";// synopsys translate_on// Location: FF_X22_Y35_N8dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y35_N6cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout = (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q// & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (// \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout// )))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )) ) ) ) # (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( !\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) ) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( !\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]// & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),.dataf(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .lut_mask = 64'h00A0AA0A11B1BB1B;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y35_N18cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) # (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout &// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ))) ) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h00008000FFFFFFFF;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y35_N20dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y35_N54cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout = (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ) #// ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ))))// ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'h7430743030303030;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y35_N24cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout// & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1_combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// (((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )))) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout )))) ) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1_combout & (// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q// ) ) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .lut_mask = 64'h3F3F00002E0C0000;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y35_N0cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & (// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout &// \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout )) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),.datad(!\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000000000300030;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y35_N5dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y35_N45cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q )))) ) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0 .lut_mask = 64'h8880000000000000;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y35_N30cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout & \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h000F000F0F0F0F0F;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y35_N41dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y35_N39cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~1 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout & ( ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][129]~q )) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout & (// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][129]~q ) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][129]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h005500550F5F0F5F;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y35_N54cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]) #// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0] ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hAAAAAAAAFAFAFAFA;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y35_N11dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~1_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y35_N6cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0] & ( ((\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0 .lut_mask = 64'h000000003FFF3FFF;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y35_N24cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout & ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0 .lut_mask = 64'h000000000F0F0F0F;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y35_N23dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";// synopsys translate_on// Location: FF_X25_Y35_N2dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y35_N0cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][76]~q ))) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][76]~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][76]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h003300330C3F0C3F;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y35_N29dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";// synopsys translate_on// Location: FF_X25_Y35_N47dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y35_N45cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][75]~q ))) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][75]~q ) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][75]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h005500550A5F0A5F;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y35_N56dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";// synopsys translate_on// Location: FF_X25_Y35_N5dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y35_N3cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][77]~q ))) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][77]~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][77]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h003300330C3F0C3F;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y35_N59dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";// synopsys translate_on// Location: FF_X25_Y35_N44dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y35_N42cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ))) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] &// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] &// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ))) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h0A5F0A5F22772277;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y35_N5dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";// synopsys translate_on// Location: FF_X30_Y35_N11dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y35_N9cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][78]~q & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][78]~q & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]) ) ) ) # (// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][78]~q & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.datad(gnd),.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][78]~q ),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h000033330C0C3F3F;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y35_N35dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y35_N30cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q &// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ),.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0000800000000000;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y35_N42cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout &// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout &// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) ) # ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q $ (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &// ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q $ (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h2121212133000033;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y35_N44dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y35_N9cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77]~q & !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q )) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hA000A00000000000;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y35_N54cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2] $ (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h66666666CCCCCCCC;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y35_N12cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q )) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0_combout )))) ) ) ) # ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q// & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q// )))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0_combout )))) ) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0_combout ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h0000A0CC00005FCC;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y35_N14dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y35_N36cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~2 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4] &// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h3CF03CF0F0F0F0F0;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y35_N3cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77]~q $ (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q &// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h5AF05AF0F0F0F0F0;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y35_N39cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~2_combout & \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout &// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~1_combout ) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~2_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~1_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h0F000F000A0A0A0A;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y35_N41dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y35_N57cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4] &// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1 .lut_mask = 64'h8080808000000000;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y35_N48cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q $ (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout// )))) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout & (// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q $ (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout )) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q $// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout )) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout & (// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q $ (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout )))) ) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout ),.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h1020132313231020;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y35_N50dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y35_N0cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] &// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hC000C00000000000;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y35_N18cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q// & (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout ))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6])))) ) ) ) # ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q & (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout &// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h00002200000022F0;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y35_N20dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y35_N27cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [7] & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [7] & (// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h5151515155555555;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y35_N6cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q &// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout )) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h2020202030303030;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y35_N8dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y35_N24cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h0000000000FF00FF;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y35_N47dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";// synopsys translate_on// Location: FF_X27_Y35_N13dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~2_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y35_N9cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~2 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~2_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][66]~q ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][66]~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h555555550F0F0F0F;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y35_N50dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~2_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y35_N48cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout &// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][66]~q & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ) # (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout// )))) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][66]~q ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][66]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00FF00FF00A800A8;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y35_N36cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1]~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout &// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout )))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout &// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout & (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1])) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout &// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]))))) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout &// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1])) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]))) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h4747474711471147;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y35_N38dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y35_N33cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0]~1 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout & ( ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0] &// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout ) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h33FF33FF337F337F;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y35_N35dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y35_N57cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] &// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ))) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid .lut_mask = 64'hFA00FA0000000000;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y34_N26dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y32_N33cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~11 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_021|src_payload~11_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~11 .lut_mask = 64'h0000000055555555;defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y32_N34dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_021|src_payload~11_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y34_N24cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][116]~q & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][116]~q & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] ) ) ) # (// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][116]~q & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datac(gnd),.datad(gnd),.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][116]~q ),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h00003333CCCCFFFF;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y34_N3cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~feeder (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~feeder_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y34_N5dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";// synopsys translate_on// Location: FF_X21_Y32_N41dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y32_N6cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~11 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_020|src_payload~11_combout = ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~11 .lut_mask = 64'h000000000F0F0F0F;defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y32_N25dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_020|src_payload~11_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y32_N39cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][116]~q ) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][116]~q ) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][116]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h00550055AAFFAAFF;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y32_N47dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y31_N6cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal14~0 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal14~0_combout = (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [18])).dataa(gnd),.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal14~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal14~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal14~0 .lut_mask = 64'h0C000C000C000C00;defparam \u0|mm_interconnect_0|router_001|Equal14~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y31_N51cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal14~1 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal14~1_combout = ( \u0|mm_interconnect_0|router_001|Equal1~1_combout & ( (\u0|mm_interconnect_0|router_001|Equal1~0_combout & (\u0|mm_interconnect_0|router_001|Equal1~2_combout &// (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & \u0|mm_interconnect_0|router_001|Equal14~0_combout ))) ) ).dataa(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),.datab(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),.datad(!\u0|mm_interconnect_0|router_001|Equal14~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal14~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal14~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal14~1 .lut_mask = 64'h0000000000100010;defparam \u0|mm_interconnect_0|router_001|Equal14~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y31_N53dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[8] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|router_001|Equal14~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [8]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[8] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[8] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y31_N15cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src8_valid~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [8] & ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel// [8] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q & \u0|hps_0|fpga_interfaces|h2f_ARVALID [0]) ) ).dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),.datab(gnd),.datac(gnd),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [8]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_demux_001|src8_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_demux_001|src8_valid~0 .lut_mask = 64'h00AA00AA00FF00FF;defparam \u0|mm_interconnect_0|cmd_demux_001|src8_valid~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y31_N27cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src8_valid~1 (// Equation(s):// \u0|mm_interconnect_0|cmd_demux_001|src8_valid~1_combout = ( \u0|mm_interconnect_0|router_001|Equal14~0_combout & ( \u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout & ( (\u0|mm_interconnect_0|router_001|Equal1~2_combout &// (\u0|mm_interconnect_0|router_001|Equal1~1_combout & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & \u0|mm_interconnect_0|router_001|Equal1~0_combout ))) ) ) ).dataa(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),.datab(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),.datad(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),.datae(!\u0|mm_interconnect_0|router_001|Equal14~0_combout ),.dataf(!\u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_demux_001|src8_valid~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_demux_001|src8_valid~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_demux_001|src8_valid~1 .lut_mask = 64'h0000000000000010;defparam \u0|mm_interconnect_0|cmd_demux_001|src8_valid~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y25_N39cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0_combout = ( \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [0] & ( \u0|mm_interconnect_0|cmd_demux|src8_valid~1_combout & ( (\u0|mm_interconnect_0|cmd_demux_001|src8_valid~1_combout &// \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [1]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [0] & ( \u0|mm_interconnect_0|cmd_demux|src8_valid~1_combout & ( (\u0|mm_interconnect_0|cmd_demux_001|src8_valid~1_combout &// \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [1]) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [0] & ( !\u0|mm_interconnect_0|cmd_demux|src8_valid~1_combout & ( (\u0|mm_interconnect_0|cmd_demux_001|src8_valid~1_combout &// \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [1]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [0] & ( !\u0|mm_interconnect_0|cmd_demux|src8_valid~1_combout & ( \u0|mm_interconnect_0|cmd_demux_001|src8_valid~1_combout ) )// ).dataa(!\u0|mm_interconnect_0|cmd_demux_001|src8_valid~1_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [1]),.datad(gnd),.datae(!\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [0]),.dataf(!\u0|mm_interconnect_0|cmd_demux|src8_valid~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0 .lut_mask = 64'h5555050505050505;defparam \u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y24_N18cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y24_N48cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout & (// (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout & ( ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] &// !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .lut_mask = 64'h5F555F550F000F00;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y24_N3cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout = (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2] $ (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) )// ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .lut_mask = 64'h50A050A05FAF5FAF;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y24_N5dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";// synopsys translate_on// Location: FF_X13_Y24_N2dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y24_N51cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout & (// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) ) # (// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),.datad(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .lut_mask = 64'h000F000F555F555F;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y24_N0cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout = (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] $ (((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q// & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] $ (((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))))) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .lut_mask = 64'h408C408C73BF73BF;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y24_N56dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y24_N39cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & ( ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg// [2]) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hF5FFF5FF0A000A00;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y24_N54cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout = ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout )))) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout )) #// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ))) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout )) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant// [1] & ( !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ) ) ) ).dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout ),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.datae(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.dataf(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .lut_mask = 64'hCC00DD11CF03DF13;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y25_N0cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y25_N2dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y25_N57cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal14~1 (// Equation(s):// \u0|mm_interconnect_0|router|Equal14~1_combout = ( \u0|mm_interconnect_0|router|Equal7~1_combout & ( (\u0|mm_interconnect_0|router|Equal14~0_combout & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout &// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout )) ) ).dataa(!\u0|mm_interconnect_0|router|Equal14~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|router|Equal7~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router|Equal14~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router|Equal14~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|router|Equal14~1 .lut_mask = 64'h0000000050005000;defparam \u0|mm_interconnect_0|router|Equal14~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y25_N59dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[8] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|router|Equal14~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [8]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[8] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[8] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y25_N3cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src8_valid~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ) #// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [8]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [8]),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_demux|src8_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_demux|src8_valid~0 .lut_mask = 64'h00000000FF0FFF0F;defparam \u0|mm_interconnect_0|cmd_demux|src8_valid~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y25_N12cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_valid~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout = ( \u0|mm_interconnect_0|router|Equal7~1_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout & (// (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & (\u0|mm_interconnect_0|router|Equal14~0_combout & (\u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout// ))) ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),.datab(!\u0|mm_interconnect_0|router|Equal14~0_combout ),.datac(!\u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout ),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~1_combout ),.datae(!\u0|mm_interconnect_0|router|Equal7~1_combout ),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_008|src_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_008|src_valid~0 .lut_mask = 64'h0000010000000000;defparam \u0|mm_interconnect_0|cmd_mux_008|src_valid~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y25_N30cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_valid~1 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout = ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_demux_001|src8_valid~1_combout ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_demux_001|src8_valid~1_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_008|src_valid~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_008|src_valid~1 .lut_mask = 64'h000000000F0F0F0F;defparam \u0|mm_interconnect_0|cmd_mux_008|src_valid~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y25_N21cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout = ( \u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout & (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) # (!\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datad(!\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .lut_mask = 64'hFFF0FFF0F0F0F0F0;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y25_N12cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout = ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) # ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )// # (((!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0])) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ))) ) ) # (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) #// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ))))) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datad(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),.datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.datag(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 .extended_lut = "on";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 .lut_mask = 64'hFEEEAAAAFFFFABAB;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y25_N54cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout = ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~18_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .lut_mask = 64'hFFFFFFFF00000000;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y25_N56dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y25_N30cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_payload[0] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_008|src_payload [0] = ( \u0|hps_0|fpga_interfaces|h2f_WLAST [0] & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WLAST [0] &// ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),.datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_008|src_payload [0]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_008|src_payload[0] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_008|src_payload[0] .lut_mask = 64'h3333333377777777;defparam \u0|mm_interconnect_0|cmd_mux_008|src_payload[0] .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y25_N32dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_008|src_payload [0]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";// synopsys translate_on// Location: FF_X11_Y25_N11dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y25_N57cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q// & ( \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1_combout ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h000000000000FFFF;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X11_Y25_N0cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout = (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) ) #// ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(gnd),.datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h0000FFFFFAFA5050;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X11_Y25_N2dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X11_Y25_N36cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout = (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] $// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2] & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] $ (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [3])) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h23DF23DF20DC20DC;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X11_Y25_N38dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X11_Y25_N6cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout = (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] &// ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]// & ( (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]// & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [2]))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2]))) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [2]))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])))) ) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h00E4FF4E0044FFEE;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X11_Y25_N8dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X11_Y25_N57cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [4] & !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h00000000A000A000;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X11_Y25_N12cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout = (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] $// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout )))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] $ (((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .lut_mask = 64'h33C333C33ACA3ACA;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X11_Y25_N39cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout = (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout &// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .lut_mask = 64'hF000F00000000000;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y25_N51cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout// & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ))) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h0100010055005500;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X11_Y25_N15cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q// ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h0000000000F000F0;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X11_Y25_N27cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout & (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout & (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) # ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout & (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout & ( ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout )) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ) ) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),.datad(gnd),.datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0000F7F7FFFFFFFF;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X11_Y25_N29dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y25_N18cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )))) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h5040504050005000;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y25_N6cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout & (// !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] &// !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),.datad(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .lut_mask = 64'hF000F000FF00FF00;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y25_N8dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y25_N24cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[34] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_008|src_data [34] = ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WSTRB [2])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]).dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),.datad(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [2]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [34]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_008|src_data[34] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[34] .lut_mask = 64'h333F333F333F333F;defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[34] .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y25_N26dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_008|src_data [34]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y25_N45cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[32] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_008|src_data [32] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [0] & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [0] & (// \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.datad(gnd),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [32]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_008|src_data[32] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[32] .lut_mask = 64'h0F0F0F0F5F5F5F5F;defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[32] .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y25_N47dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_008|src_data [32]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y25_N36cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[35] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_008|src_data [35] = ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WSTRB [3])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]).dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [3]),.datad(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [35]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_008|src_data[35] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[35] .lut_mask = 64'h05FF05FF05FF05FF;defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[35] .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y25_N38dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_008|src_data [35]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y25_N36cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2_combout = ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] &// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2 .lut_mask = 64'hC000C00000000000;defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y25_N54cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[88] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_008|src_data [88] = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ( ((\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) ) # (// !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ( (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),.datad(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [88]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_008|src_data[88] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[88] .lut_mask = 64'h000F000F555F555F;defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[88] .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y24_N21cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[87] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_008|src_data [87] = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) ) ) # (// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),.datac(gnd),.datad(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [87]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_008|src_data[87] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[87] .lut_mask = 64'h0033003355775577;defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[87] .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y25_N9cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_008|src_data [87] & ( !\u0|mm_interconnect_0|cmd_mux_008|src_data [88] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_008|src_data [88]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_008|src_data [87]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hF0F0F0F000000000;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y25_N11dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y25_N0cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|local_write~0_combout & ( (!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout &// (((\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2_combout & !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q )))) # (\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout &// ((!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]) # ((\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2_combout &// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q )))) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|local_write~0_combout & (// (!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout & (((\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2_combout & !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q )))) #// (\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout & (((\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2_combout & !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q )) #// (\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]))) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout ),.datab(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2_combout ),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|local_write~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3 .lut_mask = 64'h1F111F114F444F44;defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y25_N18cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q &// ((!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3_combout ) # (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1])))) ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) # ((!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3_combout )))) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h3032303230103010;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y25_N6cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & ((!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout )))) ) ) ) # ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & ((!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ))) ) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),.datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hF500FF003100FF00;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y24_N36cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout & (// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) ) # (// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),.datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.datad(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .lut_mask = 64'h0303030303FF03FF;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y24_N46dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y24_N33cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h0A000A0000000000;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y24_N45cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout )) )// ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout )) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .lut_mask = 64'h03CF03CFCF03CF03;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y24_N12cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout = ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout// ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] &// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout ) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & (// (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & (// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout ) ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout ),.datac(gnd),.datad(gnd),.datae(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .lut_mask = 64'h111111111111FFFF;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y24_N44dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y24_N42cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout = (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout )) ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout $ (((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]))))) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout// )))) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .lut_mask = 64'h478B478B03CF03CF;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y24_N6cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout & (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout// ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout & (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout// ) ) ) # ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout & (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout & (// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout &// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout &// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ))) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout & (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout// ) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),.datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h0F0F8F0F0F0F0F0F;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y24_N8dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y25_N42cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout = ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) ) # (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) #// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1_combout ))))) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1_combout ),.datag(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "on";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'h0C00F0F00C00F5F5;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y25_N30cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout & (// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout & (// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout &// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )))) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datad(!\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0007000707070707;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y25_N20dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y25_N12cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout & (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) #// ((!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]) # (\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout )))) ) ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout )) ) )// ) # ( \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ) #// (\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0])))) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout & (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) #// ((!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datab(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ),.datae(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout ),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hAAFABAFAAAFAEAFA;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y24_N20dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: FF_X11_Y25_N19dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X11_Y25_N18cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout = (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [6] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout &// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [6] & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & ( (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout// & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))// ) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .lut_mask = 64'h3000CFFF3A0ACAFA;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y25_N33cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout = ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .lut_mask = 64'hF0F0F0F000000000;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y25_N36cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout = ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) #// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ( (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ( (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ( (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datae(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .lut_mask = 64'h003300330033F0FB;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y25_N27cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout = ( !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & (// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout &// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout )) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .lut_mask = 64'h0500050000000000;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y25_N0cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout &// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q// )))) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout &// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h000A000A020A020A;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X11_Y25_N54cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h000000000C0C0C0C;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X11_Y25_N48cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout & (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout & (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout & (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ) ) ) # ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout & (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout & (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout & (// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout &// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ))) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ) ) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),.datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .lut_mask = 64'h0F2FFFFF0F0FFFFF;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .shared_arith = "off";// synopsys translate_on// Location: FF_X11_Y25_N50dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y25_N24cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q )) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q $// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q )) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .lut_mask = 64'hC03CC03C00C000C0;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y25_N48cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(gnd),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h1155115500440044;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y25_N50dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y25_N57cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h000000000AAA0AAA;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y25_N33cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_008|update_grant~0_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_008|update_grant~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~0 .lut_mask = 64'hFFFFFFFF00000000;defparam \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y25_N35dffeas \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y25_N6cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|update_grant~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_008|update_grant~0_combout = ( \u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & (// \u0|mm_interconnect_0|cmd_mux_008|src_payload [0] ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & (// (!\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout & ((!\u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~q ))) # (\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout & (\u0|mm_interconnect_0|cmd_mux_008|src_payload [0])) ) ) ) # (// \u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & (// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & \u0|mm_interconnect_0|cmd_mux_008|src_payload [0]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout & (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & ( (!\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout & (((!\u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~q )))) #// (\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (\u0|mm_interconnect_0|cmd_mux_008|src_payload [0]))) ) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datab(!\u0|mm_interconnect_0|cmd_mux_008|src_payload [0]),.datac(!\u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~q ),.datad(!\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout ),.datae(!\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout ),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_008|update_grant~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_008|update_grant~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_008|update_grant~0 .lut_mask = 64'hF0111111F0333333;defparam \u0|mm_interconnect_0|cmd_mux_008|update_grant~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y25_N41dffeas \u0|mm_interconnect_0|cmd_mux_008|saved_grant[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|cmd_mux_008|update_grant~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_008|saved_grant[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|cmd_mux_008|saved_grant[1] .power_up = "low";// synopsys translate_on// Location: FF_X15_Y25_N28dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";// synopsys translate_on// Location: FF_X18_Y25_N20dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y25_N18cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][66]~q ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][66]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h0F0F0F0F00FF00FF;defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y25_N48cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~feeder (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~feeder_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y25_N56dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y25_N27cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0 .lut_mask = 64'h0000000055FF55FF;defparam \u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y25_N26dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y25_N24cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][129]~q & ( \u0|mm_interconnect_0|auto_start_s1_agent|local_write~0_combout & (// (((\u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout & \u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout )) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout )) #// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][129]~q & ( \u0|mm_interconnect_0|auto_start_s1_agent|local_write~0_combout & (// (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout & \u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout )) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][129]~q & (// !\u0|mm_interconnect_0|auto_start_s1_agent|local_write~0_combout & ( ((\u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout & \u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout )) #// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][129]~q & ( !\u0|mm_interconnect_0|auto_start_s1_agent|local_write~0_combout & (// (\u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout & (\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout & !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1])) ) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout ),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datae(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][129]~q ),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|local_write~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h10101F1F10F01FFF;defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y25_N38dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~0_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y25_N24cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|comb~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0] ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129]~q ) #// (\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0]))) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|comb~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|comb~0 .lut_mask = 64'h050F050F0F0F0F0F;defparam \u0|mm_interconnect_0|auto_start_s1_agent|comb~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y25_N39cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_BREADY [0] & ( \u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout & ( (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ) #// (\u0|hps_0|fpga_interfaces|h2f_RREADY [0]) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_BREADY [0] & ( \u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] &// !\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ) ) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),.datad(gnd),.datae(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0 .lut_mask = 64'h0000000050505F5F;defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X11_Y25_N32dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";// synopsys translate_on// Location: LABCELL_X11_Y25_N30cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) #// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][74]~q ))) ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] &// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) # (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][74]~q// ))) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][74]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h447744770C3F0C3F;defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y25_N14dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";// synopsys translate_on// Location: FF_X17_Y25_N53dffeas \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y25_N36cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy~q & ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter// [2] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h0000000000FF00FF;defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X11_Y25_N35dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";// synopsys translate_on// Location: LABCELL_X11_Y25_N33cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) #// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][77]~q ))) ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][77]~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][77]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h003300330C3F0C3F;defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y25_N29dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";// synopsys translate_on// Location: FF_X14_Y25_N41dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y25_N39cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][75]~q ))) ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][75]~q ) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][75]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h005500550A5F0A5F;defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y25_N41dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";// synopsys translate_on// Location: FF_X11_Y25_N47dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";// synopsys translate_on// Location: LABCELL_X11_Y25_N45cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) #// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][76]~q ))) ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][76]~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][76]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h003300330C3F0C3F;defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y25_N23dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y25_N54cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout = (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q & (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q &// (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q & !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q ))).dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q ),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0 .lut_mask = 64'h8000800080008000;defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X11_Y25_N44dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";// synopsys translate_on// Location: LABCELL_X11_Y25_N42cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][78]~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][78]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h003300330C3F0C3F;defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y25_N17dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y25_N30cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q & ( (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ))) # (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q & ( (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ))) # (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q & ( (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ))) # (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q & ( (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ))) # (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ),.datae(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h0E040B01040E010B;defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y25_N32dffeas \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y25_N12cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter// [2] & !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (// (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) # (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h3F3F3F3FC0C0C0C0;defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y25_N42cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q & (// (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q ))) #// (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0_combout )) ) ) ) # (// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q & ( (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q $ (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q )))) # (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0_combout ),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q ),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ),.datae(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h0000E22E00002E2E;defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y25_N44dffeas \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y25_N9cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter// [5] & (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2])) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1 .lut_mask = 64'h8080808000000000;defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y25_N24cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout// & (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q )))) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout $// (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q )) # (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # (// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q )) # (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) #// ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout & (// (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout// $ (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q )))) ) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout ),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q ),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),.datae(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0060006F006F0060;defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y25_N26dffeas \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y25_N48cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout// & ( (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (((!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q & \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout )))) #// (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6])) ) ) ) # (// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q &// (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout & !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q ),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout ),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datae(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h00000C0000000CAA;defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y25_N50dffeas \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y25_N15cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy~q & (// ((!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1_combout ) # (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2])) #// (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [7]) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00000000F7F7F7F7;defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y25_N57cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout ) ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q & (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout &// !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout )) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h0C000C000F000F00;defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y25_N59dffeas \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y25_N39cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter// [5] ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $// (((!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]))) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h6A6A6A6AAAAAAAAA;defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y25_N0cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q & ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q & ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q $ (((!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q &// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q ))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q ),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h3CF03CF0F0F0F0F0;defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y25_N3cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2_combout ) ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1_combout// ) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2_combout ),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h5500550050505050;defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y25_N5dffeas \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y25_N6cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4] &// !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3])) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'h8080808000000000;defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y25_N18cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0_combout = ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q & ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q & (// (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy~q & (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q & (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q &// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy~q ),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q ),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ),.datae(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q ),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h2000000000000000;defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y25_N24cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~q & (// (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0_combout & ((!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1_combout ) #// (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~q ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1_combout ),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0_combout ),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout ),.datad(gnd),.datae(!\u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout ),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00000000FFFFC8C8;defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y25_N3cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0]~1 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0] & ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0] & ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0_combout ) ) ) # (// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & ( ((!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ) #// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1])) # (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0] & (// !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0_combout ),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),.datad(gnd),.datae(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0]),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h5555DFDF5555FFFF;defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y25_N5dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y25_N54cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0]) #// (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout & ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0] ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0]),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hAAAAAAAAEEEEEEEE;defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y25_N50dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";// synopsys translate_on// Location: FF_X18_Y25_N11dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][68] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~2_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][68]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][68] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][68] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y25_N12cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~2 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~2_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][68]~q ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used// [1] & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][68]~q ) ) ) # ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & (// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][68]~q ),.datac(gnd),.datad(gnd),.datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h0000FFFF33333333;defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y25_N56dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][68] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~2_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][68]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][68] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][68] .power_up = "low";// synopsys translate_on// Location: FF_X18_Y25_N59dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][69] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][69]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][69] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][69] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y25_N57cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~1 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][69]~q & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] ) ) # (// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][69]~q & ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] ) )// ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][69]~q & ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg// [69] ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.datad(gnd),.datae(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][69]~q ),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h0F0F0F0F0000FFFF;defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y25_N44dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][69] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~1_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][69]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][69] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][69] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y25_N15cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_008|src0_valid~0 (// Equation(s):// \u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout = ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][69]~q & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~q &// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][68]~q ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~q ),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][68]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][69]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|rsp_demux_008|src0_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|rsp_demux_008|src0_valid~0 .lut_mask = 64'h00F000F000000000;defparam \u0|mm_interconnect_0|rsp_demux_008|src0_valid~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y25_N18cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|rp_valid (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout = ( !\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0] &// ((!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129]~q ))) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|rp_valid .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|rp_valid .lut_mask = 64'hF0A0F0A000000000;defparam \u0|mm_interconnect_0|auto_start_s1_agent|rp_valid .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y31_N6cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal7~0 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal7~0_combout = (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17])).dataa(gnd),.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal7~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal7~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal7~0 .lut_mask = 64'h3000300030003000;defparam \u0|mm_interconnect_0|router_001|Equal7~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y31_N30cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal8~0 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal8~0_combout = ( \u0|mm_interconnect_0|router_001|Equal7~0_combout & ( (\u0|mm_interconnect_0|router_001|Equal2~0_combout & (\u0|mm_interconnect_0|router_001|Equal1~0_combout &// \u0|mm_interconnect_0|router_001|Equal1~1_combout )) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|router_001|Equal2~0_combout ),.datac(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),.datad(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|router_001|Equal7~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal8~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal8~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal8~0 .lut_mask = 64'h0000000000030003;defparam \u0|mm_interconnect_0|router_001|Equal8~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y31_N46dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[19] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|router_001|Equal8~0_combout ),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [19]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[19] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[19] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y38_N21cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout = ( \u0|mm_interconnect_0|router_001|Equal8~0_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) #// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [19]))) ) ).dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [19]),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|router_001|Equal8~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0 .lut_mask = 64'h000000000F050F05;defparam \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y36_N45cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y38_N27cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y38_N29dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y38_N3cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] &// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout & \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),.datac(gnd),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000000000440044;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y38_N38dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y36_N9cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y36_N11dffeas \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: FF_X25_Y36_N29dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y38_N45cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]// & (\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout & \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h000A000A00AA00AA;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y36_N48cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout = !\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1].dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hCCCCCCCCCCCCCCCC;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y36_N50dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";// synopsys translate_on// Location: FF_X25_Y38_N17dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y38_N39cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q &// (((!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout & !\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout )) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]))) ) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ) ) # (// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & (((!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout & !\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout )) #// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]))) ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h000000D5FFFF00D5;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y38_N21cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) # (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .lut_mask = 64'hFFF0FFF000000000;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y38_N9cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = ( \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] &// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout )))) #// (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & (((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout )) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ))) ) ) # (// !\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h0033003305370537;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y38_N11dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";// synopsys translate_on// Location: FF_X25_Y36_N13dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y36_N45cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & (// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] &// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1])) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h1010101030303030;defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y36_N21cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout &// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout & !\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [0])) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~0 .lut_mask = 64'h000000000A000A00;defparam \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y36_N23dffeas \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter[0] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y36_N15cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout = (\u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~q & \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [0]).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~q ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [0]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0 .lut_mask = 64'h000F000F000F000F;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y38_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (// (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h0000000030F030F0;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y36_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2] & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) ) #// ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) )// ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h55AF55AF50AA50AA;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y36_N44dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: FF_X22_Y36_N20dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y36_N33cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2] & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] $// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] $ (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) #// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h31DF31DF20CE20CE;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y36_N35dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y36_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout = (// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])) ) ) ) # ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) #// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) #// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))))) ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h0D08F7F20500FFFA;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y36_N9cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h00A000A000000000;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y36_N30cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2] & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout $// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout $// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) #// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ))) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .lut_mask = 64'h1BF51BF50AE40AE4;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y36_N32dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";// synopsys translate_on// Location: FF_X22_Y36_N56dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y36_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout = (// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )))) ) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))))// # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ))) ) ) ) # (// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .lut_mask = 64'h0404FEFEAE0454FE;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y36_N0cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout// & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout &// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout &// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout )) ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .lut_mask = 64'hC000000000000000;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y38_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (// ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0F4F0F4F00440044;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y38_N44dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y38_N51cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'hFF00FF0000000000;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y38_N36cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & (// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout )) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h0000000010101010;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y38_N39cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (// ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout &// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h004400440F4F0F4F;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y38_N41dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y38_N3cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout )) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.datad(!\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h0000000000050005;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y38_N45cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout & (// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout & (// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q &// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout )))) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h0045004555555555;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y38_N47dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y38_N21cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q )) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q $// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q )) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .lut_mask = 64'hC03CC03C00C000C0;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y38_N0cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout &// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q )) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h00CC00CC000C000C;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y38_N24cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout &// (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ))).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.datab(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datad(!\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h0002000200020002;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y38_N29dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";// synopsys translate_on// Location: FF_X25_Y38_N59dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";// synopsys translate_on// Location: FF_X25_Y38_N35dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y38_N57cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] &// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1])) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1 .lut_mask = 64'hA000A00000000000;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y36_N6cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = (!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]) # ((!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] &// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1])).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),.datab(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hECECECECECECECEC;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y36_N8dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y38_N48cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout & ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1_combout & (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] &// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q )) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2 .lut_mask = 64'h50005000F0F0F0F0;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y38_N6cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2_combout & (// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2_combout & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'h3030303033003300;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y38_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) #// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ))) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h1111111105550555;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y38_N20dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y38_N30cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] &// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] &// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]))) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] &// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1])) ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0 .lut_mask = 64'hA000800000000000;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y36_N33cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout ),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h1111111133333333;defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y36_N41dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y36_N39cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used// [1] & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] &// ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][75]~q ))) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][75]~q ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(gnd),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][75]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h0055005522772277;defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y36_N36cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~feeder (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~feeder_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y36_N38dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y36_N36cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout & ( ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][129]~q )) # (\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout & (// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][129]~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][129]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h003300330F3F0F3F;defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y36_N44dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y36_N30cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout &// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout & \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [0])) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [0]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0000000002020202;defparam \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y36_N32dffeas \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg[0] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y36_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q & (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] &// ((\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0])))) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0] & (// (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]))) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),.datad(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h003F003F002A002A;defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y15_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1]~1 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout &// ((\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]))) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0] & (// (!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout & \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h00CC00CC0CCC0CCC;defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y15_N14dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y36_N51cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0]~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0] &// \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout & (// ((\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1])) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h30FF30FF0F3F0F3F;defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y36_N53dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y36_N48cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|comb~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0] & ( ((\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]) #// (\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|comb~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|comb~0 .lut_mask = 64'h000000007F7F7F7F;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|comb~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y36_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout & ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0 .lut_mask = 64'h000000000F0F0F0F;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y36_N39cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0]~1 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout & ( ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0] &// ((\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout ) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout & ( (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h55FF55FF557F557F;defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y36_N41dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y36_N24cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]) #// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout & ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0] ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hCCCCCCCCFCFCFCFC;defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y36_N38dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";// synopsys translate_on// Location: FF_X22_Y36_N38dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y36_N36cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][78]~q ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][78]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h0303030300FF00FF;defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y36_N35dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";// synopsys translate_on// Location: FF_X22_Y36_N53dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y36_N51cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4_combout = (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] &// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))// # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][77]~q )))).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][77]~q ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h0257025702570257;defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y36_N5dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";// synopsys translate_on// Location: FF_X22_Y36_N50dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y36_N48cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] &// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [2])))) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] &// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))// # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][74]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h025702578ADF8ADF;defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y36_N23dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";// synopsys translate_on// Location: FF_X22_Y36_N14dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y36_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][76]~q ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][76]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h0303030300FF00FF;defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y36_N26dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y36_N24cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q &// (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q & !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q )) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hC000C00000000000;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y36_N44dffeas \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y36_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy~q & ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] )// ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h0000000000FF00FF;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y36_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2_combout & (// (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ) # (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h5151515100000000;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y36_N56dffeas \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y36_N3cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) )// # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3] $// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h66666666CCCCCCCC;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y36_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0_combout & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q & (// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q & (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0_combout & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout &// ((\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q ))) ) ) ) # ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0_combout & (// !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q $ (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q )))) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0_combout & (// !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q $// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q )) # (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datae(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0_combout ),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h2133210011331100;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y36_N14dffeas \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y34_N21cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) ) # (// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (// !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datad(gnd),.datae(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h5A5AAAAAAAAAAAAA;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y36_N21cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q & ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q & ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q $ (((!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q &// !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h5AF05AF0F0F0F0F0;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y36_N57cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1_combout & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout &// (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2_combout )) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1_combout & (// (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ) # (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2_combout )))// ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h5454545410101010;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y36_N59dffeas \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y36_N27cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hA000A00000000000;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y36_N6cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q )))) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout $// (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q )) # (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # (// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q )) # (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout &// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q )))) ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datae(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h1200123312331200;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y36_N8dffeas \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y36_N36cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout & (// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q & ((\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout )))) #// (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6])))) ) ) ) # (// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q &// (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout & !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datae(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h00000A0000000ACC;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y36_N38dffeas \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y36_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy~q ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy~q// & ((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1_combout ) # (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [7]))) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00AF00AF00FF00FF;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y36_N48cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q $// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q )) # (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q $// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q )))) ) ) ) # ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter// [2] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q $// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q )))) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter// [2] & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q $ (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q )) #// (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),.datae(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h00B70084008400B7;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y36_N50dffeas \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y36_N0cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] &// !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datac(gnd),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'h8800880000000000;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y36_N20dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y36_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2_combout = (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66])) #// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][66]~q ))).dataa(gnd),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][66]~q ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h0C3F0C3F0C3F0C3F;defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y36_N2dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y36_N30cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q & ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q & (// (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q & (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy~q & (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q &// !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy~q ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q ),.datae(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0000800000000000;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y36_N45cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0_combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout &// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66]~q ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0_combout & ( (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66]~q &// ((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1_combout ) # ((!\u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout ) # (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2_combout )))) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1_combout ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2_combout ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00FE00FE00CC00CC;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y36_N57cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1]~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout &// (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout &// ((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout &// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0])))) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout &// ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout & (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0])) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h05AF05AF01670167;defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y36_N59dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y38_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (// (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ))) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFFFFFFFF2A2A2A2A;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y36_N47dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y38_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1])) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .lut_mask = 64'h1DD11DD10CC00CC0;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y38_N14dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";// synopsys translate_on// Location: FF_X23_Y38_N32dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y38_N30cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg// [3] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) #// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1])) ) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1])) ) ) ) # ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout// & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 .lut_mask = 64'h0C00C0CC1D11D1DD;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y38_N29dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y38_N48cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]// & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $ (((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'hB4B4B4B4F0F0F0F0;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y38_N27cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & (// (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #// ((\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0 .lut_mask = 64'hF0F3F0F300030003;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y38_N51cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] &// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4])) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'h5000500000000000;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y38_N15cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) #// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ))) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ))) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .lut_mask = 64'h01CD01CDCD01CD01;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y38_N16dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";// synopsys translate_on// Location: FF_X23_Y38_N56dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y38_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg// [6] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ) # ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) #// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1])))) ) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout &// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (((\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1])))) ) ) ) # ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) ) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & (// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] &// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.datab(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2 .lut_mask = 64'h5000AF005033AF33;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y38_N9cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout & (// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout &// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0 .lut_mask = 64'h0F000F0000000000;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y38_N6cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout &// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout & \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0_combout )) ) )// # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) #// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout &// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout & \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0_combout ))) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Equal0~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'hF0F8F0F800880088;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y38_N8dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y38_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] &// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & ((\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout )))) ) )// ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ),.datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .lut_mask = 64'hF0F0000020A00000;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y38_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ))) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ))) #// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .lut_mask = 64'h08FF08FF08000800;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y38_N24cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout &// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ) ) ) ) # ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout )) ) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ) ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),.datad(gnd),.datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .lut_mask = 64'hC0C08080C0C00000;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y38_N0cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~0_combout = ( \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & ((\u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~q ))) #// (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout & (// \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~q ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),.datac(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.datad(!\u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~0 .lut_mask = 64'h00FF00FF03F303F3;defparam \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y38_N1dffeas \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y38_N36cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|update_grant~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_019|update_grant~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout & ( (!\u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~q &// ((!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]) # (!\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ))) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout & (// (!\u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~q ) # ((\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout )) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~q ),.datad(!\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_019|update_grant~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_019|update_grant~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_019|update_grant~0 .lut_mask = 64'hF0F5F0F5F0A0F0A0;defparam \u0|mm_interconnect_0|cmd_mux_019|update_grant~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y38_N38dffeas \u0|mm_interconnect_0|cmd_mux_019|saved_grant[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|cmd_mux_019|update_grant~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_019|saved_grant[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|cmd_mux_019|saved_grant[1] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y32_N24cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~11 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_019|src_payload~11_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~11 .lut_mask = 64'h0000000033333333;defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y32_N26dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_019|src_payload~11_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";// synopsys translate_on// Location: FF_X25_Y32_N20dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y32_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][116]~q ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][116]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h0F0F0F0F00FF00FF;defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y32_N35dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y36_N27cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] &// (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0] & !\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0])) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q & (// (!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] & !\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid .lut_mask = 64'hA0A0A0A080808080;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y32_N33cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~198 (// Equation(s):// \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~198_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & ( (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116]~q & (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout// & !\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout )) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & ( ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116]~q &// (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout & !\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ))) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][116]~q ) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116]~q ),.datab(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][116]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~198_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~198 .extended_lut = "off";defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~198 .lut_mask = 64'h40FF40FF40404040;defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~198 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y32_N45cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~199 (// Equation(s):// \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~199_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][116]~q & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~198_combout & (// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~q ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ))) ) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][116]~q & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~198_combout & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~q ) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ) ) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~q ),.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][116]~q ),.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~198_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~199_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~199 .extended_lut = "off";defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~199 .lut_mask = 64'hFF550F0500000000;defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~199 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y33_N27cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~11 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_017|src_payload~11_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~11 .lut_mask = 64'h0000000055555555;defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y33_N29dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_017|src_payload~11_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";// synopsys translate_on// Location: FF_X19_Y33_N32dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y33_N30cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][116]~q ) ) # (// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][116]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h0F0F0F0F00FF00FF;defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y33_N22dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y31_N30cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~11 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_016|src_payload~11_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),.dataf(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~11 .lut_mask = 64'h000000000000FFFF;defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y31_N32dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_016|src_payload~11_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";// synopsys translate_on// Location: FF_X17_Y31_N41dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y31_N39cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][116]~q ) ) # (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][116]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h0F0F0F0F00FF00FF;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y30_N17dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";// synopsys translate_on// Location: FF_X21_Y29_N56dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y29_N54cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~3 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~3_combout = (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66])) #// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][66]~q ))).dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][66]~q ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h0A5F0A5F0A5F0A5F;defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y29_N42cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4_combout = ( \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] & ( (\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout &// (((!\u0|mm_interconnect_0|link_start_s1_agent|local_write~0_combout ) # (\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout )) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]))) ) ) # (// !\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (!\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout &// (\u0|mm_interconnect_0|link_start_s1_agent|local_write~0_combout & \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout ))) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ),.datac(!\u0|mm_interconnect_0|link_start_s1_agent|local_write~0_combout ),.datad(!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4 .lut_mask = 64'h0008000800F700F7;defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y29_N39cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~1 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~1_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4_combout & ( \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0_combout ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h000000000F0F0F0F;defparam \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y29_N41dffeas \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y29_N9cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~0 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~0_combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][129]~q & ( ((!\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0] &// !\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0]) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][129]~q & (// (!\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0]) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0]),.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][129]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~0 .lut_mask = 64'hF000F000F555F555;defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y29_N48cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1_combout = ( \u0|hps_0|fpga_interfaces|h2f_BREADY [0] & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~0_combout & ((\u0|hps_0|fpga_interfaces|h2f_RREADY [0]) #// (\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ))) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_BREADY [0] & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~0_combout & (!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout &// \u0|hps_0|fpga_interfaces|h2f_RREADY [0])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~0_combout ),.datac(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),.datad(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datae(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1 .lut_mask = 64'h00C00CCC00C00CCC;defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y29_N54cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[1]~1 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1_combout &// ((\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [1]) # (\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0]))) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0] & (// (!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1_combout & \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [1]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0]),.datac(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1_combout ),.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h00F000F030F030F0;defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y29_N56dffeas \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y29_N57cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[0]~0 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1_combout & ( ((\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0] &// \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1_combout & (// ((!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [1] & \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0]) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0]),.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h0AFF0AFF555F555F;defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y29_N59dffeas \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y29_N12cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|comb~0 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0] & ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][129]~q ) ) # (// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0]) #// (\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0]) ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0]),.datac(gnd),.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0]),.datae(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0]),.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][129]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent|comb~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|comb~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent|comb~0 .lut_mask = 64'h000033FF0000FFFF;defparam \u0|mm_interconnect_0|link_start_s1_agent|comb~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y29_N42cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_BREADY [0] & ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( \u0|mm_interconnect_0|link_start_s1_agent|comb~0_combout ) ) ) # (// !\u0|hps_0|fpga_interfaces|h2f_BREADY [0] & ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( (!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout & \u0|mm_interconnect_0|link_start_s1_agent|comb~0_combout ) ) ) ) # (// \u0|hps_0|fpga_interfaces|h2f_BREADY [0] & ( !\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( (\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout & \u0|mm_interconnect_0|link_start_s1_agent|comb~0_combout ) ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),.datad(!\u0|mm_interconnect_0|link_start_s1_agent|comb~0_combout ),.datae(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),.dataf(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0 .lut_mask = 64'h0000000F00F000FF;defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y29_N24cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0]) #// (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout & ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hF0F0F0F0FFF0FFF0;defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y29_N53dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~3_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";// synopsys translate_on// Location: FF_X21_Y29_N59dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][69] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][69]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][69] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][69] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y29_N57cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~1 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1])// # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][69]~q ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & (// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][69]~q ) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][69]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h00550055AAFFAAFF;defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y29_N47dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][69] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~1_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][69]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][69] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][69] .power_up = "low";// synopsys translate_on// Location: FF_X22_Y29_N38dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][68] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][68]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][68] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][68] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y29_N36cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~2 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~2_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1])// # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][68]~q ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & (// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][68]~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),.datac(gnd),.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][68]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h00330033CCFFCCFF;defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y29_N17dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][68] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~2_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][68]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][68] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][68] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y29_N18cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_007|src0_valid~0 (// Equation(s):// \u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][68]~q & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66]~q &// !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][69]~q ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66]~q ),.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][69]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][68]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|rsp_demux_007|src0_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|rsp_demux_007|src0_valid~0 .lut_mask = 64'h00000000F000F000;defparam \u0|mm_interconnect_0|rsp_demux_007|src0_valid~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y31_N48cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~11 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_013|src_payload~11_combout = ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~11 .lut_mask = 64'h0000000000FF00FF;defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~11 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y38_N48cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & (\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout & \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),.datac(!\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ),.datad(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h00000000000C000C;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y31_N50dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_013|src_payload~11_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";// synopsys translate_on// Location: FF_X17_Y31_N23dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";// synopsys translate_on// Location: FF_X17_Y38_N11dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";// synopsys translate_on// Location: FF_X17_Y38_N8dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y38_N48cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & (// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] &// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h030003000F000F00;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y38_N39cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y38_N41dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y38_N51cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~q & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout// & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout & !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [0])) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~0 .lut_mask = 64'h000000000A000A00;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y38_N53dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y38_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~q & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [0] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [0]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0 .lut_mask = 64'h000000000F0F0F0F;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y38_N0cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout & !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1 .lut_mask = 64'h0F000F00FF00FF00;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y39_N9cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1_combout & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1_combout ),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h000000000000FFFF;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y38_N21cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y38_N51cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] &// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ))) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFFFFFFFF50F050F0;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y38_N22dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: FF_X19_Y38_N32dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y38_N6cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout = (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h00FF00FFFC0CFC0C;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y38_N8dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y38_N0cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] &// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h4040404000000000;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y38_N48cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout = (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout $// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] $// (((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .lut_mask = 64'h0AF50AF54EE44EE4;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y38_N47dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";// synopsys translate_on// Location: FF_X19_Y38_N44dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y38_N15cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout = (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]// & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] $// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6])))) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6])))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]// & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] &// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) ) # (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]// & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] $// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6])))) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6])) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2] & ( ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .lut_mask = 64'h0F5FC35F0F0AC30A;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y38_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout & ( ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) ) # ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout & ( ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q &// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ) #// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'hDC50DD55CC00DD55;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y38_N21cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout = ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout &// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .lut_mask = 64'h0000000000050005;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y38_N24cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout = (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout &// (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout &// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q )) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout// ))) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout &// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout// ))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .lut_mask = 64'h050F050F05070507;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y38_N26dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y38_N33cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout = (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q $// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .lut_mask = 64'hA000A0005AA05AA0;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y38_N39cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & (// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout &// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h000000000F000F00;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y38_N9cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout &// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h0055005500000000;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y38_N30cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout = (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0 .lut_mask = 64'hF0F0F0F000000000;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y38_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout// ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout & (// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout &// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout &// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ))) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) ) ) ) # (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout// ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout// ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h00FF00FF20FF00FF;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y38_N56dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y38_N51cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout = (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] $// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h00FF00FFE44EE44E;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y38_N53dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y38_N33cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout = (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] ) ) ) # (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] $// (((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h339933F0333333F0;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y38_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout = (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h000000000A0A0A0A;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y38_N48cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout = (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout// ) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout & ( ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout// & ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout )))) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) ) ) ) # (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout & (// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout )// ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout & (// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout )// ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h33FF33FF13FF33FF;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y38_N50dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";// synopsys translate_on// Location: FF_X19_Y38_N59dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y38_N57cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] &// (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] &// (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h043704378CBF8CBF;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y38_N27cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout ),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h1111111133333333;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y38_N38dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y38_N36cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout & ( ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][129]~q )) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout & (// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][129]~q ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][129]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h000F000F555F555F;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y38_N23dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y38_N15cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] &// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ))) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0] &// ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0] & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]) #// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q )))) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h0504050455445544;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y38_N45cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1]~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg// [0] & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [1]) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h05FF05FF00000000;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y38_N47dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y38_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0]~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg// [0] & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout & (// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0]),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h0CFF0CFF333F333F;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y38_N44dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y38_N6cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0_combout = (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0] & (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q )) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0]))).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0]),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0 .lut_mask = 64'h1333133313331333;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y38_N3cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0_combout ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0_combout ),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0 .lut_mask = 64'h0000000000FF00FF;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y38_N30cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0]~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used// [0]) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout & (// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0] & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1])))) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h33F733F733FF33FF;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y38_N32dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y38_N3cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout = (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]) # ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout// & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout )).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hCCFCCCFCCCFCCCFC;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y38_N14dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";// synopsys translate_on// Location: FF_X19_Y38_N56dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y38_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][75]~q ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][75]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h0505050500FF00FF;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y38_N29dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";// synopsys translate_on// Location: FF_X19_Y38_N1dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y38_N21cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][77]~q & (// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][77]~q & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datad(gnd),.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][77]~q ),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h0404373704043737;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y38_N26dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";// synopsys translate_on// Location: FF_X19_Y38_N5dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y38_N3cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ))) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h000F000F303F303F;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y38_N38dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y38_N24cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1_combout = ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ) ) # (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q &// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q & (// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ) ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),.datad(gnd),.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h3F3FC0C0FFFF0000;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y38_N11dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y38_N15cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h000000000F0F0F0F;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y38_N30cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h00000000CC0CCC0C;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y38_N32dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y38_N39cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h5F5F5F5FA0A0A0A0;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y38_N24cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0_combout & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q $ (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ))))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0_combout & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q $ (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q )))) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0_combout ),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h00000000B7778444;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y38_N26dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y38_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] &// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hC000C00000000000;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y38_N9cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout = ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q &// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q & !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q )) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hA000A00000000000;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y38_N41dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y38_N39cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6])) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h003300330C3F0C3F;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y38_N20dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y38_N48cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q )))) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout )) ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout $// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q )))) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ),.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h000000001BB14EE4;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y38_N50dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y38_N6cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q )))) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout ))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout &// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ),.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout ),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h000000000202F202;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y38_N7dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y38_N33cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h0A0F0A0F0F0F0F0F;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y38_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q $ (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q )))) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2])) ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q $// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q )))) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2])) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h00000000E44EB11B;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y38_N56dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y38_N36cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h78787878F0F0F0F0;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y38_N45cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2_combout ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1_combout &// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h0A0A0A0A0F000F00;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y38_N47dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y38_N0cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] &// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hC000C00000000000;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y38_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout = ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q &// ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q &// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h2000000000000000;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y38_N35dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y38_N33cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~2_combout = (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] &// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66])) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] &// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ))).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h0A5F0A5F0A5F0A5F;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y38_N41dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~2_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y38_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66]~q & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0_combout ) #// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ) #// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout )))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00000000FEF0FEF0;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y38_N0cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1]~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used// [0])) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout & ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]))))) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0])) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h00F500F5313B313B;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y38_N2dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y31_N21cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][116]~q ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][116]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h5555555500FF00FF;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y31_N17dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";// synopsys translate_on// Location: FF_X18_Y29_N8dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y29_N45cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[116] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_007|src_data [116] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [11])) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) ) ) # (// !\u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [11]) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),.datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),.datad(gnd),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [11]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [116]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_007|src_data[116] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[116] .lut_mask = 64'h0505050537373737;defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[116] .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y29_N46dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_007|src_data [116]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y29_N45cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] &// ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][116]~q ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & (// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][116]~q ) ) ) # ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg// [116] & ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][116]~q ),.datad(gnd),.datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21 .lut_mask = 64'h0000FFFF0F0F0F0F;defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y29_N2dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y31_N15cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~196 (// Equation(s):// \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~196_combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116]~q & ( (!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout &// ((!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ) # ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116]~q )))) #// (\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout & (((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116]~q )))) ) ) # (// !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116]~q & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116]~q ) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),.datab(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~196_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~196 .extended_lut = "off";defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~196 .lut_mask = 64'h00F000F088F888F8;defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~196 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y30_N15cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~197 (// Equation(s):// \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~197_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][116]~q & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~196_combout & (// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout & ((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][116]~q ) # (!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ))) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][116]~q & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~196_combout & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][116]~q ) #// (!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ) ) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][116]~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ),.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][116]~q ),.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~196_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~197_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~197 .extended_lut = "off";defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~197 .lut_mask = 64'hFAFA00FA00000000;defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~197 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y24_N36cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[116] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_018|src_data [116] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [11])) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]) ) ) # (// !\u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [11]) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),.datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),.datac(gnd),.datad(!\u0|hps_0|fpga_interfaces|h2f_AWID [11]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [116]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_018|src_data[116] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[116] .lut_mask = 64'h0033003355775577;defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[116] .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y24_N37dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_018|src_data [116]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";// synopsys translate_on// Location: FF_X25_Y24_N11dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~21_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y21_N36cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y21_N38dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y23_N57cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_payload[0] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_018|src_payload [0] = ((\u0|hps_0|fpga_interfaces|h2f_WLAST [0] & \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]).dataa(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),.datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),.datac(gnd),.datad(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_018|src_payload [0]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_018|src_payload[0] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_018|src_payload[0] .lut_mask = 64'h3377337733773377;defparam \u0|mm_interconnect_0|cmd_mux_018|src_payload[0] .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y23_N59dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_018|src_payload [0]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y21_N27cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout & (// (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] &// !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0])) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),.datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),.datac(gnd),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~4_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .lut_mask = 64'h7755775533003300;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y21_N15cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout = (// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]// $ (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # (// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $ (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .lut_mask = 64'h0AA00AA05FF55FF5;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y21_N17dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";// synopsys translate_on// Location: FF_X25_Y21_N35dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y21_N24cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout & (// ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout )) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) ) # (// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),.datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .lut_mask = 64'h0303030357575757;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y21_N33cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout = (// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout & (// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] $ (((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # (// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] $ (((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))))) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .lut_mask = 64'h08A208A25DF75DF7;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y21_N2dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y21_N30cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg// [3] & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $// (((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hF03CF03CF0F0F0F0;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y21_N0cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout = ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & (// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout ))) ) ) ) # (// !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & (// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ) ) # (// \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & (// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # (((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) #// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout )) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & (// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #// ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~2_combout ),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),.datae(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .lut_mask = 64'hAABBAFBF00110515;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y21_N42cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant// [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout )) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & (// (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),.datac(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~1_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .lut_mask = 64'h000F000F333F333F;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y21_N47dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y21_N21cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] &// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datab(gnd),.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h00A000A000000000;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y21_N45cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & (// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) #// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout )) ) )// # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout )) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .lut_mask = 64'h05AF05AFAF05AF05;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y21_N59dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y21_N27cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout = (// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout $// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(gnd),.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h0FF00FF00AFA0AFA;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y21_N29dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y21_N30cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout = (// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # (// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &// ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # (// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &// ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))// # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) ) ) #// ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]// & ( (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))// # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h00CAFF3A000AFFFA;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y21_N32dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y21_N15cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] &// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h0C000C0000000000;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y21_N54cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout = (// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] $ (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .lut_mask = 64'h0FF00FF02E2E2E2E;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y21_N35dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";// synopsys translate_on// Location: FF_X28_Y21_N7dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y21_N6cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout = (// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ) ) ) # (// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout// ) ) ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) #// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ) ) # (// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .lut_mask = 64'h3030CFCF00AAFFAA;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y21_N30cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout = ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'hFF00FF0000000000;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y21_N48cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout = ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & (// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) #// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ) #// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & (// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ( (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & (// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ( (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & (// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ( (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .lut_mask = 64'h005500550055F4F5;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y23_N30cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_valid~1 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_018|src_valid~1_combout = ( \u0|mm_interconnect_0|cmd_demux_001|src18_valid~1_combout & ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_demux_001|src18_valid~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_018|src_valid~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_018|src_valid~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_018|src_valid~1 .lut_mask = 64'h0000000000FF00FF;defparam \u0|mm_interconnect_0|cmd_mux_018|src_valid~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y23_N33cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y23_N35dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y23_N9cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout = ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (// \u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & ( !\u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout & (// !\u0|mm_interconnect_0|cmd_mux_018|src_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & ( !\u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_018|src_valid~1_combout ),.datad(gnd),.datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.dataf(!\u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .lut_mask = 64'hFFFFF0F0FFFF0000;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y21_N6cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout = ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & ( (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) ) ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout// & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & ( (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout &// (!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout )) ) ) ) # (// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & (// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & (((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout &// !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1])) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .lut_mask = 64'h0073005000330000;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y21_N39cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) # (// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ( (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout &// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ))) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h0100010055005500;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y21_N42cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout & (// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout &// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout &// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ))) #// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout & (// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .lut_mask = 64'h0F0F0F0F4F0F4F0F;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y21_N44dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y21_N0cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = ( !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & (// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]))) ) ) # ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & (// ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) # ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q &// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// ))))) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "on";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h3030F3F73030F7F7;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y20_N51cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[35] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_018|src_data [35] = ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] ) # ( !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WSTRB// [3]) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [3]),.datad(gnd),.datae(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [35]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_018|src_data[35] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[35] .lut_mask = 64'h0505FFFF0505FFFF;defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[35] .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y20_N53dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_018|src_data [35]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y20_N42cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[34] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_018|src_data [34] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [2] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [2] & (// \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [34]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_018|src_data[34] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[34] .lut_mask = 64'h00FF00FF55FF55FF;defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[34] .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y20_N44dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_018|src_data [34]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y20_N30cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[33] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_018|src_data [33] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [1] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [1] & (// \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),.datac(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),.datad(gnd),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [33]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_018|src_data[33] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[33] .lut_mask = 64'h333333333F3F3F3F;defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[33] .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y20_N32dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_018|src_data [33]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y20_N9cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~2 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~2_combout = ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & (// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] &// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2])) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~2 .lut_mask = 64'hA000A00000000000;defparam \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y20_N3cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[88] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_018|src_data [88] = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2])) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) ) # (// !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [88]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_018|src_data[88] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[88] .lut_mask = 64'h000F000F555F555F;defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[88] .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y20_N45cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[87] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_018|src_data [87] = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1])) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) ) # (// !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [87]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_018|src_data[87] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[87] .lut_mask = 64'h000F000F555F555F;defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[87] .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y20_N54cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = (!\u0|mm_interconnect_0|cmd_mux_018|src_data [88] & !\u0|mm_interconnect_0|cmd_mux_018|src_data [87]).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_018|src_data [88]),.datad(!\u0|mm_interconnect_0|cmd_mux_018|src_data [87]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hF000F000F000F000;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y20_N56dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y20_N30cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & (// (\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout & (!\u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0_combout $ (!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0]))) ) ) ) # (// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout &// (!\u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0_combout $ (!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0])))) # (\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~2_combout ) ) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout ),.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~2_combout ),.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0_combout ),.datad(!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0]),.datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3 .lut_mask = 64'h3773055000000000;defparam \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y20_N24cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & ( (!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) #// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .lut_mask = 64'hF0FFF0FF00000000;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y20_N26dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y21_N24cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3_combout &// ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))) # (\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3_combout &// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & ( ((!\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3_combout &// ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))) # (\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3_combout &// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ) ) ) # (// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & (// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3_combout ),.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h5555FD5D0000FC0C;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y21_N18cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & (// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout & \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]) ) ) # (// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout & \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~0_combout ),.datad(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .lut_mask = 64'h000F000F333F333F;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y21_N14dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y21_N12cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & (// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] $// (((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]))))) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout )))) ) ) # (// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]))) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout )) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .lut_mask = 64'h05AF05AF8D278D27;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y21_N54cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout & (// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ) ) # (// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout// & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout &// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout &// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout &// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ))) ) ) ) # (// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout// ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),.datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'hFFFF0080FFFF0000;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y21_N56dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y21_N33cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1_combout & (// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )) #// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) ) # (// !\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1_combout & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h550F550F55335533;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y21_N18cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout = ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) # ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #// (((!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1])) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ))) ) ) # (// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) #// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout )))) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.datag(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .extended_lut = "on";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .lut_mask = 64'hFFECCCCCFFFFCCCF;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y21_N54cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout = ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .lut_mask = 64'hFFFFFFFF00000000;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y21_N56dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y21_N45cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) ) # (// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q &// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) #// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q $// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ))) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .lut_mask = 64'hA550A55050005000;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y21_N57cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout & (// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout &// ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout &// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datac(gnd),.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h0022002211331133;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y21_N59dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y21_N42cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'hF3F3F3F3F0F0F0F0;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y21_N44dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";// synopsys translate_on// Location: FF_X28_Y20_N26dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y20_N0cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & (// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0 .lut_mask = 64'h000000000F0F0F0F;defparam \u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y20_N18cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1_combout = ( \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0] & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] &// (((\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout & !\u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0_combout )) # (\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ))) ) ) # (// !\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0] & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout &// \u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0_combout )) # (\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ))) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout ),.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ),.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1 .lut_mask = 64'h0C4C0C4C4C0C4C0C;defparam \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y21_N48cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q &// ( \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1_combout ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h000000000F0F0F0F;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y21_N57cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout = (// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] $// (((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h30CF30CF22EE22EE;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y21_N24cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout = (// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout & (// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout &// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .lut_mask = 64'hF000F00000000000;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y21_N51cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & (((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q// ))) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h1113111300000000;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y21_N0cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & (// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )// ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(gnd),.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h0000000033003300;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y21_N45cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) # (// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout & ( (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout &// ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ) #// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ) #// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout )))) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~0_combout ),.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0B0F0B0FFFFFFFFF;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y21_N47dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";// synopsys translate_on// Location: FF_X28_Y21_N20dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y21_N18cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~6 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #// (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][75]~q ))) ) ) # (// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][75]~q ) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(gnd),.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][75]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h0055005522772277;defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y22_N3cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout &// !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0] ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hFFFFFFFF50505050;defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y21_N59dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~6_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";// synopsys translate_on// Location: FF_X28_Y21_N23dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~7_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y21_N21cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~7 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][76]~q ) ) # (// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][76]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h0303030300FF00FF;defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y21_N29dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~7_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";// synopsys translate_on// Location: FF_X28_Y21_N5dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y21_N3cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~5 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]// & ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] &// (((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] &// (((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][74]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h025702578ADF8ADF;defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y21_N17dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~5_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y21_N30cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q $// (((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q ))))) # (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (((\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q $// (((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q ))))) # (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q ),.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q ),.datae(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h00000000D8728D27;defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y21_N32dffeas \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y21_N12cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~0 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~0_combout = !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [4] $ (((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3]// & !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))).dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datab(gnd),.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h5AAA5AAA5AAA5AAA;defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y21_N6cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~0_combout & ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout &// ( (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76]~q $ (((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q ) #// (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q ))))) ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~0_combout & ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout & (// (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76]~q $ (((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q ) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q )))) #// (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ) ) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q ),.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76]~q ),.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q ),.datae(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~0_combout ),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h00000000D75F820A;defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y21_N8dffeas \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";// synopsys translate_on// Location: FF_X28_Y21_N53dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~9_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y21_N51cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~9 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~9_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #// (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # (// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][78]~q ) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(gnd),.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][78]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h0055005522772277;defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y21_N56dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~9_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";// synopsys translate_on// Location: FF_X28_Y21_N50dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~8_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y21_N48cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~8 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~8_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][77]~q ) ) # (// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][77]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h0303030300FF00FF;defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y21_N14dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~8_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y21_N57cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0_combout = (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76]~q & (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77]~q &// (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q & !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q ))).dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76]~q ),.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77]~q ),.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q ),.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0 .lut_mask = 64'h8000800080008000;defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y21_N54cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q & ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77]~q ) ) # (// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q & ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77]~q $ (((!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76]~q &// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76]~q ),.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77]~q ),.datac(gnd),.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h66CC66CCCCCCCCCC;defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y21_N15cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~2 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2]// & (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3])) ) ) # (// !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & ( ((\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) #// (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [4])) # (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h7F7F7F7F80808080;defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y21_N48cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~2_combout & (// (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~1_combout ))// ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~2_combout & ( (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~1_combout ) #// (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~1_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h0F050F050A000A00;defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y21_N50dffeas \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y21_N12cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter// [2] & (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1 .lut_mask = 64'h8080808000000000;defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y21_N36cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78]~q $// ((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0_combout )))) # (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1_combout ))))// ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout & (// (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78]~q $ ((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0_combout )))) #// (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (((\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1_combout )))) ) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78]~q ),.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0_combout ),.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1_combout ),.datae(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h00000000606F6F60;defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y21_N38dffeas \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y21_N21cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (// (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &// !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [6])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hC000C00000000000;defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y21_N47dffeas \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y21_N42cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0_combout & ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout &// ( (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78]~q )) #// (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [6] &// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0_combout & ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout & (// (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [6] &// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78]~q ),.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1_combout ),.datae(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0_combout ),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h00000000003088B8;defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y21_N44dffeas \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y21_N18cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [7] & (// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [7] & (// (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q & ((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1_combout ) # (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter// [2]))) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00AF00AF00FF00FF;defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y21_N51cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout & (// (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q & ((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q ) #// (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) # (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q ) # (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q ),.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q ),.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h00000000DDD0DDD0;defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y21_N53dffeas \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";// synopsys translate_on// Location: FF_X27_Y20_N34dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";// synopsys translate_on// Location: FF_X28_Y20_N23dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y20_N21cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3_combout = (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66])) #// (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][66]~q ))).dataa(gnd),.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][66]~q ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h0C3F0C3F0C3F0C3F;defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y22_N20dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y21_N24cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~0 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~0_combout = ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q & ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77]~q & (// (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78]~q & (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q & (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76]~q &// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78]~q ),.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q ),.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76]~q ),.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q ),.datae(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q ),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0080000000000000;defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y21_N3cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1_combout & ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~0_combout & (// (!\u0|mm_interconnect_0|clock_sel_s1_agent|comb~0_combout & \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q ) ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1_combout & (// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~0_combout & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent|comb~0_combout & \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q ) ) ) ) # (// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1_combout & ( !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~0_combout & ( (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q &// ((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) # ((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q ) # (!\u0|mm_interconnect_0|clock_sel_s1_agent|comb~0_combout )))) ) ) ) # (// !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1_combout & ( !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~0_combout & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q ) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q ),.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|comb~0_combout ),.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q ),.datae(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1_combout ),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00FF00FE00F000F0;defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y22_N57cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0_combout & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &// ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~4_combout ))) ) ) ) # (// !\u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0_combout & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] &// (\u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0_combout & ((\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~4_combout )))) ) ) ) # (// \u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0_combout & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] &// ((\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~4_combout ))) ) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~4_combout ),.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ),.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent|local_write~0_combout ),.datae(!\u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0_combout ),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h0000707000707070;defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y22_N0cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[1]~0 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0_combout & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout &// (((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0])))) # (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout & ((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout &// ((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout & (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0])))) ) ) # (// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0_combout & ( (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ) #// (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ))) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ),.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[1]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h00BB00BB0B4F0B4F;defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y22_N2dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[1]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y24_N9cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~21 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~21_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][116]~q & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] ) ) # (// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][116]~q & ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) )// ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][116]~q & ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg// [116] ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.datad(gnd),.datae(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][116]~q ),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~21_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~21 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~21 .lut_mask = 64'h0F0F0F0F0000FFFF;defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~21 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y26_N2dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~21_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y23_N15cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[116] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_015|src_data [116] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [11])) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) ) ) # (// !\u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [11]) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),.datad(!\u0|hps_0|fpga_interfaces|h2f_AWID [11]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [116]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_015|src_data[116] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[116] .lut_mask = 64'h005500550F5F0F5F;defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[116] .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y23_N17dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_015|src_data [116]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";// synopsys translate_on// Location: FF_X18_Y23_N35dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y23_N33cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][116]~q & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] ) ) # (// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][116]~q & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][116]~q & (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.datad(gnd),.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][116]~q ),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21 .lut_mask = 64'h0F0F0F0F0000FFFF;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y19_N57cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_015|WideOr0~0 (// Equation(s):// \u0|mm_interconnect_0|rsp_demux_015|WideOr0~0_combout = ( \u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout & ( \u0|hps_0|fpga_interfaces|h2f_BREADY [0] ) ) # ( !\u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout & (// \u0|hps_0|fpga_interfaces|h2f_RREADY [0] ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|rsp_demux_015|WideOr0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|rsp_demux_015|WideOr0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|rsp_demux_015|WideOr0~0 .lut_mask = 64'h0F0F0F0F55555555;defparam \u0|mm_interconnect_0|rsp_demux_015|WideOr0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y21_N14dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y21_N0cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0 .lut_mask = 64'h0000000033333333;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y21_N51cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~1_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~0_combout & (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~1 .lut_mask = 64'h00000000FF00FF00;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y21_N53dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y21_N12cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout &// \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0]) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout &// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0] $ (((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout ) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]))))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4 .lut_mask = 64'h0451045100550055;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y19_N39cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~1_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4_combout & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~0_combout// ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~0_combout ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h0000000055555555;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y19_N41dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg[0] .power_up = "low";// synopsys translate_on// Location: FF_X19_Y19_N32dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";// synopsys translate_on// Location: FF_X21_Y21_N29dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y21_N42cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0 .lut_mask = 64'h000000000FFF0FFF;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y19_N30cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~0_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][129]~q & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout & (// (((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout & \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout )) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1])) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][129]~q & (// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout &// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout )) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout ))) ) ) ) # (// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][129]~q & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout & ( ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout &// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout )) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][129]~q & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] &// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout & \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][129]~q ),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h000C333F444C777F;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y19_N57cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~feeder (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~feeder_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~0_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y19_N59dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y19_N12cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0] & ( ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0] &// !\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0] & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0] & !\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0]) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0]),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0]),.datac(gnd),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h8888888888FF88FF;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y19_N9cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~1_combout = ( \u0|mm_interconnect_0|rsp_demux_015|WideOr0~0_combout & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0_combout ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\u0|mm_interconnect_0|rsp_demux_015|WideOr0~0_combout ),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~1 .lut_mask = 64'h0000FFFF00000000;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y19_N36cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[1]~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~1_combout & ( ((\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0] &// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [1]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0]),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h03FF03FF00000000;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y19_N38dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y19_N27cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[0]~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~1_combout & ( ((\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0] &// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~1_combout & (// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [1] & \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0]) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0]),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h0AFF0AFF555F555F;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y19_N29dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y19_N24cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~q & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0] & (// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0] ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~q & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0] & (// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0] ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~q & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0] & (// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0] ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~q & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0] & (// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0] & \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0]) ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0]),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0]),.datad(gnd),.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~q ),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0 .lut_mask = 64'h0303333333333333;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y19_N18cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout = ( \u0|mm_interconnect_0|rsp_demux_015|WideOr0~0_combout & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0_combout ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\u0|mm_interconnect_0|rsp_demux_015|WideOr0~0_combout ),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0 .lut_mask = 64'h000000000000FFFF;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y19_N48cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4_combout & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4_combout & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout ) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout & (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4_combout & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] &// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout )))) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4_combout & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout &// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~0_combout ),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h040404440C0C0CCC;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y19_N12cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[0]~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ) )// # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0_combout ) ) )// # ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ) # ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0_combout )) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),.datad(gnd),.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0]),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h3333BFBF3333FFFF;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y19_N14dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y19_N39cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ) # (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0]) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0] ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hF0F0F0F0FCFCFCFC;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y26_N44dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y19_N15cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid~combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0] &// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~q )) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0] & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0] & !\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0]) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0]),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0]),.datac(gnd),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid .lut_mask = 64'h8888888888008800;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y22_N3cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_015|src1_valid (// Equation(s):// \u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout = (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid~combout & !\u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid~combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout ),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|rsp_demux_015|src1_valid .extended_lut = "off";defparam \u0|mm_interconnect_0|rsp_demux_015|src1_valid .lut_mask = 64'hA0A0A0A0A0A0A0A0;defparam \u0|mm_interconnect_0|rsp_demux_015|src1_valid .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y26_N42cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~202 (// Equation(s):// \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~202_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116]~q & ( \u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116]~q & ( \u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout & ( (\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout &// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116]~q ) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116]~q & ( !\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout & (// (\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout & \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116]~q ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116]~q & (// !\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout & ( (\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout & \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116]~q ) ) ) ).dataa(!\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116]~q ),.datad(gnd),.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116]~q ),.dataf(!\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~202_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~202 .extended_lut = "off";defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~202 .lut_mask = 64'h050505050505FFFF;defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~202 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y31_N45cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal18~0 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal18~0_combout = ( \u0|mm_interconnect_0|router_001|Equal7~0_combout & ( (\u0|mm_interconnect_0|router_001|Equal1~0_combout & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] &// (\u0|mm_interconnect_0|router_001|Equal1~2_combout & \u0|mm_interconnect_0|router_001|Equal1~1_combout ))) ) ).dataa(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),.datac(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),.datad(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|router_001|Equal7~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal18~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal18~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal18~0 .lut_mask = 64'h0000000000010001;defparam \u0|mm_interconnect_0|router_001|Equal18~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y31_N10dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[12] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|router_001|Equal18~0_combout ),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [12]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[12] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[12] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y32_N3cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout = ( \u0|mm_interconnect_0|router_001|Equal18~0_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) #// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [12]))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [12]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|router_001|Equal18~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0 .lut_mask = 64'h000000000C0F0C0F;defparam \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y32_N39cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y32_N41dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y32_N27cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout & ( (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datad(gnd),.datae(!\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000050500000000;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y32_N29dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";// synopsys translate_on// Location: FF_X15_Y32_N47dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";// synopsys translate_on// Location: FF_X15_Y31_N11dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";// synopsys translate_on// Location: FF_X11_Y35_N5dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X11_Y35_N51cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X11_Y35_N53dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X11_Y35_N0cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]// $ (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2] $ (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1])) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .lut_mask = 64'h1BB11BB10AA00AA0;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X11_Y35_N2dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X11_Y35_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout = (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout )))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] &// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q// & (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout )))) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (// !\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.dataf(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .lut_mask = 64'h0808A2A2085DA2F7;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X11_Y35_N56dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X11_Y35_N9cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $// (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]))) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datac(gnd),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hAAAAAAAA66AA66AA;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X11_Y35_N3cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout = (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .lut_mask = 64'hABABABAB01010101;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X11_Y35_N6cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] &// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h0A000A0000000000;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X11_Y35_N50dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X11_Y35_N48cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout = ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout $// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] &// ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout $// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) ) ).dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .lut_mask = 64'h30C030C035C535C5;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y32_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout// & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout &// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout )) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h0000000010101010;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y31_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h000000000CCC0CCC;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y32_N51cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout = (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h55AF55AF50AA50AA;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y32_N53dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y32_N39cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout = (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h54AE54AE04FE04FE;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y32_N41dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y32_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout = (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) ) ) ) # (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h0B03F7FF0800F4FC;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y32_N14dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y32_N48cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h4040404000000000;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y32_N36cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout = (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .lut_mask = 64'h04FE04FEF40EF40E;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y32_N38dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";// synopsys translate_on// Location: FF_X13_Y32_N31dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y32_N30cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout = (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) ) ) # (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .lut_mask = 64'h0044FFEEF0440FEE;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y32_N0cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout = (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout )) ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .lut_mask = 64'hC000000000000000;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y32_N15cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h004400440F4F0F4F;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y32_N17dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y32_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout = ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h0000000000030003;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y32_N57cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout &// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q &// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout )))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h0045004555555555;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y32_N59dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y32_N51cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout = (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q $// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .lut_mask = 64'hC000C0003CC03CC0;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y32_N45cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0F4F0F4F00440044;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y32_N47dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y32_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout = (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'hFF00FF0000000000;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y32_N44dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y32_N33cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q// )) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q// ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h00AA00AA000A000A;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y32_N9cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] &// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ).dataa(gnd),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFFFFFFFFF000F000;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y32_N11dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";// synopsys translate_on// Location: FF_X15_Y32_N8dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";// synopsys translate_on// Location: FF_X15_Y32_N50dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";// synopsys translate_on// Location: FF_X15_Y32_N41dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y32_N48cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1_combout = ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1])) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1 .lut_mask = 64'hA000A00000000000;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y32_N6cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1_combout & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ))) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1_combout & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2 .lut_mask = 64'h0F000F00CF00CF00;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X11_Y32_N33cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hFFFFFFFF00000000;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y32_N52dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y32_N51cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2_combout &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2_combout ))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h3303330330003000;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y32_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & ( (!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]) # ((!\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ) #// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout// ))) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.datab(!\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hFFEFFFEF00000000;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X11_Y35_N20dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X11_Y35_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout = (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1])) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout )))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1])) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .lut_mask = 64'h00A0AA0A11B1BB1B;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X11_Y35_N24cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout & (// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h00FF80FF00FF00FF;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X11_Y35_N26dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y32_N45cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )// # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )// # ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q// & \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout &// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ))) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h02000303CECCCFCF;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y32_N30cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1])) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h0500050055005500;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y32_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout = (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout// ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .lut_mask = 64'hFF00FF00F000F000;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y32_N15cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( ((\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & (\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & (\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.datab(!\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h001100110F1F0F1F;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y32_N17dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y31_N9cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h0000000030F030F0;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y31_N39cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y31_N41dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y31_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~q & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout// & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout & \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [0])) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [0]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0000000002020202;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y31_N20dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y31_N36cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout & ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0 .lut_mask = 64'h000000000F0F0F0F;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y31_N45cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout & \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h000F000F0F0F0F0F;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y31_N3cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0]~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0] & (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1])) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h00F700F7FFFFFFFF;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y31_N5dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: FF_X15_Y31_N2dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y31_N0cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout & ( ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][129]~q )) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][129]~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][129]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h003300330F3F0F3F;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y31_N30cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout = (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]) # ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout )).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hBABABABABABABABA;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y31_N26dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y31_N27cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout = ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q & (// (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]))) ) ) ) # (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] &// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0] & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]))) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h050F050F050F0000;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y31_N51cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1]~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout &// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]))) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout & \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [1]) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h00F000F050F050F0;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y31_N53dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y31_N48cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0]~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]// & \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout & (// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [1])) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h50FF50FF0F5F0F5F;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y31_N50dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y31_N6cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0] ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0 .lut_mask = 64'h005F005F00FF00FF;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y32_N23dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y32_N21cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h0505050500FF00FF;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y32_N11dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";// synopsys translate_on// Location: FF_X13_Y32_N59dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y32_N57cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][75]~q ))) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][75]~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][75]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h003300330C3F0C3F;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y32_N59dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";// synopsys translate_on// Location: FF_X13_Y32_N20dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y32_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &// (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &// (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][74]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h043704378CBF8CBF;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y32_N35dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";// synopsys translate_on// Location: FF_X13_Y32_N56dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y32_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][77]~q ))) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][77]~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][77]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h003300330C3F0C3F;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y32_N32dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y32_N30cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout = (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ))).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0 .lut_mask = 64'h8000800080008000;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y32_N23dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y32_N57cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h0000000055555555;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y32_N48cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q )) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h3000300030303030;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y32_N50dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y32_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4])) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3])) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h7F7F7F7F80808080;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y32_N33cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1_combout = !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77]~q $ (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q )))).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h78F078F078F078F0;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y32_N15cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1_combout & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2_combout )) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1_combout & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ) #// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2_combout ))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h0F0A0F0A05000500;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y32_N17dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y32_N27cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3])) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1 .lut_mask = 64'h8080808000000000;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y32_N29dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y32_N27cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][78]~q & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][78]~q & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][78]~q & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datad(gnd),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h00000F0F50505F5F;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y32_N56dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y32_N0cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout )) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout ))))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout )) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout ))))) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout )) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout ))))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout )) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout ))))) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h1103113022032230;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y32_N2dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y32_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6])) ) ) ) # (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout ))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6])))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout ),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout ),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h0022103200001010;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y32_N19dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y32_N51cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00AF00AF00FF00FF;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y32_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q )) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q )) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q )) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q )) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h00D8008D00720027;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y32_N44dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y32_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] $ (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datac(gnd),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h33CC33CCFF00FF00;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y32_N36cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0_combout )) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q $ (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q )))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h0000CA3A00003A3A;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y32_N38dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y32_N24cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6])) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'h8080808000000000;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y32_N6cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout = ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0000000080000000;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y30_N20dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y30_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h00550055AAFFAAFF;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y30_N36cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~feeder (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~feeder_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y30_N38dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y30_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~q & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout ) #// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout )) ) ) ) # (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~q & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout ) #// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout ) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout ),.datad(gnd),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h0000FAFA0000EAEA;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y31_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1]~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used// [0]))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1])))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0])))) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h331133110F270F27;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y31_N14dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y31_N15cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ))) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFFFFFFFF0CCC0CCC;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y32_N30cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q// & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) ) ) ) # (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datad(gnd),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h03030F0F00000C0C;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y32_N32dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y32_N24cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout = ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg// [1] & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q &// ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]// & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3])) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0 .lut_mask = 64'hA000000080000000;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y31_N21cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~0_combout = (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout &// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~q & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [0]))).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~q ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [0]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~0 .lut_mask = 64'h0200020002000200;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y31_N23dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y31_N33cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~q & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [0] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0 .lut_mask = 64'h0000000000FF00FF;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y32_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout &// (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout )) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ))) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .lut_mask = 64'hCC4CCC0000000000;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y32_N21cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q// & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .lut_mask = 64'h5D555D5508000800;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y32_N36cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout = (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout &// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .lut_mask = 64'hA080A000A080A000;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y32_N0cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout & (// ((\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout & \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~q ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout & ( (\u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~q & ((!\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ) #// (!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]))) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.datad(!\u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~0 .lut_mask = 64'h00FA00FA05FF05FF;defparam \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y32_N2dffeas \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y32_N48cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|update_grant~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_012|update_grant~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout & ( (!\u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~q &// ((!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]) # (!\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ))) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout// & ( (!\u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~q ) # ((\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout )) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.datad(!\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_012|update_grant~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_012|update_grant~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_012|update_grant~0 .lut_mask = 64'hAAAFAAAFAAA0AAA0;defparam \u0|mm_interconnect_0|cmd_mux_012|update_grant~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y32_N50dffeas \u0|mm_interconnect_0|cmd_mux_012|saved_grant[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|cmd_mux_012|update_grant~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_012|saved_grant[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|cmd_mux_012|saved_grant[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X11_Y32_N42cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~11 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_012|src_payload~11_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.datad(gnd),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~11 .lut_mask = 64'h000000000F0F0F0F;defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X11_Y32_N43dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_012|src_payload~11_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";// synopsys translate_on// Location: FF_X13_Y32_N44dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y32_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][116]~q & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] ) ) # (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][116]~q & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][116]~q & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.datad(gnd),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][116]~q ),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h0F0F0F0F0000FFFF;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y30_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~feeder (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~feeder_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y30_N19dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y31_N3cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal1~5 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal1~5_combout = ( \u0|mm_interconnect_0|router_001|Equal1~4_combout & ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] ) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\u0|mm_interconnect_0|router_001|Equal1~4_combout ),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal1~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal1~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal1~5 .lut_mask = 64'h0000AAAA00000000;defparam \u0|mm_interconnect_0|router_001|Equal1~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y31_N1dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|router_001|Equal1~5_combout ),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y27_N51cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q & ( \u0|mm_interconnect_0|router_001|Equal1~4_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] &// (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [1]))) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q// & ( \u0|mm_interconnect_0|router_001|Equal1~4_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [19])) ) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),.datab(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [1]),.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),.dataf(!\u0|mm_interconnect_0|router_001|Equal1~4_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0 .lut_mask = 64'h0000000020200020;defparam \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X11_Y23_N18cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X11_Y23_N20dffeas \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: LABCELL_X11_Y23_N42cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~q & ( \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [0] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [0]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0 .lut_mask = 64'h000000000F0F0F0F;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y23_N51cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y23_N53dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y23_N45cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used// [1] & \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout & (// (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout// )) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h0202020222222222;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X11_Y20_N12cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X11_Y20_N14dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y20_N33cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg// [2])))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]))) ) ) # (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]))) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .lut_mask = 64'h10DC10DCDC10DC10;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y20_N35dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y20_N54cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout = (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) #// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (((\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1])))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))))// # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1])))) ) ) ) # (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ) ) # (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datac(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .lut_mask = 64'h0088CC44038BCF47;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y20_N56dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";// synopsys translate_on// Location: FF_X13_Y20_N32dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y20_N15cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) ) ) # (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & ( ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg// [2]) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hF5FFF5FF0A000A00;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y20_N30cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout &// ( (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ) # (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #// ((\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datac(gnd),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .lut_mask = 64'hCCDDCCDD00110011;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y20_N27cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] &// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h5000500000000000;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y20_N39cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout = ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout $// (((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout )))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout $ (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .lut_mask = 64'h44884488478B478B;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y20_N41dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";// synopsys translate_on// Location: FF_X13_Y20_N2dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y20_N0cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout = (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) #// ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (((\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1])))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) #// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1])))) ) ) ) # (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) #// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) ) ) ) # (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & (// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] &// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.datac(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .lut_mask = 64'h4400BB00440FBB0F;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y23_N30cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout = ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & (// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout )) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datad(!\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h0000000000030003;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y23_N9cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout & (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout & (// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q &// ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout// )))) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h0045004555555555;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y23_N11dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";// synopsys translate_on// Location: LABCELL_X11_Y23_N54cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q// & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h0000000030F030F0;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y23_N3cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout = (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [2]))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h00FF00FFFA0AFA0A;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y23_N5dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y23_N0cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout = (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]// $ (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) #// ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h00FF00FFE22EE22E;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y23_N2dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y23_N12cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout = (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [2])) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) )// ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]// & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) )// ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h0000FFFFB3807F4C;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y23_N14dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y23_N36cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [2])) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h5000500000000000;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y23_N41dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y23_N39cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout = (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout $ (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout $// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [5])) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ))) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .lut_mask = 64'h1DF31DF30CE20CE2;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y23_N19dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y23_N18cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout = (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]// & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) )// ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) #// ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [5] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout// )))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [5] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ))))// # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .lut_mask = 64'h10DCFE321010FEFE;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y23_N30cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout = (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout &// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout &// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout &// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ))) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .lut_mask = 64'h8000800000000000;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y23_N48cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout &// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout &// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ))).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h0010001000100010;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y23_N6cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout & (// ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ) ) ) # (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout & ( (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout &// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) )// ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h004400440F4F0F4F;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y23_N8dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y23_N24cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout = ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q// & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'hCCCCCCCC00000000;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y23_N6cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_001|saved_grant// [1] & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout & \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000000004040404;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y23_N17dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y23_N42cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q &// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout )) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h0C0C0C0C000C000C;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y23_N36cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout = !\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1].dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hF0F0F0F0F0F0F0F0;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y23_N38dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";// synopsys translate_on// Location: FF_X14_Y23_N5dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";// synopsys translate_on// Location: FF_X14_Y23_N38dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";// synopsys translate_on// Location: FF_X14_Y23_N55dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y23_N54cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1_combout = ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] &// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0])) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1 .lut_mask = 64'hA000A00000000000;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y23_N39cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] &// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] ).dataa(gnd),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFFFFFFFFF000F000;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y23_N41dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y23_N36cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] ) ) # (// !\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1_combout & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q &// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1])) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1_combout ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.datac(gnd),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2 .lut_mask = 64'h44004400FF00FF00;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y23_N21cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// (!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2_combout & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))) #// (\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2_combout & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h00000000F0CCF0CC;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y23_N27cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) #// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout & (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ( !\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout & (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ( !\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout & (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.datae(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.dataf(!\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hFF00FF00FF00AF00;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y20_N42cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ) ) # (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout &// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout &// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout &// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ))) ) ) ) # (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),.datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h0000FFFF8000FFFF;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y20_N44dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y23_N57cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) #// ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .lut_mask = 64'hFF00FF00F000F000;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y23_N51cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// (((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout )) #// (\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ( (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.datad(!\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h0303030303570357;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y23_N53dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X11_Y23_N21cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (// (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ))) ) ) # (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFFFFFFFF0AAA0AAA;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y23_N51cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout// & ( ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout &// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0F4F0F4F00440044;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y23_N53dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y23_N27cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q $ (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ))) #// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .lut_mask = 64'h8080808068686868;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y23_N57cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout & ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h0555055500500050;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y23_N59dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y23_N0cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #// (((!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout & !\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout )) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1])) ) ) ) # (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q// & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & ( (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// (((!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout & !\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout )) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]))) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ),.datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h00002303CCCCEFCF;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y23_N48cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q// & ( (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ) # (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q// & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) #// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )))) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .lut_mask = 64'h7430743030303030;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y23_N12cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q &// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout &// (((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # (\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout )) # (\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout )))// ) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .lut_mask = 64'hF700F00000000000;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y23_N18cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout = ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) #// ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .lut_mask = 64'hF080F08000000000;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y23_N33cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~0_combout = ( \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ) ) #// ( !\u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout & ( (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] &// \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout & (// (!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]) # (!\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ) ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ),.datad(gnd),.datae(!\u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q ),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~0 .lut_mask = 64'h0000FAFA0505FFFF;defparam \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y23_N35dffeas \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y23_N21cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|update_grant~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_001|update_grant~0_combout = ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout & (// (!\u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q & !\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout & ( !\u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout & ( (!\u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q ) # (\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ) ) ) ) # (// !\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout & ( !\u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ),.datad(gnd),.datae(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_001|update_grant~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_001|update_grant~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_001|update_grant~0 .lut_mask = 64'hAAAAAFAFAAAAA0A0;defparam \u0|mm_interconnect_0|cmd_mux_001|update_grant~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y23_N23dffeas \u0|mm_interconnect_0|cmd_mux_001|saved_grant[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|cmd_mux_001|update_grant~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_001|saved_grant[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|cmd_mux_001|saved_grant[1] .power_up = "low";// synopsys translate_on// Location: FF_X14_Y23_N35dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y23_N24cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout = ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] &// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] &// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] &// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1])) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0 .lut_mask = 64'h8080000080000000;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X11_Y23_N33cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~q & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout &// (!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout & !\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [0])) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~0 .lut_mask = 64'h0000000050005000;defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X11_Y23_N35dffeas \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X11_Y23_N24cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~q & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout &// (\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [0] & !\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout )) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [0]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0000000005000500;defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X11_Y23_N26dffeas \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg[0] .power_up = "low";// synopsys translate_on// Location: FF_X11_Y23_N38dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";// synopsys translate_on// Location: LABCELL_X11_Y23_N36cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout &// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout )) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][129]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & (// (\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout & \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][129]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h0303030303FF03FF;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X11_Y23_N30cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0_combout & ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0 .lut_mask = 64'h0000000000FF00FF;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X11_Y23_N57cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0]) #// (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0] ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hAAAAAAAAFAFAFAFA;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X11_Y23_N59dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";// synopsys translate_on// Location: LABCELL_X11_Y23_N45cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q// & ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0])))) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0] & (// (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]))) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),.datab(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h1313131313001300;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X11_Y23_N6cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1]~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] &// \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h03FF03FF00000000;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X11_Y23_N8dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X11_Y23_N39cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0]~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] &// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout & (// ((\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1])) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h50FF50FF0F5F0F5F;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X11_Y23_N41dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X11_Y23_N9cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0] ) ) # (// !\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q ) #// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]))) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0]),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),.datac(gnd),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0 .lut_mask = 64'h1155115555555555;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y23_N29dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";// synopsys translate_on// Location: FF_X13_Y23_N47dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y23_N45cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][77]~q ) ) # (// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][77]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h0505050500FF00FF;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y23_N53dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";// synopsys translate_on// Location: FF_X14_Y23_N29dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y23_N33cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]))) #// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][76]~q )) ) ) # (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][76]~q &// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][76]~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h005500550F550F55;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y23_N32dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";// synopsys translate_on// Location: FF_X13_Y23_N44dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~8_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y23_N42cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~8 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~8_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #// ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] &// (((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] &// (((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][74]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h043704378CBF8CBF;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y23_N17dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~8_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";// synopsys translate_on// Location: FF_X15_Y23_N50dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y23_N48cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][75]~q ))) ) ) # (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][75]~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][75]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h000F000F303F303F;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y23_N8dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";// synopsys translate_on// Location: LABCELL_X10_Y23_N15cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77]~q ) ) # (// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77]~q $ (((!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q &// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77]~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h5AAA5AAAAAAAAAAA;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X10_Y23_N18cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout &// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout &// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout & (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q// $ (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout & (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q// $ (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q ),.datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h4411441150500505;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y23_N20dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X10_Y21_N15cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0_combout = ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] ) ) ) # (// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] ) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h5555AAAAFFFF0000;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X10_Y23_N42cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q// & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q )) #// (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0_combout ))) ) ) ) # (// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q & (// (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q $ (((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q ))))) #// (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (((!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0_combout )))) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q ),.datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0000D87200007272;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y23_N44dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),