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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [ulight_fifo/] [synthesis/] [submodules/] [ulight_fifo_mm_interconnect_0.v] - Rev 32

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// ulight_fifo_mm_interconnect_0.v
 
// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 17.0 598
 
`timescale 1 ps / 1 ps
module ulight_fifo_mm_interconnect_0 (
		input  wire [11:0] hps_0_h2f_axi_master_awid,                                        //                                       hps_0_h2f_axi_master.awid
		input  wire [29:0] hps_0_h2f_axi_master_awaddr,                                      //                                                           .awaddr
		input  wire [3:0]  hps_0_h2f_axi_master_awlen,                                       //                                                           .awlen
		input  wire [2:0]  hps_0_h2f_axi_master_awsize,                                      //                                                           .awsize
		input  wire [1:0]  hps_0_h2f_axi_master_awburst,                                     //                                                           .awburst
		input  wire [1:0]  hps_0_h2f_axi_master_awlock,                                      //                                                           .awlock
		input  wire [3:0]  hps_0_h2f_axi_master_awcache,                                     //                                                           .awcache
		input  wire [2:0]  hps_0_h2f_axi_master_awprot,                                      //                                                           .awprot
		input  wire        hps_0_h2f_axi_master_awvalid,                                     //                                                           .awvalid
		output wire        hps_0_h2f_axi_master_awready,                                     //                                                           .awready
		input  wire [11:0] hps_0_h2f_axi_master_wid,                                         //                                                           .wid
		input  wire [31:0] hps_0_h2f_axi_master_wdata,                                       //                                                           .wdata
		input  wire [3:0]  hps_0_h2f_axi_master_wstrb,                                       //                                                           .wstrb
		input  wire        hps_0_h2f_axi_master_wlast,                                       //                                                           .wlast
		input  wire        hps_0_h2f_axi_master_wvalid,                                      //                                                           .wvalid
		output wire        hps_0_h2f_axi_master_wready,                                      //                                                           .wready
		output wire [11:0] hps_0_h2f_axi_master_bid,                                         //                                                           .bid
		output wire [1:0]  hps_0_h2f_axi_master_bresp,                                       //                                                           .bresp
		output wire        hps_0_h2f_axi_master_bvalid,                                      //                                                           .bvalid
		input  wire        hps_0_h2f_axi_master_bready,                                      //                                                           .bready
		input  wire [11:0] hps_0_h2f_axi_master_arid,                                        //                                                           .arid
		input  wire [29:0] hps_0_h2f_axi_master_araddr,                                      //                                                           .araddr
		input  wire [3:0]  hps_0_h2f_axi_master_arlen,                                       //                                                           .arlen
		input  wire [2:0]  hps_0_h2f_axi_master_arsize,                                      //                                                           .arsize
		input  wire [1:0]  hps_0_h2f_axi_master_arburst,                                     //                                                           .arburst
		input  wire [1:0]  hps_0_h2f_axi_master_arlock,                                      //                                                           .arlock
		input  wire [3:0]  hps_0_h2f_axi_master_arcache,                                     //                                                           .arcache
		input  wire [2:0]  hps_0_h2f_axi_master_arprot,                                      //                                                           .arprot
		input  wire        hps_0_h2f_axi_master_arvalid,                                     //                                                           .arvalid
		output wire        hps_0_h2f_axi_master_arready,                                     //                                                           .arready
		output wire [11:0] hps_0_h2f_axi_master_rid,                                         //                                                           .rid
		output wire [31:0] hps_0_h2f_axi_master_rdata,                                       //                                                           .rdata
		output wire [1:0]  hps_0_h2f_axi_master_rresp,                                       //                                                           .rresp
		output wire        hps_0_h2f_axi_master_rlast,                                       //                                                           .rlast
		output wire        hps_0_h2f_axi_master_rvalid,                                      //                                                           .rvalid
		input  wire        hps_0_h2f_axi_master_rready,                                      //                                                           .rready
		input  wire        clk_0_clk_clk,                                                    //                                                  clk_0_clk.clk
		input  wire        hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset, // hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
		input  wire        led_pio_test_reset_reset_bridge_in_reset_reset,                   //                   led_pio_test_reset_reset_bridge_in_reset.reset
		output wire [1:0]  auto_start_s1_address,                                            //                                              auto_start_s1.address
		output wire        auto_start_s1_write,                                              //                                                           .write
		input  wire [31:0] auto_start_s1_readdata,                                           //                                                           .readdata
		output wire [31:0] auto_start_s1_writedata,                                          //                                                           .writedata
		output wire        auto_start_s1_chipselect,                                         //                                                           .chipselect
		output wire [1:0]  clock_sel_s1_address,                                             //                                               clock_sel_s1.address
		output wire        clock_sel_s1_write,                                               //                                                           .write
		input  wire [31:0] clock_sel_s1_readdata,                                            //                                                           .readdata
		output wire [31:0] clock_sel_s1_writedata,                                           //                                                           .writedata
		output wire        clock_sel_s1_chipselect,                                          //                                                           .chipselect
		output wire [1:0]  counter_rx_fifo_s1_address,                                       //                                         counter_rx_fifo_s1.address
		input  wire [31:0] counter_rx_fifo_s1_readdata,                                      //                                                           .readdata
		output wire [1:0]  counter_tx_fifo_s1_address,                                       //                                         counter_tx_fifo_s1.address
		input  wire [31:0] counter_tx_fifo_s1_readdata,                                      //                                                           .readdata
		output wire [1:0]  data_flag_rx_s1_address,                                          //                                            data_flag_rx_s1.address
		input  wire [31:0] data_flag_rx_s1_readdata,                                         //                                                           .readdata
		output wire [1:0]  data_info_s1_address,                                             //                                               data_info_s1.address
		input  wire [31:0] data_info_s1_readdata,                                            //                                                           .readdata
		output wire [1:0]  data_read_en_rx_s1_address,                                       //                                         data_read_en_rx_s1.address
		output wire        data_read_en_rx_s1_write,                                         //                                                           .write
		input  wire [31:0] data_read_en_rx_s1_readdata,                                      //                                                           .readdata
		output wire [31:0] data_read_en_rx_s1_writedata,                                     //                                                           .writedata
		output wire        data_read_en_rx_s1_chipselect,                                    //                                                           .chipselect
		output wire [1:0]  fifo_empty_rx_status_s1_address,                                  //                                    fifo_empty_rx_status_s1.address
		input  wire [31:0] fifo_empty_rx_status_s1_readdata,                                 //                                                           .readdata
		output wire [1:0]  fifo_empty_tx_status_s1_address,                                  //                                    fifo_empty_tx_status_s1.address
		input  wire [31:0] fifo_empty_tx_status_s1_readdata,                                 //                                                           .readdata
		output wire [1:0]  fifo_full_rx_status_s1_address,                                   //                                     fifo_full_rx_status_s1.address
		input  wire [31:0] fifo_full_rx_status_s1_readdata,                                  //                                                           .readdata
		output wire [1:0]  fifo_full_tx_status_s1_address,                                   //                                     fifo_full_tx_status_s1.address
		input  wire [31:0] fifo_full_tx_status_s1_readdata,                                  //                                                           .readdata
		output wire [1:0]  fsm_info_s1_address,                                              //                                                fsm_info_s1.address
		input  wire [31:0] fsm_info_s1_readdata,                                             //                                                           .readdata
		output wire [1:0]  led_pio_test_s1_address,                                          //                                            led_pio_test_s1.address
		output wire        led_pio_test_s1_write,                                            //                                                           .write
		input  wire [31:0] led_pio_test_s1_readdata,                                         //                                                           .readdata
		output wire [31:0] led_pio_test_s1_writedata,                                        //                                                           .writedata
		output wire        led_pio_test_s1_chipselect,                                       //                                                           .chipselect
		output wire [1:0]  link_disable_s1_address,                                          //                                            link_disable_s1.address
		output wire        link_disable_s1_write,                                            //                                                           .write
		input  wire [31:0] link_disable_s1_readdata,                                         //                                                           .readdata
		output wire [31:0] link_disable_s1_writedata,                                        //                                                           .writedata
		output wire        link_disable_s1_chipselect,                                       //                                                           .chipselect
		output wire [1:0]  link_start_s1_address,                                            //                                              link_start_s1.address
		output wire        link_start_s1_write,                                              //                                                           .write
		input  wire [31:0] link_start_s1_readdata,                                           //                                                           .readdata
		output wire [31:0] link_start_s1_writedata,                                          //                                                           .writedata
		output wire        link_start_s1_chipselect,                                         //                                                           .chipselect
		output wire [1:0]  timecode_ready_rx_s1_address,                                     //                                       timecode_ready_rx_s1.address
		input  wire [31:0] timecode_ready_rx_s1_readdata,                                    //                                                           .readdata
		output wire [1:0]  timecode_rx_s1_address,                                           //                                             timecode_rx_s1.address
		input  wire [31:0] timecode_rx_s1_readdata,                                          //                                                           .readdata
		output wire [1:0]  timecode_tx_data_s1_address,                                      //                                        timecode_tx_data_s1.address
		output wire        timecode_tx_data_s1_write,                                        //                                                           .write
		input  wire [31:0] timecode_tx_data_s1_readdata,                                     //                                                           .readdata
		output wire [31:0] timecode_tx_data_s1_writedata,                                    //                                                           .writedata
		output wire        timecode_tx_data_s1_chipselect,                                   //                                                           .chipselect
		output wire [1:0]  timecode_tx_enable_s1_address,                                    //                                      timecode_tx_enable_s1.address
		output wire        timecode_tx_enable_s1_write,                                      //                                                           .write
		input  wire [31:0] timecode_tx_enable_s1_readdata,                                   //                                                           .readdata
		output wire [31:0] timecode_tx_enable_s1_writedata,                                  //                                                           .writedata
		output wire        timecode_tx_enable_s1_chipselect,                                 //                                                           .chipselect
		output wire [1:0]  timecode_tx_ready_s1_address,                                     //                                       timecode_tx_ready_s1.address
		input  wire [31:0] timecode_tx_ready_s1_readdata,                                    //                                                           .readdata
		output wire [1:0]  write_data_fifo_tx_s1_address,                                    //                                      write_data_fifo_tx_s1.address
		output wire        write_data_fifo_tx_s1_write,                                      //                                                           .write
		input  wire [31:0] write_data_fifo_tx_s1_readdata,                                   //                                                           .readdata
		output wire [31:0] write_data_fifo_tx_s1_writedata,                                  //                                                           .writedata
		output wire        write_data_fifo_tx_s1_chipselect,                                 //                                                           .chipselect
		output wire [1:0]  write_en_tx_s1_address,                                           //                                             write_en_tx_s1.address
		output wire        write_en_tx_s1_write,                                             //                                                           .write
		input  wire [31:0] write_en_tx_s1_readdata,                                          //                                                           .readdata
		output wire [31:0] write_en_tx_s1_writedata,                                         //                                                           .writedata
		output wire        write_en_tx_s1_chipselect                                         //                                                           .chipselect
	);
 
	wire   [31:0] led_pio_test_s1_agent_m0_readdata;                           // led_pio_test_s1_translator:uav_readdata -> led_pio_test_s1_agent:m0_readdata
	wire          led_pio_test_s1_agent_m0_waitrequest;                        // led_pio_test_s1_translator:uav_waitrequest -> led_pio_test_s1_agent:m0_waitrequest
	wire          led_pio_test_s1_agent_m0_debugaccess;                        // led_pio_test_s1_agent:m0_debugaccess -> led_pio_test_s1_translator:uav_debugaccess
	wire   [29:0] led_pio_test_s1_agent_m0_address;                            // led_pio_test_s1_agent:m0_address -> led_pio_test_s1_translator:uav_address
	wire    [3:0] led_pio_test_s1_agent_m0_byteenable;                         // led_pio_test_s1_agent:m0_byteenable -> led_pio_test_s1_translator:uav_byteenable
	wire          led_pio_test_s1_agent_m0_read;                               // led_pio_test_s1_agent:m0_read -> led_pio_test_s1_translator:uav_read
	wire          led_pio_test_s1_agent_m0_readdatavalid;                      // led_pio_test_s1_translator:uav_readdatavalid -> led_pio_test_s1_agent:m0_readdatavalid
	wire          led_pio_test_s1_agent_m0_lock;                               // led_pio_test_s1_agent:m0_lock -> led_pio_test_s1_translator:uav_lock
	wire   [31:0] led_pio_test_s1_agent_m0_writedata;                          // led_pio_test_s1_agent:m0_writedata -> led_pio_test_s1_translator:uav_writedata
	wire          led_pio_test_s1_agent_m0_write;                              // led_pio_test_s1_agent:m0_write -> led_pio_test_s1_translator:uav_write
	wire    [2:0] led_pio_test_s1_agent_m0_burstcount;                         // led_pio_test_s1_agent:m0_burstcount -> led_pio_test_s1_translator:uav_burstcount
	wire          led_pio_test_s1_agent_rf_source_valid;                       // led_pio_test_s1_agent:rf_source_valid -> led_pio_test_s1_agent_rsp_fifo:in_valid
	wire  [129:0] led_pio_test_s1_agent_rf_source_data;                        // led_pio_test_s1_agent:rf_source_data -> led_pio_test_s1_agent_rsp_fifo:in_data
	wire          led_pio_test_s1_agent_rf_source_ready;                       // led_pio_test_s1_agent_rsp_fifo:in_ready -> led_pio_test_s1_agent:rf_source_ready
	wire          led_pio_test_s1_agent_rf_source_startofpacket;               // led_pio_test_s1_agent:rf_source_startofpacket -> led_pio_test_s1_agent_rsp_fifo:in_startofpacket
	wire          led_pio_test_s1_agent_rf_source_endofpacket;                 // led_pio_test_s1_agent:rf_source_endofpacket -> led_pio_test_s1_agent_rsp_fifo:in_endofpacket
	wire          led_pio_test_s1_agent_rsp_fifo_out_valid;                    // led_pio_test_s1_agent_rsp_fifo:out_valid -> led_pio_test_s1_agent:rf_sink_valid
	wire  [129:0] led_pio_test_s1_agent_rsp_fifo_out_data;                     // led_pio_test_s1_agent_rsp_fifo:out_data -> led_pio_test_s1_agent:rf_sink_data
	wire          led_pio_test_s1_agent_rsp_fifo_out_ready;                    // led_pio_test_s1_agent:rf_sink_ready -> led_pio_test_s1_agent_rsp_fifo:out_ready
	wire          led_pio_test_s1_agent_rsp_fifo_out_startofpacket;            // led_pio_test_s1_agent_rsp_fifo:out_startofpacket -> led_pio_test_s1_agent:rf_sink_startofpacket
	wire          led_pio_test_s1_agent_rsp_fifo_out_endofpacket;              // led_pio_test_s1_agent_rsp_fifo:out_endofpacket -> led_pio_test_s1_agent:rf_sink_endofpacket
	wire          led_pio_test_s1_agent_rdata_fifo_src_valid;                  // led_pio_test_s1_agent:rdata_fifo_src_valid -> led_pio_test_s1_agent_rdata_fifo:in_valid
	wire   [33:0] led_pio_test_s1_agent_rdata_fifo_src_data;                   // led_pio_test_s1_agent:rdata_fifo_src_data -> led_pio_test_s1_agent_rdata_fifo:in_data
	wire          led_pio_test_s1_agent_rdata_fifo_src_ready;                  // led_pio_test_s1_agent_rdata_fifo:in_ready -> led_pio_test_s1_agent:rdata_fifo_src_ready
	wire   [31:0] timecode_rx_s1_agent_m0_readdata;                            // timecode_rx_s1_translator:uav_readdata -> timecode_rx_s1_agent:m0_readdata
	wire          timecode_rx_s1_agent_m0_waitrequest;                         // timecode_rx_s1_translator:uav_waitrequest -> timecode_rx_s1_agent:m0_waitrequest
	wire          timecode_rx_s1_agent_m0_debugaccess;                         // timecode_rx_s1_agent:m0_debugaccess -> timecode_rx_s1_translator:uav_debugaccess
	wire   [29:0] timecode_rx_s1_agent_m0_address;                             // timecode_rx_s1_agent:m0_address -> timecode_rx_s1_translator:uav_address
	wire    [3:0] timecode_rx_s1_agent_m0_byteenable;                          // timecode_rx_s1_agent:m0_byteenable -> timecode_rx_s1_translator:uav_byteenable
	wire          timecode_rx_s1_agent_m0_read;                                // timecode_rx_s1_agent:m0_read -> timecode_rx_s1_translator:uav_read
	wire          timecode_rx_s1_agent_m0_readdatavalid;                       // timecode_rx_s1_translator:uav_readdatavalid -> timecode_rx_s1_agent:m0_readdatavalid
	wire          timecode_rx_s1_agent_m0_lock;                                // timecode_rx_s1_agent:m0_lock -> timecode_rx_s1_translator:uav_lock
	wire   [31:0] timecode_rx_s1_agent_m0_writedata;                           // timecode_rx_s1_agent:m0_writedata -> timecode_rx_s1_translator:uav_writedata
	wire          timecode_rx_s1_agent_m0_write;                               // timecode_rx_s1_agent:m0_write -> timecode_rx_s1_translator:uav_write
	wire    [2:0] timecode_rx_s1_agent_m0_burstcount;                          // timecode_rx_s1_agent:m0_burstcount -> timecode_rx_s1_translator:uav_burstcount
	wire          timecode_rx_s1_agent_rf_source_valid;                        // timecode_rx_s1_agent:rf_source_valid -> timecode_rx_s1_agent_rsp_fifo:in_valid
	wire  [129:0] timecode_rx_s1_agent_rf_source_data;                         // timecode_rx_s1_agent:rf_source_data -> timecode_rx_s1_agent_rsp_fifo:in_data
	wire          timecode_rx_s1_agent_rf_source_ready;                        // timecode_rx_s1_agent_rsp_fifo:in_ready -> timecode_rx_s1_agent:rf_source_ready
	wire          timecode_rx_s1_agent_rf_source_startofpacket;                // timecode_rx_s1_agent:rf_source_startofpacket -> timecode_rx_s1_agent_rsp_fifo:in_startofpacket
	wire          timecode_rx_s1_agent_rf_source_endofpacket;                  // timecode_rx_s1_agent:rf_source_endofpacket -> timecode_rx_s1_agent_rsp_fifo:in_endofpacket
	wire          timecode_rx_s1_agent_rsp_fifo_out_valid;                     // timecode_rx_s1_agent_rsp_fifo:out_valid -> timecode_rx_s1_agent:rf_sink_valid
	wire  [129:0] timecode_rx_s1_agent_rsp_fifo_out_data;                      // timecode_rx_s1_agent_rsp_fifo:out_data -> timecode_rx_s1_agent:rf_sink_data
	wire          timecode_rx_s1_agent_rsp_fifo_out_ready;                     // timecode_rx_s1_agent:rf_sink_ready -> timecode_rx_s1_agent_rsp_fifo:out_ready
	wire          timecode_rx_s1_agent_rsp_fifo_out_startofpacket;             // timecode_rx_s1_agent_rsp_fifo:out_startofpacket -> timecode_rx_s1_agent:rf_sink_startofpacket
	wire          timecode_rx_s1_agent_rsp_fifo_out_endofpacket;               // timecode_rx_s1_agent_rsp_fifo:out_endofpacket -> timecode_rx_s1_agent:rf_sink_endofpacket
	wire          timecode_rx_s1_agent_rdata_fifo_src_valid;                   // timecode_rx_s1_agent:rdata_fifo_src_valid -> timecode_rx_s1_agent_rdata_fifo:in_valid
	wire   [33:0] timecode_rx_s1_agent_rdata_fifo_src_data;                    // timecode_rx_s1_agent:rdata_fifo_src_data -> timecode_rx_s1_agent_rdata_fifo:in_data
	wire          timecode_rx_s1_agent_rdata_fifo_src_ready;                   // timecode_rx_s1_agent_rdata_fifo:in_ready -> timecode_rx_s1_agent:rdata_fifo_src_ready
	wire   [31:0] timecode_ready_rx_s1_agent_m0_readdata;                      // timecode_ready_rx_s1_translator:uav_readdata -> timecode_ready_rx_s1_agent:m0_readdata
	wire          timecode_ready_rx_s1_agent_m0_waitrequest;                   // timecode_ready_rx_s1_translator:uav_waitrequest -> timecode_ready_rx_s1_agent:m0_waitrequest
	wire          timecode_ready_rx_s1_agent_m0_debugaccess;                   // timecode_ready_rx_s1_agent:m0_debugaccess -> timecode_ready_rx_s1_translator:uav_debugaccess
	wire   [29:0] timecode_ready_rx_s1_agent_m0_address;                       // timecode_ready_rx_s1_agent:m0_address -> timecode_ready_rx_s1_translator:uav_address
	wire    [3:0] timecode_ready_rx_s1_agent_m0_byteenable;                    // timecode_ready_rx_s1_agent:m0_byteenable -> timecode_ready_rx_s1_translator:uav_byteenable
	wire          timecode_ready_rx_s1_agent_m0_read;                          // timecode_ready_rx_s1_agent:m0_read -> timecode_ready_rx_s1_translator:uav_read
	wire          timecode_ready_rx_s1_agent_m0_readdatavalid;                 // timecode_ready_rx_s1_translator:uav_readdatavalid -> timecode_ready_rx_s1_agent:m0_readdatavalid
	wire          timecode_ready_rx_s1_agent_m0_lock;                          // timecode_ready_rx_s1_agent:m0_lock -> timecode_ready_rx_s1_translator:uav_lock
	wire   [31:0] timecode_ready_rx_s1_agent_m0_writedata;                     // timecode_ready_rx_s1_agent:m0_writedata -> timecode_ready_rx_s1_translator:uav_writedata
	wire          timecode_ready_rx_s1_agent_m0_write;                         // timecode_ready_rx_s1_agent:m0_write -> timecode_ready_rx_s1_translator:uav_write
	wire    [2:0] timecode_ready_rx_s1_agent_m0_burstcount;                    // timecode_ready_rx_s1_agent:m0_burstcount -> timecode_ready_rx_s1_translator:uav_burstcount
	wire          timecode_ready_rx_s1_agent_rf_source_valid;                  // timecode_ready_rx_s1_agent:rf_source_valid -> timecode_ready_rx_s1_agent_rsp_fifo:in_valid
	wire  [129:0] timecode_ready_rx_s1_agent_rf_source_data;                   // timecode_ready_rx_s1_agent:rf_source_data -> timecode_ready_rx_s1_agent_rsp_fifo:in_data
	wire          timecode_ready_rx_s1_agent_rf_source_ready;                  // timecode_ready_rx_s1_agent_rsp_fifo:in_ready -> timecode_ready_rx_s1_agent:rf_source_ready
	wire          timecode_ready_rx_s1_agent_rf_source_startofpacket;          // timecode_ready_rx_s1_agent:rf_source_startofpacket -> timecode_ready_rx_s1_agent_rsp_fifo:in_startofpacket
	wire          timecode_ready_rx_s1_agent_rf_source_endofpacket;            // timecode_ready_rx_s1_agent:rf_source_endofpacket -> timecode_ready_rx_s1_agent_rsp_fifo:in_endofpacket
	wire          timecode_ready_rx_s1_agent_rsp_fifo_out_valid;               // timecode_ready_rx_s1_agent_rsp_fifo:out_valid -> timecode_ready_rx_s1_agent:rf_sink_valid
	wire  [129:0] timecode_ready_rx_s1_agent_rsp_fifo_out_data;                // timecode_ready_rx_s1_agent_rsp_fifo:out_data -> timecode_ready_rx_s1_agent:rf_sink_data
	wire          timecode_ready_rx_s1_agent_rsp_fifo_out_ready;               // timecode_ready_rx_s1_agent:rf_sink_ready -> timecode_ready_rx_s1_agent_rsp_fifo:out_ready
	wire          timecode_ready_rx_s1_agent_rsp_fifo_out_startofpacket;       // timecode_ready_rx_s1_agent_rsp_fifo:out_startofpacket -> timecode_ready_rx_s1_agent:rf_sink_startofpacket
	wire          timecode_ready_rx_s1_agent_rsp_fifo_out_endofpacket;         // timecode_ready_rx_s1_agent_rsp_fifo:out_endofpacket -> timecode_ready_rx_s1_agent:rf_sink_endofpacket
	wire          timecode_ready_rx_s1_agent_rdata_fifo_src_valid;             // timecode_ready_rx_s1_agent:rdata_fifo_src_valid -> timecode_ready_rx_s1_agent_rdata_fifo:in_valid
	wire   [33:0] timecode_ready_rx_s1_agent_rdata_fifo_src_data;              // timecode_ready_rx_s1_agent:rdata_fifo_src_data -> timecode_ready_rx_s1_agent_rdata_fifo:in_data
	wire          timecode_ready_rx_s1_agent_rdata_fifo_src_ready;             // timecode_ready_rx_s1_agent_rdata_fifo:in_ready -> timecode_ready_rx_s1_agent:rdata_fifo_src_ready
	wire   [31:0] data_flag_rx_s1_agent_m0_readdata;                           // data_flag_rx_s1_translator:uav_readdata -> data_flag_rx_s1_agent:m0_readdata
	wire          data_flag_rx_s1_agent_m0_waitrequest;                        // data_flag_rx_s1_translator:uav_waitrequest -> data_flag_rx_s1_agent:m0_waitrequest
	wire          data_flag_rx_s1_agent_m0_debugaccess;                        // data_flag_rx_s1_agent:m0_debugaccess -> data_flag_rx_s1_translator:uav_debugaccess
	wire   [29:0] data_flag_rx_s1_agent_m0_address;                            // data_flag_rx_s1_agent:m0_address -> data_flag_rx_s1_translator:uav_address
	wire    [3:0] data_flag_rx_s1_agent_m0_byteenable;                         // data_flag_rx_s1_agent:m0_byteenable -> data_flag_rx_s1_translator:uav_byteenable
	wire          data_flag_rx_s1_agent_m0_read;                               // data_flag_rx_s1_agent:m0_read -> data_flag_rx_s1_translator:uav_read
	wire          data_flag_rx_s1_agent_m0_readdatavalid;                      // data_flag_rx_s1_translator:uav_readdatavalid -> data_flag_rx_s1_agent:m0_readdatavalid
	wire          data_flag_rx_s1_agent_m0_lock;                               // data_flag_rx_s1_agent:m0_lock -> data_flag_rx_s1_translator:uav_lock
	wire   [31:0] data_flag_rx_s1_agent_m0_writedata;                          // data_flag_rx_s1_agent:m0_writedata -> data_flag_rx_s1_translator:uav_writedata
	wire          data_flag_rx_s1_agent_m0_write;                              // data_flag_rx_s1_agent:m0_write -> data_flag_rx_s1_translator:uav_write
	wire    [2:0] data_flag_rx_s1_agent_m0_burstcount;                         // data_flag_rx_s1_agent:m0_burstcount -> data_flag_rx_s1_translator:uav_burstcount
	wire          data_flag_rx_s1_agent_rf_source_valid;                       // data_flag_rx_s1_agent:rf_source_valid -> data_flag_rx_s1_agent_rsp_fifo:in_valid
	wire  [129:0] data_flag_rx_s1_agent_rf_source_data;                        // data_flag_rx_s1_agent:rf_source_data -> data_flag_rx_s1_agent_rsp_fifo:in_data
	wire          data_flag_rx_s1_agent_rf_source_ready;                       // data_flag_rx_s1_agent_rsp_fifo:in_ready -> data_flag_rx_s1_agent:rf_source_ready
	wire          data_flag_rx_s1_agent_rf_source_startofpacket;               // data_flag_rx_s1_agent:rf_source_startofpacket -> data_flag_rx_s1_agent_rsp_fifo:in_startofpacket
	wire          data_flag_rx_s1_agent_rf_source_endofpacket;                 // data_flag_rx_s1_agent:rf_source_endofpacket -> data_flag_rx_s1_agent_rsp_fifo:in_endofpacket
	wire          data_flag_rx_s1_agent_rsp_fifo_out_valid;                    // data_flag_rx_s1_agent_rsp_fifo:out_valid -> data_flag_rx_s1_agent:rf_sink_valid
	wire  [129:0] data_flag_rx_s1_agent_rsp_fifo_out_data;                     // data_flag_rx_s1_agent_rsp_fifo:out_data -> data_flag_rx_s1_agent:rf_sink_data
	wire          data_flag_rx_s1_agent_rsp_fifo_out_ready;                    // data_flag_rx_s1_agent:rf_sink_ready -> data_flag_rx_s1_agent_rsp_fifo:out_ready
	wire          data_flag_rx_s1_agent_rsp_fifo_out_startofpacket;            // data_flag_rx_s1_agent_rsp_fifo:out_startofpacket -> data_flag_rx_s1_agent:rf_sink_startofpacket
	wire          data_flag_rx_s1_agent_rsp_fifo_out_endofpacket;              // data_flag_rx_s1_agent_rsp_fifo:out_endofpacket -> data_flag_rx_s1_agent:rf_sink_endofpacket
	wire          data_flag_rx_s1_agent_rdata_fifo_src_valid;                  // data_flag_rx_s1_agent:rdata_fifo_src_valid -> data_flag_rx_s1_agent_rdata_fifo:in_valid
	wire   [33:0] data_flag_rx_s1_agent_rdata_fifo_src_data;                   // data_flag_rx_s1_agent:rdata_fifo_src_data -> data_flag_rx_s1_agent_rdata_fifo:in_data
	wire          data_flag_rx_s1_agent_rdata_fifo_src_ready;                  // data_flag_rx_s1_agent_rdata_fifo:in_ready -> data_flag_rx_s1_agent:rdata_fifo_src_ready
	wire   [31:0] data_read_en_rx_s1_agent_m0_readdata;                        // data_read_en_rx_s1_translator:uav_readdata -> data_read_en_rx_s1_agent:m0_readdata
	wire          data_read_en_rx_s1_agent_m0_waitrequest;                     // data_read_en_rx_s1_translator:uav_waitrequest -> data_read_en_rx_s1_agent:m0_waitrequest
	wire          data_read_en_rx_s1_agent_m0_debugaccess;                     // data_read_en_rx_s1_agent:m0_debugaccess -> data_read_en_rx_s1_translator:uav_debugaccess
	wire   [29:0] data_read_en_rx_s1_agent_m0_address;                         // data_read_en_rx_s1_agent:m0_address -> data_read_en_rx_s1_translator:uav_address
	wire    [3:0] data_read_en_rx_s1_agent_m0_byteenable;                      // data_read_en_rx_s1_agent:m0_byteenable -> data_read_en_rx_s1_translator:uav_byteenable
	wire          data_read_en_rx_s1_agent_m0_read;                            // data_read_en_rx_s1_agent:m0_read -> data_read_en_rx_s1_translator:uav_read
	wire          data_read_en_rx_s1_agent_m0_readdatavalid;                   // data_read_en_rx_s1_translator:uav_readdatavalid -> data_read_en_rx_s1_agent:m0_readdatavalid
	wire          data_read_en_rx_s1_agent_m0_lock;                            // data_read_en_rx_s1_agent:m0_lock -> data_read_en_rx_s1_translator:uav_lock
	wire   [31:0] data_read_en_rx_s1_agent_m0_writedata;                       // data_read_en_rx_s1_agent:m0_writedata -> data_read_en_rx_s1_translator:uav_writedata
	wire          data_read_en_rx_s1_agent_m0_write;                           // data_read_en_rx_s1_agent:m0_write -> data_read_en_rx_s1_translator:uav_write
	wire    [2:0] data_read_en_rx_s1_agent_m0_burstcount;                      // data_read_en_rx_s1_agent:m0_burstcount -> data_read_en_rx_s1_translator:uav_burstcount
	wire          data_read_en_rx_s1_agent_rf_source_valid;                    // data_read_en_rx_s1_agent:rf_source_valid -> data_read_en_rx_s1_agent_rsp_fifo:in_valid
	wire  [129:0] data_read_en_rx_s1_agent_rf_source_data;                     // data_read_en_rx_s1_agent:rf_source_data -> data_read_en_rx_s1_agent_rsp_fifo:in_data
	wire          data_read_en_rx_s1_agent_rf_source_ready;                    // data_read_en_rx_s1_agent_rsp_fifo:in_ready -> data_read_en_rx_s1_agent:rf_source_ready
	wire          data_read_en_rx_s1_agent_rf_source_startofpacket;            // data_read_en_rx_s1_agent:rf_source_startofpacket -> data_read_en_rx_s1_agent_rsp_fifo:in_startofpacket
	wire          data_read_en_rx_s1_agent_rf_source_endofpacket;              // data_read_en_rx_s1_agent:rf_source_endofpacket -> data_read_en_rx_s1_agent_rsp_fifo:in_endofpacket
	wire          data_read_en_rx_s1_agent_rsp_fifo_out_valid;                 // data_read_en_rx_s1_agent_rsp_fifo:out_valid -> data_read_en_rx_s1_agent:rf_sink_valid
	wire  [129:0] data_read_en_rx_s1_agent_rsp_fifo_out_data;                  // data_read_en_rx_s1_agent_rsp_fifo:out_data -> data_read_en_rx_s1_agent:rf_sink_data
	wire          data_read_en_rx_s1_agent_rsp_fifo_out_ready;                 // data_read_en_rx_s1_agent:rf_sink_ready -> data_read_en_rx_s1_agent_rsp_fifo:out_ready
	wire          data_read_en_rx_s1_agent_rsp_fifo_out_startofpacket;         // data_read_en_rx_s1_agent_rsp_fifo:out_startofpacket -> data_read_en_rx_s1_agent:rf_sink_startofpacket
	wire          data_read_en_rx_s1_agent_rsp_fifo_out_endofpacket;           // data_read_en_rx_s1_agent_rsp_fifo:out_endofpacket -> data_read_en_rx_s1_agent:rf_sink_endofpacket
	wire          data_read_en_rx_s1_agent_rdata_fifo_src_valid;               // data_read_en_rx_s1_agent:rdata_fifo_src_valid -> data_read_en_rx_s1_agent_rdata_fifo:in_valid
	wire   [33:0] data_read_en_rx_s1_agent_rdata_fifo_src_data;                // data_read_en_rx_s1_agent:rdata_fifo_src_data -> data_read_en_rx_s1_agent_rdata_fifo:in_data
	wire          data_read_en_rx_s1_agent_rdata_fifo_src_ready;               // data_read_en_rx_s1_agent_rdata_fifo:in_ready -> data_read_en_rx_s1_agent:rdata_fifo_src_ready
	wire   [31:0] fifo_full_rx_status_s1_agent_m0_readdata;                    // fifo_full_rx_status_s1_translator:uav_readdata -> fifo_full_rx_status_s1_agent:m0_readdata
	wire          fifo_full_rx_status_s1_agent_m0_waitrequest;                 // fifo_full_rx_status_s1_translator:uav_waitrequest -> fifo_full_rx_status_s1_agent:m0_waitrequest
	wire          fifo_full_rx_status_s1_agent_m0_debugaccess;                 // fifo_full_rx_status_s1_agent:m0_debugaccess -> fifo_full_rx_status_s1_translator:uav_debugaccess
	wire   [29:0] fifo_full_rx_status_s1_agent_m0_address;                     // fifo_full_rx_status_s1_agent:m0_address -> fifo_full_rx_status_s1_translator:uav_address
	wire    [3:0] fifo_full_rx_status_s1_agent_m0_byteenable;                  // fifo_full_rx_status_s1_agent:m0_byteenable -> fifo_full_rx_status_s1_translator:uav_byteenable
	wire          fifo_full_rx_status_s1_agent_m0_read;                        // fifo_full_rx_status_s1_agent:m0_read -> fifo_full_rx_status_s1_translator:uav_read
	wire          fifo_full_rx_status_s1_agent_m0_readdatavalid;               // fifo_full_rx_status_s1_translator:uav_readdatavalid -> fifo_full_rx_status_s1_agent:m0_readdatavalid
	wire          fifo_full_rx_status_s1_agent_m0_lock;                        // fifo_full_rx_status_s1_agent:m0_lock -> fifo_full_rx_status_s1_translator:uav_lock
	wire   [31:0] fifo_full_rx_status_s1_agent_m0_writedata;                   // fifo_full_rx_status_s1_agent:m0_writedata -> fifo_full_rx_status_s1_translator:uav_writedata
	wire          fifo_full_rx_status_s1_agent_m0_write;                       // fifo_full_rx_status_s1_agent:m0_write -> fifo_full_rx_status_s1_translator:uav_write
	wire    [2:0] fifo_full_rx_status_s1_agent_m0_burstcount;                  // fifo_full_rx_status_s1_agent:m0_burstcount -> fifo_full_rx_status_s1_translator:uav_burstcount
	wire          fifo_full_rx_status_s1_agent_rf_source_valid;                // fifo_full_rx_status_s1_agent:rf_source_valid -> fifo_full_rx_status_s1_agent_rsp_fifo:in_valid
	wire  [129:0] fifo_full_rx_status_s1_agent_rf_source_data;                 // fifo_full_rx_status_s1_agent:rf_source_data -> fifo_full_rx_status_s1_agent_rsp_fifo:in_data
	wire          fifo_full_rx_status_s1_agent_rf_source_ready;                // fifo_full_rx_status_s1_agent_rsp_fifo:in_ready -> fifo_full_rx_status_s1_agent:rf_source_ready
	wire          fifo_full_rx_status_s1_agent_rf_source_startofpacket;        // fifo_full_rx_status_s1_agent:rf_source_startofpacket -> fifo_full_rx_status_s1_agent_rsp_fifo:in_startofpacket
	wire          fifo_full_rx_status_s1_agent_rf_source_endofpacket;          // fifo_full_rx_status_s1_agent:rf_source_endofpacket -> fifo_full_rx_status_s1_agent_rsp_fifo:in_endofpacket
	wire          fifo_full_rx_status_s1_agent_rsp_fifo_out_valid;             // fifo_full_rx_status_s1_agent_rsp_fifo:out_valid -> fifo_full_rx_status_s1_agent:rf_sink_valid
	wire  [129:0] fifo_full_rx_status_s1_agent_rsp_fifo_out_data;              // fifo_full_rx_status_s1_agent_rsp_fifo:out_data -> fifo_full_rx_status_s1_agent:rf_sink_data
	wire          fifo_full_rx_status_s1_agent_rsp_fifo_out_ready;             // fifo_full_rx_status_s1_agent:rf_sink_ready -> fifo_full_rx_status_s1_agent_rsp_fifo:out_ready
	wire          fifo_full_rx_status_s1_agent_rsp_fifo_out_startofpacket;     // fifo_full_rx_status_s1_agent_rsp_fifo:out_startofpacket -> fifo_full_rx_status_s1_agent:rf_sink_startofpacket
	wire          fifo_full_rx_status_s1_agent_rsp_fifo_out_endofpacket;       // fifo_full_rx_status_s1_agent_rsp_fifo:out_endofpacket -> fifo_full_rx_status_s1_agent:rf_sink_endofpacket
	wire          fifo_full_rx_status_s1_agent_rdata_fifo_src_valid;           // fifo_full_rx_status_s1_agent:rdata_fifo_src_valid -> fifo_full_rx_status_s1_agent_rdata_fifo:in_valid
	wire   [33:0] fifo_full_rx_status_s1_agent_rdata_fifo_src_data;            // fifo_full_rx_status_s1_agent:rdata_fifo_src_data -> fifo_full_rx_status_s1_agent_rdata_fifo:in_data
	wire          fifo_full_rx_status_s1_agent_rdata_fifo_src_ready;           // fifo_full_rx_status_s1_agent_rdata_fifo:in_ready -> fifo_full_rx_status_s1_agent:rdata_fifo_src_ready
	wire   [31:0] fifo_empty_rx_status_s1_agent_m0_readdata;                   // fifo_empty_rx_status_s1_translator:uav_readdata -> fifo_empty_rx_status_s1_agent:m0_readdata
	wire          fifo_empty_rx_status_s1_agent_m0_waitrequest;                // fifo_empty_rx_status_s1_translator:uav_waitrequest -> fifo_empty_rx_status_s1_agent:m0_waitrequest
	wire          fifo_empty_rx_status_s1_agent_m0_debugaccess;                // fifo_empty_rx_status_s1_agent:m0_debugaccess -> fifo_empty_rx_status_s1_translator:uav_debugaccess
	wire   [29:0] fifo_empty_rx_status_s1_agent_m0_address;                    // fifo_empty_rx_status_s1_agent:m0_address -> fifo_empty_rx_status_s1_translator:uav_address
	wire    [3:0] fifo_empty_rx_status_s1_agent_m0_byteenable;                 // fifo_empty_rx_status_s1_agent:m0_byteenable -> fifo_empty_rx_status_s1_translator:uav_byteenable
	wire          fifo_empty_rx_status_s1_agent_m0_read;                       // fifo_empty_rx_status_s1_agent:m0_read -> fifo_empty_rx_status_s1_translator:uav_read
	wire          fifo_empty_rx_status_s1_agent_m0_readdatavalid;              // fifo_empty_rx_status_s1_translator:uav_readdatavalid -> fifo_empty_rx_status_s1_agent:m0_readdatavalid
	wire          fifo_empty_rx_status_s1_agent_m0_lock;                       // fifo_empty_rx_status_s1_agent:m0_lock -> fifo_empty_rx_status_s1_translator:uav_lock
	wire   [31:0] fifo_empty_rx_status_s1_agent_m0_writedata;                  // fifo_empty_rx_status_s1_agent:m0_writedata -> fifo_empty_rx_status_s1_translator:uav_writedata
	wire          fifo_empty_rx_status_s1_agent_m0_write;                      // fifo_empty_rx_status_s1_agent:m0_write -> fifo_empty_rx_status_s1_translator:uav_write
	wire    [2:0] fifo_empty_rx_status_s1_agent_m0_burstcount;                 // fifo_empty_rx_status_s1_agent:m0_burstcount -> fifo_empty_rx_status_s1_translator:uav_burstcount
	wire          fifo_empty_rx_status_s1_agent_rf_source_valid;               // fifo_empty_rx_status_s1_agent:rf_source_valid -> fifo_empty_rx_status_s1_agent_rsp_fifo:in_valid
	wire  [129:0] fifo_empty_rx_status_s1_agent_rf_source_data;                // fifo_empty_rx_status_s1_agent:rf_source_data -> fifo_empty_rx_status_s1_agent_rsp_fifo:in_data
	wire          fifo_empty_rx_status_s1_agent_rf_source_ready;               // fifo_empty_rx_status_s1_agent_rsp_fifo:in_ready -> fifo_empty_rx_status_s1_agent:rf_source_ready
	wire          fifo_empty_rx_status_s1_agent_rf_source_startofpacket;       // fifo_empty_rx_status_s1_agent:rf_source_startofpacket -> fifo_empty_rx_status_s1_agent_rsp_fifo:in_startofpacket
	wire          fifo_empty_rx_status_s1_agent_rf_source_endofpacket;         // fifo_empty_rx_status_s1_agent:rf_source_endofpacket -> fifo_empty_rx_status_s1_agent_rsp_fifo:in_endofpacket
	wire          fifo_empty_rx_status_s1_agent_rsp_fifo_out_valid;            // fifo_empty_rx_status_s1_agent_rsp_fifo:out_valid -> fifo_empty_rx_status_s1_agent:rf_sink_valid
	wire  [129:0] fifo_empty_rx_status_s1_agent_rsp_fifo_out_data;             // fifo_empty_rx_status_s1_agent_rsp_fifo:out_data -> fifo_empty_rx_status_s1_agent:rf_sink_data
	wire          fifo_empty_rx_status_s1_agent_rsp_fifo_out_ready;            // fifo_empty_rx_status_s1_agent:rf_sink_ready -> fifo_empty_rx_status_s1_agent_rsp_fifo:out_ready
	wire          fifo_empty_rx_status_s1_agent_rsp_fifo_out_startofpacket;    // fifo_empty_rx_status_s1_agent_rsp_fifo:out_startofpacket -> fifo_empty_rx_status_s1_agent:rf_sink_startofpacket
	wire          fifo_empty_rx_status_s1_agent_rsp_fifo_out_endofpacket;      // fifo_empty_rx_status_s1_agent_rsp_fifo:out_endofpacket -> fifo_empty_rx_status_s1_agent:rf_sink_endofpacket
	wire          fifo_empty_rx_status_s1_agent_rdata_fifo_src_valid;          // fifo_empty_rx_status_s1_agent:rdata_fifo_src_valid -> fifo_empty_rx_status_s1_agent_rdata_fifo:in_valid
	wire   [33:0] fifo_empty_rx_status_s1_agent_rdata_fifo_src_data;           // fifo_empty_rx_status_s1_agent:rdata_fifo_src_data -> fifo_empty_rx_status_s1_agent_rdata_fifo:in_data
	wire          fifo_empty_rx_status_s1_agent_rdata_fifo_src_ready;          // fifo_empty_rx_status_s1_agent_rdata_fifo:in_ready -> fifo_empty_rx_status_s1_agent:rdata_fifo_src_ready
	wire   [31:0] link_start_s1_agent_m0_readdata;                             // link_start_s1_translator:uav_readdata -> link_start_s1_agent:m0_readdata
	wire          link_start_s1_agent_m0_waitrequest;                          // link_start_s1_translator:uav_waitrequest -> link_start_s1_agent:m0_waitrequest
	wire          link_start_s1_agent_m0_debugaccess;                          // link_start_s1_agent:m0_debugaccess -> link_start_s1_translator:uav_debugaccess
	wire   [29:0] link_start_s1_agent_m0_address;                              // link_start_s1_agent:m0_address -> link_start_s1_translator:uav_address
	wire    [3:0] link_start_s1_agent_m0_byteenable;                           // link_start_s1_agent:m0_byteenable -> link_start_s1_translator:uav_byteenable
	wire          link_start_s1_agent_m0_read;                                 // link_start_s1_agent:m0_read -> link_start_s1_translator:uav_read
	wire          link_start_s1_agent_m0_readdatavalid;                        // link_start_s1_translator:uav_readdatavalid -> link_start_s1_agent:m0_readdatavalid
	wire          link_start_s1_agent_m0_lock;                                 // link_start_s1_agent:m0_lock -> link_start_s1_translator:uav_lock
	wire   [31:0] link_start_s1_agent_m0_writedata;                            // link_start_s1_agent:m0_writedata -> link_start_s1_translator:uav_writedata
	wire          link_start_s1_agent_m0_write;                                // link_start_s1_agent:m0_write -> link_start_s1_translator:uav_write
	wire    [2:0] link_start_s1_agent_m0_burstcount;                           // link_start_s1_agent:m0_burstcount -> link_start_s1_translator:uav_burstcount
	wire          link_start_s1_agent_rf_source_valid;                         // link_start_s1_agent:rf_source_valid -> link_start_s1_agent_rsp_fifo:in_valid
	wire  [129:0] link_start_s1_agent_rf_source_data;                          // link_start_s1_agent:rf_source_data -> link_start_s1_agent_rsp_fifo:in_data
	wire          link_start_s1_agent_rf_source_ready;                         // link_start_s1_agent_rsp_fifo:in_ready -> link_start_s1_agent:rf_source_ready
	wire          link_start_s1_agent_rf_source_startofpacket;                 // link_start_s1_agent:rf_source_startofpacket -> link_start_s1_agent_rsp_fifo:in_startofpacket
	wire          link_start_s1_agent_rf_source_endofpacket;                   // link_start_s1_agent:rf_source_endofpacket -> link_start_s1_agent_rsp_fifo:in_endofpacket
	wire          link_start_s1_agent_rsp_fifo_out_valid;                      // link_start_s1_agent_rsp_fifo:out_valid -> link_start_s1_agent:rf_sink_valid
	wire  [129:0] link_start_s1_agent_rsp_fifo_out_data;                       // link_start_s1_agent_rsp_fifo:out_data -> link_start_s1_agent:rf_sink_data
	wire          link_start_s1_agent_rsp_fifo_out_ready;                      // link_start_s1_agent:rf_sink_ready -> link_start_s1_agent_rsp_fifo:out_ready
	wire          link_start_s1_agent_rsp_fifo_out_startofpacket;              // link_start_s1_agent_rsp_fifo:out_startofpacket -> link_start_s1_agent:rf_sink_startofpacket
	wire          link_start_s1_agent_rsp_fifo_out_endofpacket;                // link_start_s1_agent_rsp_fifo:out_endofpacket -> link_start_s1_agent:rf_sink_endofpacket
	wire          link_start_s1_agent_rdata_fifo_src_valid;                    // link_start_s1_agent:rdata_fifo_src_valid -> link_start_s1_agent_rdata_fifo:in_valid
	wire   [33:0] link_start_s1_agent_rdata_fifo_src_data;                     // link_start_s1_agent:rdata_fifo_src_data -> link_start_s1_agent_rdata_fifo:in_data
	wire          link_start_s1_agent_rdata_fifo_src_ready;                    // link_start_s1_agent_rdata_fifo:in_ready -> link_start_s1_agent:rdata_fifo_src_ready
	wire   [31:0] auto_start_s1_agent_m0_readdata;                             // auto_start_s1_translator:uav_readdata -> auto_start_s1_agent:m0_readdata
	wire          auto_start_s1_agent_m0_waitrequest;                          // auto_start_s1_translator:uav_waitrequest -> auto_start_s1_agent:m0_waitrequest
	wire          auto_start_s1_agent_m0_debugaccess;                          // auto_start_s1_agent:m0_debugaccess -> auto_start_s1_translator:uav_debugaccess
	wire   [29:0] auto_start_s1_agent_m0_address;                              // auto_start_s1_agent:m0_address -> auto_start_s1_translator:uav_address
	wire    [3:0] auto_start_s1_agent_m0_byteenable;                           // auto_start_s1_agent:m0_byteenable -> auto_start_s1_translator:uav_byteenable
	wire          auto_start_s1_agent_m0_read;                                 // auto_start_s1_agent:m0_read -> auto_start_s1_translator:uav_read
	wire          auto_start_s1_agent_m0_readdatavalid;                        // auto_start_s1_translator:uav_readdatavalid -> auto_start_s1_agent:m0_readdatavalid
	wire          auto_start_s1_agent_m0_lock;                                 // auto_start_s1_agent:m0_lock -> auto_start_s1_translator:uav_lock
	wire   [31:0] auto_start_s1_agent_m0_writedata;                            // auto_start_s1_agent:m0_writedata -> auto_start_s1_translator:uav_writedata
	wire          auto_start_s1_agent_m0_write;                                // auto_start_s1_agent:m0_write -> auto_start_s1_translator:uav_write
	wire    [2:0] auto_start_s1_agent_m0_burstcount;                           // auto_start_s1_agent:m0_burstcount -> auto_start_s1_translator:uav_burstcount
	wire          auto_start_s1_agent_rf_source_valid;                         // auto_start_s1_agent:rf_source_valid -> auto_start_s1_agent_rsp_fifo:in_valid
	wire  [129:0] auto_start_s1_agent_rf_source_data;                          // auto_start_s1_agent:rf_source_data -> auto_start_s1_agent_rsp_fifo:in_data
	wire          auto_start_s1_agent_rf_source_ready;                         // auto_start_s1_agent_rsp_fifo:in_ready -> auto_start_s1_agent:rf_source_ready
	wire          auto_start_s1_agent_rf_source_startofpacket;                 // auto_start_s1_agent:rf_source_startofpacket -> auto_start_s1_agent_rsp_fifo:in_startofpacket
	wire          auto_start_s1_agent_rf_source_endofpacket;                   // auto_start_s1_agent:rf_source_endofpacket -> auto_start_s1_agent_rsp_fifo:in_endofpacket
	wire          auto_start_s1_agent_rsp_fifo_out_valid;                      // auto_start_s1_agent_rsp_fifo:out_valid -> auto_start_s1_agent:rf_sink_valid
	wire  [129:0] auto_start_s1_agent_rsp_fifo_out_data;                       // auto_start_s1_agent_rsp_fifo:out_data -> auto_start_s1_agent:rf_sink_data
	wire          auto_start_s1_agent_rsp_fifo_out_ready;                      // auto_start_s1_agent:rf_sink_ready -> auto_start_s1_agent_rsp_fifo:out_ready
	wire          auto_start_s1_agent_rsp_fifo_out_startofpacket;              // auto_start_s1_agent_rsp_fifo:out_startofpacket -> auto_start_s1_agent:rf_sink_startofpacket
	wire          auto_start_s1_agent_rsp_fifo_out_endofpacket;                // auto_start_s1_agent_rsp_fifo:out_endofpacket -> auto_start_s1_agent:rf_sink_endofpacket
	wire          auto_start_s1_agent_rdata_fifo_src_valid;                    // auto_start_s1_agent:rdata_fifo_src_valid -> auto_start_s1_agent_rdata_fifo:in_valid
	wire   [33:0] auto_start_s1_agent_rdata_fifo_src_data;                     // auto_start_s1_agent:rdata_fifo_src_data -> auto_start_s1_agent_rdata_fifo:in_data
	wire          auto_start_s1_agent_rdata_fifo_src_ready;                    // auto_start_s1_agent_rdata_fifo:in_ready -> auto_start_s1_agent:rdata_fifo_src_ready
	wire   [31:0] link_disable_s1_agent_m0_readdata;                           // link_disable_s1_translator:uav_readdata -> link_disable_s1_agent:m0_readdata
	wire          link_disable_s1_agent_m0_waitrequest;                        // link_disable_s1_translator:uav_waitrequest -> link_disable_s1_agent:m0_waitrequest
	wire          link_disable_s1_agent_m0_debugaccess;                        // link_disable_s1_agent:m0_debugaccess -> link_disable_s1_translator:uav_debugaccess
	wire   [29:0] link_disable_s1_agent_m0_address;                            // link_disable_s1_agent:m0_address -> link_disable_s1_translator:uav_address
	wire    [3:0] link_disable_s1_agent_m0_byteenable;                         // link_disable_s1_agent:m0_byteenable -> link_disable_s1_translator:uav_byteenable
	wire          link_disable_s1_agent_m0_read;                               // link_disable_s1_agent:m0_read -> link_disable_s1_translator:uav_read
	wire          link_disable_s1_agent_m0_readdatavalid;                      // link_disable_s1_translator:uav_readdatavalid -> link_disable_s1_agent:m0_readdatavalid
	wire          link_disable_s1_agent_m0_lock;                               // link_disable_s1_agent:m0_lock -> link_disable_s1_translator:uav_lock
	wire   [31:0] link_disable_s1_agent_m0_writedata;                          // link_disable_s1_agent:m0_writedata -> link_disable_s1_translator:uav_writedata
	wire          link_disable_s1_agent_m0_write;                              // link_disable_s1_agent:m0_write -> link_disable_s1_translator:uav_write
	wire    [2:0] link_disable_s1_agent_m0_burstcount;                         // link_disable_s1_agent:m0_burstcount -> link_disable_s1_translator:uav_burstcount
	wire          link_disable_s1_agent_rf_source_valid;                       // link_disable_s1_agent:rf_source_valid -> link_disable_s1_agent_rsp_fifo:in_valid
	wire  [129:0] link_disable_s1_agent_rf_source_data;                        // link_disable_s1_agent:rf_source_data -> link_disable_s1_agent_rsp_fifo:in_data
	wire          link_disable_s1_agent_rf_source_ready;                       // link_disable_s1_agent_rsp_fifo:in_ready -> link_disable_s1_agent:rf_source_ready
	wire          link_disable_s1_agent_rf_source_startofpacket;               // link_disable_s1_agent:rf_source_startofpacket -> link_disable_s1_agent_rsp_fifo:in_startofpacket
	wire          link_disable_s1_agent_rf_source_endofpacket;                 // link_disable_s1_agent:rf_source_endofpacket -> link_disable_s1_agent_rsp_fifo:in_endofpacket
	wire          link_disable_s1_agent_rsp_fifo_out_valid;                    // link_disable_s1_agent_rsp_fifo:out_valid -> link_disable_s1_agent:rf_sink_valid
	wire  [129:0] link_disable_s1_agent_rsp_fifo_out_data;                     // link_disable_s1_agent_rsp_fifo:out_data -> link_disable_s1_agent:rf_sink_data
	wire          link_disable_s1_agent_rsp_fifo_out_ready;                    // link_disable_s1_agent:rf_sink_ready -> link_disable_s1_agent_rsp_fifo:out_ready
	wire          link_disable_s1_agent_rsp_fifo_out_startofpacket;            // link_disable_s1_agent_rsp_fifo:out_startofpacket -> link_disable_s1_agent:rf_sink_startofpacket
	wire          link_disable_s1_agent_rsp_fifo_out_endofpacket;              // link_disable_s1_agent_rsp_fifo:out_endofpacket -> link_disable_s1_agent:rf_sink_endofpacket
	wire          link_disable_s1_agent_rdata_fifo_src_valid;                  // link_disable_s1_agent:rdata_fifo_src_valid -> link_disable_s1_agent_rdata_fifo:in_valid
	wire   [33:0] link_disable_s1_agent_rdata_fifo_src_data;                   // link_disable_s1_agent:rdata_fifo_src_data -> link_disable_s1_agent_rdata_fifo:in_data
	wire          link_disable_s1_agent_rdata_fifo_src_ready;                  // link_disable_s1_agent_rdata_fifo:in_ready -> link_disable_s1_agent:rdata_fifo_src_ready
	wire   [31:0] write_data_fifo_tx_s1_agent_m0_readdata;                     // write_data_fifo_tx_s1_translator:uav_readdata -> write_data_fifo_tx_s1_agent:m0_readdata
	wire          write_data_fifo_tx_s1_agent_m0_waitrequest;                  // write_data_fifo_tx_s1_translator:uav_waitrequest -> write_data_fifo_tx_s1_agent:m0_waitrequest
	wire          write_data_fifo_tx_s1_agent_m0_debugaccess;                  // write_data_fifo_tx_s1_agent:m0_debugaccess -> write_data_fifo_tx_s1_translator:uav_debugaccess
	wire   [29:0] write_data_fifo_tx_s1_agent_m0_address;                      // write_data_fifo_tx_s1_agent:m0_address -> write_data_fifo_tx_s1_translator:uav_address
	wire    [3:0] write_data_fifo_tx_s1_agent_m0_byteenable;                   // write_data_fifo_tx_s1_agent:m0_byteenable -> write_data_fifo_tx_s1_translator:uav_byteenable
	wire          write_data_fifo_tx_s1_agent_m0_read;                         // write_data_fifo_tx_s1_agent:m0_read -> write_data_fifo_tx_s1_translator:uav_read
	wire          write_data_fifo_tx_s1_agent_m0_readdatavalid;                // write_data_fifo_tx_s1_translator:uav_readdatavalid -> write_data_fifo_tx_s1_agent:m0_readdatavalid
	wire          write_data_fifo_tx_s1_agent_m0_lock;                         // write_data_fifo_tx_s1_agent:m0_lock -> write_data_fifo_tx_s1_translator:uav_lock
	wire   [31:0] write_data_fifo_tx_s1_agent_m0_writedata;                    // write_data_fifo_tx_s1_agent:m0_writedata -> write_data_fifo_tx_s1_translator:uav_writedata
	wire          write_data_fifo_tx_s1_agent_m0_write;                        // write_data_fifo_tx_s1_agent:m0_write -> write_data_fifo_tx_s1_translator:uav_write
	wire    [2:0] write_data_fifo_tx_s1_agent_m0_burstcount;                   // write_data_fifo_tx_s1_agent:m0_burstcount -> write_data_fifo_tx_s1_translator:uav_burstcount
	wire          write_data_fifo_tx_s1_agent_rf_source_valid;                 // write_data_fifo_tx_s1_agent:rf_source_valid -> write_data_fifo_tx_s1_agent_rsp_fifo:in_valid
	wire  [129:0] write_data_fifo_tx_s1_agent_rf_source_data;                  // write_data_fifo_tx_s1_agent:rf_source_data -> write_data_fifo_tx_s1_agent_rsp_fifo:in_data
	wire          write_data_fifo_tx_s1_agent_rf_source_ready;                 // write_data_fifo_tx_s1_agent_rsp_fifo:in_ready -> write_data_fifo_tx_s1_agent:rf_source_ready
	wire          write_data_fifo_tx_s1_agent_rf_source_startofpacket;         // write_data_fifo_tx_s1_agent:rf_source_startofpacket -> write_data_fifo_tx_s1_agent_rsp_fifo:in_startofpacket
	wire          write_data_fifo_tx_s1_agent_rf_source_endofpacket;           // write_data_fifo_tx_s1_agent:rf_source_endofpacket -> write_data_fifo_tx_s1_agent_rsp_fifo:in_endofpacket
	wire          write_data_fifo_tx_s1_agent_rsp_fifo_out_valid;              // write_data_fifo_tx_s1_agent_rsp_fifo:out_valid -> write_data_fifo_tx_s1_agent:rf_sink_valid
	wire  [129:0] write_data_fifo_tx_s1_agent_rsp_fifo_out_data;               // write_data_fifo_tx_s1_agent_rsp_fifo:out_data -> write_data_fifo_tx_s1_agent:rf_sink_data
	wire          write_data_fifo_tx_s1_agent_rsp_fifo_out_ready;              // write_data_fifo_tx_s1_agent:rf_sink_ready -> write_data_fifo_tx_s1_agent_rsp_fifo:out_ready
	wire          write_data_fifo_tx_s1_agent_rsp_fifo_out_startofpacket;      // write_data_fifo_tx_s1_agent_rsp_fifo:out_startofpacket -> write_data_fifo_tx_s1_agent:rf_sink_startofpacket
	wire          write_data_fifo_tx_s1_agent_rsp_fifo_out_endofpacket;        // write_data_fifo_tx_s1_agent_rsp_fifo:out_endofpacket -> write_data_fifo_tx_s1_agent:rf_sink_endofpacket
	wire          write_data_fifo_tx_s1_agent_rdata_fifo_src_valid;            // write_data_fifo_tx_s1_agent:rdata_fifo_src_valid -> write_data_fifo_tx_s1_agent_rdata_fifo:in_valid
	wire   [33:0] write_data_fifo_tx_s1_agent_rdata_fifo_src_data;             // write_data_fifo_tx_s1_agent:rdata_fifo_src_data -> write_data_fifo_tx_s1_agent_rdata_fifo:in_data
	wire          write_data_fifo_tx_s1_agent_rdata_fifo_src_ready;            // write_data_fifo_tx_s1_agent_rdata_fifo:in_ready -> write_data_fifo_tx_s1_agent:rdata_fifo_src_ready
	wire   [31:0] write_en_tx_s1_agent_m0_readdata;                            // write_en_tx_s1_translator:uav_readdata -> write_en_tx_s1_agent:m0_readdata
	wire          write_en_tx_s1_agent_m0_waitrequest;                         // write_en_tx_s1_translator:uav_waitrequest -> write_en_tx_s1_agent:m0_waitrequest
	wire          write_en_tx_s1_agent_m0_debugaccess;                         // write_en_tx_s1_agent:m0_debugaccess -> write_en_tx_s1_translator:uav_debugaccess
	wire   [29:0] write_en_tx_s1_agent_m0_address;                             // write_en_tx_s1_agent:m0_address -> write_en_tx_s1_translator:uav_address
	wire    [3:0] write_en_tx_s1_agent_m0_byteenable;                          // write_en_tx_s1_agent:m0_byteenable -> write_en_tx_s1_translator:uav_byteenable
	wire          write_en_tx_s1_agent_m0_read;                                // write_en_tx_s1_agent:m0_read -> write_en_tx_s1_translator:uav_read
	wire          write_en_tx_s1_agent_m0_readdatavalid;                       // write_en_tx_s1_translator:uav_readdatavalid -> write_en_tx_s1_agent:m0_readdatavalid
	wire          write_en_tx_s1_agent_m0_lock;                                // write_en_tx_s1_agent:m0_lock -> write_en_tx_s1_translator:uav_lock
	wire   [31:0] write_en_tx_s1_agent_m0_writedata;                           // write_en_tx_s1_agent:m0_writedata -> write_en_tx_s1_translator:uav_writedata
	wire          write_en_tx_s1_agent_m0_write;                               // write_en_tx_s1_agent:m0_write -> write_en_tx_s1_translator:uav_write
	wire    [2:0] write_en_tx_s1_agent_m0_burstcount;                          // write_en_tx_s1_agent:m0_burstcount -> write_en_tx_s1_translator:uav_burstcount
	wire          write_en_tx_s1_agent_rf_source_valid;                        // write_en_tx_s1_agent:rf_source_valid -> write_en_tx_s1_agent_rsp_fifo:in_valid
	wire  [129:0] write_en_tx_s1_agent_rf_source_data;                         // write_en_tx_s1_agent:rf_source_data -> write_en_tx_s1_agent_rsp_fifo:in_data
	wire          write_en_tx_s1_agent_rf_source_ready;                        // write_en_tx_s1_agent_rsp_fifo:in_ready -> write_en_tx_s1_agent:rf_source_ready
	wire          write_en_tx_s1_agent_rf_source_startofpacket;                // write_en_tx_s1_agent:rf_source_startofpacket -> write_en_tx_s1_agent_rsp_fifo:in_startofpacket
	wire          write_en_tx_s1_agent_rf_source_endofpacket;                  // write_en_tx_s1_agent:rf_source_endofpacket -> write_en_tx_s1_agent_rsp_fifo:in_endofpacket
	wire          write_en_tx_s1_agent_rsp_fifo_out_valid;                     // write_en_tx_s1_agent_rsp_fifo:out_valid -> write_en_tx_s1_agent:rf_sink_valid
	wire  [129:0] write_en_tx_s1_agent_rsp_fifo_out_data;                      // write_en_tx_s1_agent_rsp_fifo:out_data -> write_en_tx_s1_agent:rf_sink_data
	wire          write_en_tx_s1_agent_rsp_fifo_out_ready;                     // write_en_tx_s1_agent:rf_sink_ready -> write_en_tx_s1_agent_rsp_fifo:out_ready
	wire          write_en_tx_s1_agent_rsp_fifo_out_startofpacket;             // write_en_tx_s1_agent_rsp_fifo:out_startofpacket -> write_en_tx_s1_agent:rf_sink_startofpacket
	wire          write_en_tx_s1_agent_rsp_fifo_out_endofpacket;               // write_en_tx_s1_agent_rsp_fifo:out_endofpacket -> write_en_tx_s1_agent:rf_sink_endofpacket
	wire          write_en_tx_s1_agent_rdata_fifo_src_valid;                   // write_en_tx_s1_agent:rdata_fifo_src_valid -> write_en_tx_s1_agent_rdata_fifo:in_valid
	wire   [33:0] write_en_tx_s1_agent_rdata_fifo_src_data;                    // write_en_tx_s1_agent:rdata_fifo_src_data -> write_en_tx_s1_agent_rdata_fifo:in_data
	wire          write_en_tx_s1_agent_rdata_fifo_src_ready;                   // write_en_tx_s1_agent_rdata_fifo:in_ready -> write_en_tx_s1_agent:rdata_fifo_src_ready
	wire   [31:0] fifo_full_tx_status_s1_agent_m0_readdata;                    // fifo_full_tx_status_s1_translator:uav_readdata -> fifo_full_tx_status_s1_agent:m0_readdata
	wire          fifo_full_tx_status_s1_agent_m0_waitrequest;                 // fifo_full_tx_status_s1_translator:uav_waitrequest -> fifo_full_tx_status_s1_agent:m0_waitrequest
	wire          fifo_full_tx_status_s1_agent_m0_debugaccess;                 // fifo_full_tx_status_s1_agent:m0_debugaccess -> fifo_full_tx_status_s1_translator:uav_debugaccess
	wire   [29:0] fifo_full_tx_status_s1_agent_m0_address;                     // fifo_full_tx_status_s1_agent:m0_address -> fifo_full_tx_status_s1_translator:uav_address
	wire    [3:0] fifo_full_tx_status_s1_agent_m0_byteenable;                  // fifo_full_tx_status_s1_agent:m0_byteenable -> fifo_full_tx_status_s1_translator:uav_byteenable
	wire          fifo_full_tx_status_s1_agent_m0_read;                        // fifo_full_tx_status_s1_agent:m0_read -> fifo_full_tx_status_s1_translator:uav_read
	wire          fifo_full_tx_status_s1_agent_m0_readdatavalid;               // fifo_full_tx_status_s1_translator:uav_readdatavalid -> fifo_full_tx_status_s1_agent:m0_readdatavalid
	wire          fifo_full_tx_status_s1_agent_m0_lock;                        // fifo_full_tx_status_s1_agent:m0_lock -> fifo_full_tx_status_s1_translator:uav_lock
	wire   [31:0] fifo_full_tx_status_s1_agent_m0_writedata;                   // fifo_full_tx_status_s1_agent:m0_writedata -> fifo_full_tx_status_s1_translator:uav_writedata
	wire          fifo_full_tx_status_s1_agent_m0_write;                       // fifo_full_tx_status_s1_agent:m0_write -> fifo_full_tx_status_s1_translator:uav_write
	wire    [2:0] fifo_full_tx_status_s1_agent_m0_burstcount;                  // fifo_full_tx_status_s1_agent:m0_burstcount -> fifo_full_tx_status_s1_translator:uav_burstcount
	wire          fifo_full_tx_status_s1_agent_rf_source_valid;                // fifo_full_tx_status_s1_agent:rf_source_valid -> fifo_full_tx_status_s1_agent_rsp_fifo:in_valid
	wire  [129:0] fifo_full_tx_status_s1_agent_rf_source_data;                 // fifo_full_tx_status_s1_agent:rf_source_data -> fifo_full_tx_status_s1_agent_rsp_fifo:in_data
	wire          fifo_full_tx_status_s1_agent_rf_source_ready;                // fifo_full_tx_status_s1_agent_rsp_fifo:in_ready -> fifo_full_tx_status_s1_agent:rf_source_ready
	wire          fifo_full_tx_status_s1_agent_rf_source_startofpacket;        // fifo_full_tx_status_s1_agent:rf_source_startofpacket -> fifo_full_tx_status_s1_agent_rsp_fifo:in_startofpacket
	wire          fifo_full_tx_status_s1_agent_rf_source_endofpacket;          // fifo_full_tx_status_s1_agent:rf_source_endofpacket -> fifo_full_tx_status_s1_agent_rsp_fifo:in_endofpacket
	wire          fifo_full_tx_status_s1_agent_rsp_fifo_out_valid;             // fifo_full_tx_status_s1_agent_rsp_fifo:out_valid -> fifo_full_tx_status_s1_agent:rf_sink_valid
	wire  [129:0] fifo_full_tx_status_s1_agent_rsp_fifo_out_data;              // fifo_full_tx_status_s1_agent_rsp_fifo:out_data -> fifo_full_tx_status_s1_agent:rf_sink_data
	wire          fifo_full_tx_status_s1_agent_rsp_fifo_out_ready;             // fifo_full_tx_status_s1_agent:rf_sink_ready -> fifo_full_tx_status_s1_agent_rsp_fifo:out_ready
	wire          fifo_full_tx_status_s1_agent_rsp_fifo_out_startofpacket;     // fifo_full_tx_status_s1_agent_rsp_fifo:out_startofpacket -> fifo_full_tx_status_s1_agent:rf_sink_startofpacket
	wire          fifo_full_tx_status_s1_agent_rsp_fifo_out_endofpacket;       // fifo_full_tx_status_s1_agent_rsp_fifo:out_endofpacket -> fifo_full_tx_status_s1_agent:rf_sink_endofpacket
	wire          fifo_full_tx_status_s1_agent_rdata_fifo_src_valid;           // fifo_full_tx_status_s1_agent:rdata_fifo_src_valid -> fifo_full_tx_status_s1_agent_rdata_fifo:in_valid
	wire   [33:0] fifo_full_tx_status_s1_agent_rdata_fifo_src_data;            // fifo_full_tx_status_s1_agent:rdata_fifo_src_data -> fifo_full_tx_status_s1_agent_rdata_fifo:in_data
	wire          fifo_full_tx_status_s1_agent_rdata_fifo_src_ready;           // fifo_full_tx_status_s1_agent_rdata_fifo:in_ready -> fifo_full_tx_status_s1_agent:rdata_fifo_src_ready
	wire   [31:0] fifo_empty_tx_status_s1_agent_m0_readdata;                   // fifo_empty_tx_status_s1_translator:uav_readdata -> fifo_empty_tx_status_s1_agent:m0_readdata
	wire          fifo_empty_tx_status_s1_agent_m0_waitrequest;                // fifo_empty_tx_status_s1_translator:uav_waitrequest -> fifo_empty_tx_status_s1_agent:m0_waitrequest
	wire          fifo_empty_tx_status_s1_agent_m0_debugaccess;                // fifo_empty_tx_status_s1_agent:m0_debugaccess -> fifo_empty_tx_status_s1_translator:uav_debugaccess
	wire   [29:0] fifo_empty_tx_status_s1_agent_m0_address;                    // fifo_empty_tx_status_s1_agent:m0_address -> fifo_empty_tx_status_s1_translator:uav_address
	wire    [3:0] fifo_empty_tx_status_s1_agent_m0_byteenable;                 // fifo_empty_tx_status_s1_agent:m0_byteenable -> fifo_empty_tx_status_s1_translator:uav_byteenable
	wire          fifo_empty_tx_status_s1_agent_m0_read;                       // fifo_empty_tx_status_s1_agent:m0_read -> fifo_empty_tx_status_s1_translator:uav_read
	wire          fifo_empty_tx_status_s1_agent_m0_readdatavalid;              // fifo_empty_tx_status_s1_translator:uav_readdatavalid -> fifo_empty_tx_status_s1_agent:m0_readdatavalid
	wire          fifo_empty_tx_status_s1_agent_m0_lock;                       // fifo_empty_tx_status_s1_agent:m0_lock -> fifo_empty_tx_status_s1_translator:uav_lock
	wire   [31:0] fifo_empty_tx_status_s1_agent_m0_writedata;                  // fifo_empty_tx_status_s1_agent:m0_writedata -> fifo_empty_tx_status_s1_translator:uav_writedata
	wire          fifo_empty_tx_status_s1_agent_m0_write;                      // fifo_empty_tx_status_s1_agent:m0_write -> fifo_empty_tx_status_s1_translator:uav_write
	wire    [2:0] fifo_empty_tx_status_s1_agent_m0_burstcount;                 // fifo_empty_tx_status_s1_agent:m0_burstcount -> fifo_empty_tx_status_s1_translator:uav_burstcount
	wire          fifo_empty_tx_status_s1_agent_rf_source_valid;               // fifo_empty_tx_status_s1_agent:rf_source_valid -> fifo_empty_tx_status_s1_agent_rsp_fifo:in_valid
	wire  [129:0] fifo_empty_tx_status_s1_agent_rf_source_data;                // fifo_empty_tx_status_s1_agent:rf_source_data -> fifo_empty_tx_status_s1_agent_rsp_fifo:in_data
	wire          fifo_empty_tx_status_s1_agent_rf_source_ready;               // fifo_empty_tx_status_s1_agent_rsp_fifo:in_ready -> fifo_empty_tx_status_s1_agent:rf_source_ready
	wire          fifo_empty_tx_status_s1_agent_rf_source_startofpacket;       // fifo_empty_tx_status_s1_agent:rf_source_startofpacket -> fifo_empty_tx_status_s1_agent_rsp_fifo:in_startofpacket
	wire          fifo_empty_tx_status_s1_agent_rf_source_endofpacket;         // fifo_empty_tx_status_s1_agent:rf_source_endofpacket -> fifo_empty_tx_status_s1_agent_rsp_fifo:in_endofpacket
	wire          fifo_empty_tx_status_s1_agent_rsp_fifo_out_valid;            // fifo_empty_tx_status_s1_agent_rsp_fifo:out_valid -> fifo_empty_tx_status_s1_agent:rf_sink_valid
	wire  [129:0] fifo_empty_tx_status_s1_agent_rsp_fifo_out_data;             // fifo_empty_tx_status_s1_agent_rsp_fifo:out_data -> fifo_empty_tx_status_s1_agent:rf_sink_data
	wire          fifo_empty_tx_status_s1_agent_rsp_fifo_out_ready;            // fifo_empty_tx_status_s1_agent:rf_sink_ready -> fifo_empty_tx_status_s1_agent_rsp_fifo:out_ready
	wire          fifo_empty_tx_status_s1_agent_rsp_fifo_out_startofpacket;    // fifo_empty_tx_status_s1_agent_rsp_fifo:out_startofpacket -> fifo_empty_tx_status_s1_agent:rf_sink_startofpacket
	wire          fifo_empty_tx_status_s1_agent_rsp_fifo_out_endofpacket;      // fifo_empty_tx_status_s1_agent_rsp_fifo:out_endofpacket -> fifo_empty_tx_status_s1_agent:rf_sink_endofpacket
	wire          fifo_empty_tx_status_s1_agent_rdata_fifo_src_valid;          // fifo_empty_tx_status_s1_agent:rdata_fifo_src_valid -> fifo_empty_tx_status_s1_agent_rdata_fifo:in_valid
	wire   [33:0] fifo_empty_tx_status_s1_agent_rdata_fifo_src_data;           // fifo_empty_tx_status_s1_agent:rdata_fifo_src_data -> fifo_empty_tx_status_s1_agent_rdata_fifo:in_data
	wire          fifo_empty_tx_status_s1_agent_rdata_fifo_src_ready;          // fifo_empty_tx_status_s1_agent_rdata_fifo:in_ready -> fifo_empty_tx_status_s1_agent:rdata_fifo_src_ready
	wire   [31:0] timecode_tx_data_s1_agent_m0_readdata;                       // timecode_tx_data_s1_translator:uav_readdata -> timecode_tx_data_s1_agent:m0_readdata
	wire          timecode_tx_data_s1_agent_m0_waitrequest;                    // timecode_tx_data_s1_translator:uav_waitrequest -> timecode_tx_data_s1_agent:m0_waitrequest
	wire          timecode_tx_data_s1_agent_m0_debugaccess;                    // timecode_tx_data_s1_agent:m0_debugaccess -> timecode_tx_data_s1_translator:uav_debugaccess
	wire   [29:0] timecode_tx_data_s1_agent_m0_address;                        // timecode_tx_data_s1_agent:m0_address -> timecode_tx_data_s1_translator:uav_address
	wire    [3:0] timecode_tx_data_s1_agent_m0_byteenable;                     // timecode_tx_data_s1_agent:m0_byteenable -> timecode_tx_data_s1_translator:uav_byteenable
	wire          timecode_tx_data_s1_agent_m0_read;                           // timecode_tx_data_s1_agent:m0_read -> timecode_tx_data_s1_translator:uav_read
	wire          timecode_tx_data_s1_agent_m0_readdatavalid;                  // timecode_tx_data_s1_translator:uav_readdatavalid -> timecode_tx_data_s1_agent:m0_readdatavalid
	wire          timecode_tx_data_s1_agent_m0_lock;                           // timecode_tx_data_s1_agent:m0_lock -> timecode_tx_data_s1_translator:uav_lock
	wire   [31:0] timecode_tx_data_s1_agent_m0_writedata;                      // timecode_tx_data_s1_agent:m0_writedata -> timecode_tx_data_s1_translator:uav_writedata
	wire          timecode_tx_data_s1_agent_m0_write;                          // timecode_tx_data_s1_agent:m0_write -> timecode_tx_data_s1_translator:uav_write
	wire    [2:0] timecode_tx_data_s1_agent_m0_burstcount;                     // timecode_tx_data_s1_agent:m0_burstcount -> timecode_tx_data_s1_translator:uav_burstcount
	wire          timecode_tx_data_s1_agent_rf_source_valid;                   // timecode_tx_data_s1_agent:rf_source_valid -> timecode_tx_data_s1_agent_rsp_fifo:in_valid
	wire  [129:0] timecode_tx_data_s1_agent_rf_source_data;                    // timecode_tx_data_s1_agent:rf_source_data -> timecode_tx_data_s1_agent_rsp_fifo:in_data
	wire          timecode_tx_data_s1_agent_rf_source_ready;                   // timecode_tx_data_s1_agent_rsp_fifo:in_ready -> timecode_tx_data_s1_agent:rf_source_ready
	wire          timecode_tx_data_s1_agent_rf_source_startofpacket;           // timecode_tx_data_s1_agent:rf_source_startofpacket -> timecode_tx_data_s1_agent_rsp_fifo:in_startofpacket
	wire          timecode_tx_data_s1_agent_rf_source_endofpacket;             // timecode_tx_data_s1_agent:rf_source_endofpacket -> timecode_tx_data_s1_agent_rsp_fifo:in_endofpacket
	wire          timecode_tx_data_s1_agent_rsp_fifo_out_valid;                // timecode_tx_data_s1_agent_rsp_fifo:out_valid -> timecode_tx_data_s1_agent:rf_sink_valid
	wire  [129:0] timecode_tx_data_s1_agent_rsp_fifo_out_data;                 // timecode_tx_data_s1_agent_rsp_fifo:out_data -> timecode_tx_data_s1_agent:rf_sink_data
	wire          timecode_tx_data_s1_agent_rsp_fifo_out_ready;                // timecode_tx_data_s1_agent:rf_sink_ready -> timecode_tx_data_s1_agent_rsp_fifo:out_ready
	wire          timecode_tx_data_s1_agent_rsp_fifo_out_startofpacket;        // timecode_tx_data_s1_agent_rsp_fifo:out_startofpacket -> timecode_tx_data_s1_agent:rf_sink_startofpacket
	wire          timecode_tx_data_s1_agent_rsp_fifo_out_endofpacket;          // timecode_tx_data_s1_agent_rsp_fifo:out_endofpacket -> timecode_tx_data_s1_agent:rf_sink_endofpacket
	wire          timecode_tx_data_s1_agent_rdata_fifo_src_valid;              // timecode_tx_data_s1_agent:rdata_fifo_src_valid -> timecode_tx_data_s1_agent_rdata_fifo:in_valid
	wire   [33:0] timecode_tx_data_s1_agent_rdata_fifo_src_data;               // timecode_tx_data_s1_agent:rdata_fifo_src_data -> timecode_tx_data_s1_agent_rdata_fifo:in_data
	wire          timecode_tx_data_s1_agent_rdata_fifo_src_ready;              // timecode_tx_data_s1_agent_rdata_fifo:in_ready -> timecode_tx_data_s1_agent:rdata_fifo_src_ready
	wire   [31:0] timecode_tx_enable_s1_agent_m0_readdata;                     // timecode_tx_enable_s1_translator:uav_readdata -> timecode_tx_enable_s1_agent:m0_readdata
	wire          timecode_tx_enable_s1_agent_m0_waitrequest;                  // timecode_tx_enable_s1_translator:uav_waitrequest -> timecode_tx_enable_s1_agent:m0_waitrequest
	wire          timecode_tx_enable_s1_agent_m0_debugaccess;                  // timecode_tx_enable_s1_agent:m0_debugaccess -> timecode_tx_enable_s1_translator:uav_debugaccess
	wire   [29:0] timecode_tx_enable_s1_agent_m0_address;                      // timecode_tx_enable_s1_agent:m0_address -> timecode_tx_enable_s1_translator:uav_address
	wire    [3:0] timecode_tx_enable_s1_agent_m0_byteenable;                   // timecode_tx_enable_s1_agent:m0_byteenable -> timecode_tx_enable_s1_translator:uav_byteenable
	wire          timecode_tx_enable_s1_agent_m0_read;                         // timecode_tx_enable_s1_agent:m0_read -> timecode_tx_enable_s1_translator:uav_read
	wire          timecode_tx_enable_s1_agent_m0_readdatavalid;                // timecode_tx_enable_s1_translator:uav_readdatavalid -> timecode_tx_enable_s1_agent:m0_readdatavalid
	wire          timecode_tx_enable_s1_agent_m0_lock;                         // timecode_tx_enable_s1_agent:m0_lock -> timecode_tx_enable_s1_translator:uav_lock
	wire   [31:0] timecode_tx_enable_s1_agent_m0_writedata;                    // timecode_tx_enable_s1_agent:m0_writedata -> timecode_tx_enable_s1_translator:uav_writedata
	wire          timecode_tx_enable_s1_agent_m0_write;                        // timecode_tx_enable_s1_agent:m0_write -> timecode_tx_enable_s1_translator:uav_write
	wire    [2:0] timecode_tx_enable_s1_agent_m0_burstcount;                   // timecode_tx_enable_s1_agent:m0_burstcount -> timecode_tx_enable_s1_translator:uav_burstcount
	wire          timecode_tx_enable_s1_agent_rf_source_valid;                 // timecode_tx_enable_s1_agent:rf_source_valid -> timecode_tx_enable_s1_agent_rsp_fifo:in_valid
	wire  [129:0] timecode_tx_enable_s1_agent_rf_source_data;                  // timecode_tx_enable_s1_agent:rf_source_data -> timecode_tx_enable_s1_agent_rsp_fifo:in_data
	wire          timecode_tx_enable_s1_agent_rf_source_ready;                 // timecode_tx_enable_s1_agent_rsp_fifo:in_ready -> timecode_tx_enable_s1_agent:rf_source_ready
	wire          timecode_tx_enable_s1_agent_rf_source_startofpacket;         // timecode_tx_enable_s1_agent:rf_source_startofpacket -> timecode_tx_enable_s1_agent_rsp_fifo:in_startofpacket
	wire          timecode_tx_enable_s1_agent_rf_source_endofpacket;           // timecode_tx_enable_s1_agent:rf_source_endofpacket -> timecode_tx_enable_s1_agent_rsp_fifo:in_endofpacket
	wire          timecode_tx_enable_s1_agent_rsp_fifo_out_valid;              // timecode_tx_enable_s1_agent_rsp_fifo:out_valid -> timecode_tx_enable_s1_agent:rf_sink_valid
	wire  [129:0] timecode_tx_enable_s1_agent_rsp_fifo_out_data;               // timecode_tx_enable_s1_agent_rsp_fifo:out_data -> timecode_tx_enable_s1_agent:rf_sink_data
	wire          timecode_tx_enable_s1_agent_rsp_fifo_out_ready;              // timecode_tx_enable_s1_agent:rf_sink_ready -> timecode_tx_enable_s1_agent_rsp_fifo:out_ready
	wire          timecode_tx_enable_s1_agent_rsp_fifo_out_startofpacket;      // timecode_tx_enable_s1_agent_rsp_fifo:out_startofpacket -> timecode_tx_enable_s1_agent:rf_sink_startofpacket
	wire          timecode_tx_enable_s1_agent_rsp_fifo_out_endofpacket;        // timecode_tx_enable_s1_agent_rsp_fifo:out_endofpacket -> timecode_tx_enable_s1_agent:rf_sink_endofpacket
	wire          timecode_tx_enable_s1_agent_rdata_fifo_src_valid;            // timecode_tx_enable_s1_agent:rdata_fifo_src_valid -> timecode_tx_enable_s1_agent_rdata_fifo:in_valid
	wire   [33:0] timecode_tx_enable_s1_agent_rdata_fifo_src_data;             // timecode_tx_enable_s1_agent:rdata_fifo_src_data -> timecode_tx_enable_s1_agent_rdata_fifo:in_data
	wire          timecode_tx_enable_s1_agent_rdata_fifo_src_ready;            // timecode_tx_enable_s1_agent_rdata_fifo:in_ready -> timecode_tx_enable_s1_agent:rdata_fifo_src_ready
	wire   [31:0] timecode_tx_ready_s1_agent_m0_readdata;                      // timecode_tx_ready_s1_translator:uav_readdata -> timecode_tx_ready_s1_agent:m0_readdata
	wire          timecode_tx_ready_s1_agent_m0_waitrequest;                   // timecode_tx_ready_s1_translator:uav_waitrequest -> timecode_tx_ready_s1_agent:m0_waitrequest
	wire          timecode_tx_ready_s1_agent_m0_debugaccess;                   // timecode_tx_ready_s1_agent:m0_debugaccess -> timecode_tx_ready_s1_translator:uav_debugaccess
	wire   [29:0] timecode_tx_ready_s1_agent_m0_address;                       // timecode_tx_ready_s1_agent:m0_address -> timecode_tx_ready_s1_translator:uav_address
	wire    [3:0] timecode_tx_ready_s1_agent_m0_byteenable;                    // timecode_tx_ready_s1_agent:m0_byteenable -> timecode_tx_ready_s1_translator:uav_byteenable
	wire          timecode_tx_ready_s1_agent_m0_read;                          // timecode_tx_ready_s1_agent:m0_read -> timecode_tx_ready_s1_translator:uav_read
	wire          timecode_tx_ready_s1_agent_m0_readdatavalid;                 // timecode_tx_ready_s1_translator:uav_readdatavalid -> timecode_tx_ready_s1_agent:m0_readdatavalid
	wire          timecode_tx_ready_s1_agent_m0_lock;                          // timecode_tx_ready_s1_agent:m0_lock -> timecode_tx_ready_s1_translator:uav_lock
	wire   [31:0] timecode_tx_ready_s1_agent_m0_writedata;                     // timecode_tx_ready_s1_agent:m0_writedata -> timecode_tx_ready_s1_translator:uav_writedata
	wire          timecode_tx_ready_s1_agent_m0_write;                         // timecode_tx_ready_s1_agent:m0_write -> timecode_tx_ready_s1_translator:uav_write
	wire    [2:0] timecode_tx_ready_s1_agent_m0_burstcount;                    // timecode_tx_ready_s1_agent:m0_burstcount -> timecode_tx_ready_s1_translator:uav_burstcount
	wire          timecode_tx_ready_s1_agent_rf_source_valid;                  // timecode_tx_ready_s1_agent:rf_source_valid -> timecode_tx_ready_s1_agent_rsp_fifo:in_valid
	wire  [129:0] timecode_tx_ready_s1_agent_rf_source_data;                   // timecode_tx_ready_s1_agent:rf_source_data -> timecode_tx_ready_s1_agent_rsp_fifo:in_data
	wire          timecode_tx_ready_s1_agent_rf_source_ready;                  // timecode_tx_ready_s1_agent_rsp_fifo:in_ready -> timecode_tx_ready_s1_agent:rf_source_ready
	wire          timecode_tx_ready_s1_agent_rf_source_startofpacket;          // timecode_tx_ready_s1_agent:rf_source_startofpacket -> timecode_tx_ready_s1_agent_rsp_fifo:in_startofpacket
	wire          timecode_tx_ready_s1_agent_rf_source_endofpacket;            // timecode_tx_ready_s1_agent:rf_source_endofpacket -> timecode_tx_ready_s1_agent_rsp_fifo:in_endofpacket
	wire          timecode_tx_ready_s1_agent_rsp_fifo_out_valid;               // timecode_tx_ready_s1_agent_rsp_fifo:out_valid -> timecode_tx_ready_s1_agent:rf_sink_valid
	wire  [129:0] timecode_tx_ready_s1_agent_rsp_fifo_out_data;                // timecode_tx_ready_s1_agent_rsp_fifo:out_data -> timecode_tx_ready_s1_agent:rf_sink_data
	wire          timecode_tx_ready_s1_agent_rsp_fifo_out_ready;               // timecode_tx_ready_s1_agent:rf_sink_ready -> timecode_tx_ready_s1_agent_rsp_fifo:out_ready
	wire          timecode_tx_ready_s1_agent_rsp_fifo_out_startofpacket;       // timecode_tx_ready_s1_agent_rsp_fifo:out_startofpacket -> timecode_tx_ready_s1_agent:rf_sink_startofpacket
	wire          timecode_tx_ready_s1_agent_rsp_fifo_out_endofpacket;         // timecode_tx_ready_s1_agent_rsp_fifo:out_endofpacket -> timecode_tx_ready_s1_agent:rf_sink_endofpacket
	wire          timecode_tx_ready_s1_agent_rdata_fifo_src_valid;             // timecode_tx_ready_s1_agent:rdata_fifo_src_valid -> timecode_tx_ready_s1_agent_rdata_fifo:in_valid
	wire   [33:0] timecode_tx_ready_s1_agent_rdata_fifo_src_data;              // timecode_tx_ready_s1_agent:rdata_fifo_src_data -> timecode_tx_ready_s1_agent_rdata_fifo:in_data
	wire          timecode_tx_ready_s1_agent_rdata_fifo_src_ready;             // timecode_tx_ready_s1_agent_rdata_fifo:in_ready -> timecode_tx_ready_s1_agent:rdata_fifo_src_ready
	wire   [31:0] data_info_s1_agent_m0_readdata;                              // data_info_s1_translator:uav_readdata -> data_info_s1_agent:m0_readdata
	wire          data_info_s1_agent_m0_waitrequest;                           // data_info_s1_translator:uav_waitrequest -> data_info_s1_agent:m0_waitrequest
	wire          data_info_s1_agent_m0_debugaccess;                           // data_info_s1_agent:m0_debugaccess -> data_info_s1_translator:uav_debugaccess
	wire   [29:0] data_info_s1_agent_m0_address;                               // data_info_s1_agent:m0_address -> data_info_s1_translator:uav_address
	wire    [3:0] data_info_s1_agent_m0_byteenable;                            // data_info_s1_agent:m0_byteenable -> data_info_s1_translator:uav_byteenable
	wire          data_info_s1_agent_m0_read;                                  // data_info_s1_agent:m0_read -> data_info_s1_translator:uav_read
	wire          data_info_s1_agent_m0_readdatavalid;                         // data_info_s1_translator:uav_readdatavalid -> data_info_s1_agent:m0_readdatavalid
	wire          data_info_s1_agent_m0_lock;                                  // data_info_s1_agent:m0_lock -> data_info_s1_translator:uav_lock
	wire   [31:0] data_info_s1_agent_m0_writedata;                             // data_info_s1_agent:m0_writedata -> data_info_s1_translator:uav_writedata
	wire          data_info_s1_agent_m0_write;                                 // data_info_s1_agent:m0_write -> data_info_s1_translator:uav_write
	wire    [2:0] data_info_s1_agent_m0_burstcount;                            // data_info_s1_agent:m0_burstcount -> data_info_s1_translator:uav_burstcount
	wire          data_info_s1_agent_rf_source_valid;                          // data_info_s1_agent:rf_source_valid -> data_info_s1_agent_rsp_fifo:in_valid
	wire  [129:0] data_info_s1_agent_rf_source_data;                           // data_info_s1_agent:rf_source_data -> data_info_s1_agent_rsp_fifo:in_data
	wire          data_info_s1_agent_rf_source_ready;                          // data_info_s1_agent_rsp_fifo:in_ready -> data_info_s1_agent:rf_source_ready
	wire          data_info_s1_agent_rf_source_startofpacket;                  // data_info_s1_agent:rf_source_startofpacket -> data_info_s1_agent_rsp_fifo:in_startofpacket
	wire          data_info_s1_agent_rf_source_endofpacket;                    // data_info_s1_agent:rf_source_endofpacket -> data_info_s1_agent_rsp_fifo:in_endofpacket
	wire          data_info_s1_agent_rsp_fifo_out_valid;                       // data_info_s1_agent_rsp_fifo:out_valid -> data_info_s1_agent:rf_sink_valid
	wire  [129:0] data_info_s1_agent_rsp_fifo_out_data;                        // data_info_s1_agent_rsp_fifo:out_data -> data_info_s1_agent:rf_sink_data
	wire          data_info_s1_agent_rsp_fifo_out_ready;                       // data_info_s1_agent:rf_sink_ready -> data_info_s1_agent_rsp_fifo:out_ready
	wire          data_info_s1_agent_rsp_fifo_out_startofpacket;               // data_info_s1_agent_rsp_fifo:out_startofpacket -> data_info_s1_agent:rf_sink_startofpacket
	wire          data_info_s1_agent_rsp_fifo_out_endofpacket;                 // data_info_s1_agent_rsp_fifo:out_endofpacket -> data_info_s1_agent:rf_sink_endofpacket
	wire          data_info_s1_agent_rdata_fifo_src_valid;                     // data_info_s1_agent:rdata_fifo_src_valid -> data_info_s1_agent_rdata_fifo:in_valid
	wire   [33:0] data_info_s1_agent_rdata_fifo_src_data;                      // data_info_s1_agent:rdata_fifo_src_data -> data_info_s1_agent_rdata_fifo:in_data
	wire          data_info_s1_agent_rdata_fifo_src_ready;                     // data_info_s1_agent_rdata_fifo:in_ready -> data_info_s1_agent:rdata_fifo_src_ready
	wire   [31:0] clock_sel_s1_agent_m0_readdata;                              // clock_sel_s1_translator:uav_readdata -> clock_sel_s1_agent:m0_readdata
	wire          clock_sel_s1_agent_m0_waitrequest;                           // clock_sel_s1_translator:uav_waitrequest -> clock_sel_s1_agent:m0_waitrequest
	wire          clock_sel_s1_agent_m0_debugaccess;                           // clock_sel_s1_agent:m0_debugaccess -> clock_sel_s1_translator:uav_debugaccess
	wire   [29:0] clock_sel_s1_agent_m0_address;                               // clock_sel_s1_agent:m0_address -> clock_sel_s1_translator:uav_address
	wire    [3:0] clock_sel_s1_agent_m0_byteenable;                            // clock_sel_s1_agent:m0_byteenable -> clock_sel_s1_translator:uav_byteenable
	wire          clock_sel_s1_agent_m0_read;                                  // clock_sel_s1_agent:m0_read -> clock_sel_s1_translator:uav_read
	wire          clock_sel_s1_agent_m0_readdatavalid;                         // clock_sel_s1_translator:uav_readdatavalid -> clock_sel_s1_agent:m0_readdatavalid
	wire          clock_sel_s1_agent_m0_lock;                                  // clock_sel_s1_agent:m0_lock -> clock_sel_s1_translator:uav_lock
	wire   [31:0] clock_sel_s1_agent_m0_writedata;                             // clock_sel_s1_agent:m0_writedata -> clock_sel_s1_translator:uav_writedata
	wire          clock_sel_s1_agent_m0_write;                                 // clock_sel_s1_agent:m0_write -> clock_sel_s1_translator:uav_write
	wire    [2:0] clock_sel_s1_agent_m0_burstcount;                            // clock_sel_s1_agent:m0_burstcount -> clock_sel_s1_translator:uav_burstcount
	wire          clock_sel_s1_agent_rf_source_valid;                          // clock_sel_s1_agent:rf_source_valid -> clock_sel_s1_agent_rsp_fifo:in_valid
	wire  [129:0] clock_sel_s1_agent_rf_source_data;                           // clock_sel_s1_agent:rf_source_data -> clock_sel_s1_agent_rsp_fifo:in_data
	wire          clock_sel_s1_agent_rf_source_ready;                          // clock_sel_s1_agent_rsp_fifo:in_ready -> clock_sel_s1_agent:rf_source_ready
	wire          clock_sel_s1_agent_rf_source_startofpacket;                  // clock_sel_s1_agent:rf_source_startofpacket -> clock_sel_s1_agent_rsp_fifo:in_startofpacket
	wire          clock_sel_s1_agent_rf_source_endofpacket;                    // clock_sel_s1_agent:rf_source_endofpacket -> clock_sel_s1_agent_rsp_fifo:in_endofpacket
	wire          clock_sel_s1_agent_rsp_fifo_out_valid;                       // clock_sel_s1_agent_rsp_fifo:out_valid -> clock_sel_s1_agent:rf_sink_valid
	wire  [129:0] clock_sel_s1_agent_rsp_fifo_out_data;                        // clock_sel_s1_agent_rsp_fifo:out_data -> clock_sel_s1_agent:rf_sink_data
	wire          clock_sel_s1_agent_rsp_fifo_out_ready;                       // clock_sel_s1_agent:rf_sink_ready -> clock_sel_s1_agent_rsp_fifo:out_ready
	wire          clock_sel_s1_agent_rsp_fifo_out_startofpacket;               // clock_sel_s1_agent_rsp_fifo:out_startofpacket -> clock_sel_s1_agent:rf_sink_startofpacket
	wire          clock_sel_s1_agent_rsp_fifo_out_endofpacket;                 // clock_sel_s1_agent_rsp_fifo:out_endofpacket -> clock_sel_s1_agent:rf_sink_endofpacket
	wire          clock_sel_s1_agent_rdata_fifo_src_valid;                     // clock_sel_s1_agent:rdata_fifo_src_valid -> clock_sel_s1_agent_rdata_fifo:in_valid
	wire   [33:0] clock_sel_s1_agent_rdata_fifo_src_data;                      // clock_sel_s1_agent:rdata_fifo_src_data -> clock_sel_s1_agent_rdata_fifo:in_data
	wire          clock_sel_s1_agent_rdata_fifo_src_ready;                     // clock_sel_s1_agent_rdata_fifo:in_ready -> clock_sel_s1_agent:rdata_fifo_src_ready
	wire   [31:0] fsm_info_s1_agent_m0_readdata;                               // fsm_info_s1_translator:uav_readdata -> fsm_info_s1_agent:m0_readdata
	wire          fsm_info_s1_agent_m0_waitrequest;                            // fsm_info_s1_translator:uav_waitrequest -> fsm_info_s1_agent:m0_waitrequest
	wire          fsm_info_s1_agent_m0_debugaccess;                            // fsm_info_s1_agent:m0_debugaccess -> fsm_info_s1_translator:uav_debugaccess
	wire   [29:0] fsm_info_s1_agent_m0_address;                                // fsm_info_s1_agent:m0_address -> fsm_info_s1_translator:uav_address
	wire    [3:0] fsm_info_s1_agent_m0_byteenable;                             // fsm_info_s1_agent:m0_byteenable -> fsm_info_s1_translator:uav_byteenable
	wire          fsm_info_s1_agent_m0_read;                                   // fsm_info_s1_agent:m0_read -> fsm_info_s1_translator:uav_read
	wire          fsm_info_s1_agent_m0_readdatavalid;                          // fsm_info_s1_translator:uav_readdatavalid -> fsm_info_s1_agent:m0_readdatavalid
	wire          fsm_info_s1_agent_m0_lock;                                   // fsm_info_s1_agent:m0_lock -> fsm_info_s1_translator:uav_lock
	wire   [31:0] fsm_info_s1_agent_m0_writedata;                              // fsm_info_s1_agent:m0_writedata -> fsm_info_s1_translator:uav_writedata
	wire          fsm_info_s1_agent_m0_write;                                  // fsm_info_s1_agent:m0_write -> fsm_info_s1_translator:uav_write
	wire    [2:0] fsm_info_s1_agent_m0_burstcount;                             // fsm_info_s1_agent:m0_burstcount -> fsm_info_s1_translator:uav_burstcount
	wire          fsm_info_s1_agent_rf_source_valid;                           // fsm_info_s1_agent:rf_source_valid -> fsm_info_s1_agent_rsp_fifo:in_valid
	wire  [129:0] fsm_info_s1_agent_rf_source_data;                            // fsm_info_s1_agent:rf_source_data -> fsm_info_s1_agent_rsp_fifo:in_data
	wire          fsm_info_s1_agent_rf_source_ready;                           // fsm_info_s1_agent_rsp_fifo:in_ready -> fsm_info_s1_agent:rf_source_ready
	wire          fsm_info_s1_agent_rf_source_startofpacket;                   // fsm_info_s1_agent:rf_source_startofpacket -> fsm_info_s1_agent_rsp_fifo:in_startofpacket
	wire          fsm_info_s1_agent_rf_source_endofpacket;                     // fsm_info_s1_agent:rf_source_endofpacket -> fsm_info_s1_agent_rsp_fifo:in_endofpacket
	wire          fsm_info_s1_agent_rsp_fifo_out_valid;                        // fsm_info_s1_agent_rsp_fifo:out_valid -> fsm_info_s1_agent:rf_sink_valid
	wire  [129:0] fsm_info_s1_agent_rsp_fifo_out_data;                         // fsm_info_s1_agent_rsp_fifo:out_data -> fsm_info_s1_agent:rf_sink_data
	wire          fsm_info_s1_agent_rsp_fifo_out_ready;                        // fsm_info_s1_agent:rf_sink_ready -> fsm_info_s1_agent_rsp_fifo:out_ready
	wire          fsm_info_s1_agent_rsp_fifo_out_startofpacket;                // fsm_info_s1_agent_rsp_fifo:out_startofpacket -> fsm_info_s1_agent:rf_sink_startofpacket
	wire          fsm_info_s1_agent_rsp_fifo_out_endofpacket;                  // fsm_info_s1_agent_rsp_fifo:out_endofpacket -> fsm_info_s1_agent:rf_sink_endofpacket
	wire          fsm_info_s1_agent_rdata_fifo_src_valid;                      // fsm_info_s1_agent:rdata_fifo_src_valid -> fsm_info_s1_agent_rdata_fifo:in_valid
	wire   [33:0] fsm_info_s1_agent_rdata_fifo_src_data;                       // fsm_info_s1_agent:rdata_fifo_src_data -> fsm_info_s1_agent_rdata_fifo:in_data
	wire          fsm_info_s1_agent_rdata_fifo_src_ready;                      // fsm_info_s1_agent_rdata_fifo:in_ready -> fsm_info_s1_agent:rdata_fifo_src_ready
	wire   [31:0] counter_tx_fifo_s1_agent_m0_readdata;                        // counter_tx_fifo_s1_translator:uav_readdata -> counter_tx_fifo_s1_agent:m0_readdata
	wire          counter_tx_fifo_s1_agent_m0_waitrequest;                     // counter_tx_fifo_s1_translator:uav_waitrequest -> counter_tx_fifo_s1_agent:m0_waitrequest
	wire          counter_tx_fifo_s1_agent_m0_debugaccess;                     // counter_tx_fifo_s1_agent:m0_debugaccess -> counter_tx_fifo_s1_translator:uav_debugaccess
	wire   [29:0] counter_tx_fifo_s1_agent_m0_address;                         // counter_tx_fifo_s1_agent:m0_address -> counter_tx_fifo_s1_translator:uav_address
	wire    [3:0] counter_tx_fifo_s1_agent_m0_byteenable;                      // counter_tx_fifo_s1_agent:m0_byteenable -> counter_tx_fifo_s1_translator:uav_byteenable
	wire          counter_tx_fifo_s1_agent_m0_read;                            // counter_tx_fifo_s1_agent:m0_read -> counter_tx_fifo_s1_translator:uav_read
	wire          counter_tx_fifo_s1_agent_m0_readdatavalid;                   // counter_tx_fifo_s1_translator:uav_readdatavalid -> counter_tx_fifo_s1_agent:m0_readdatavalid
	wire          counter_tx_fifo_s1_agent_m0_lock;                            // counter_tx_fifo_s1_agent:m0_lock -> counter_tx_fifo_s1_translator:uav_lock
	wire   [31:0] counter_tx_fifo_s1_agent_m0_writedata;                       // counter_tx_fifo_s1_agent:m0_writedata -> counter_tx_fifo_s1_translator:uav_writedata
	wire          counter_tx_fifo_s1_agent_m0_write;                           // counter_tx_fifo_s1_agent:m0_write -> counter_tx_fifo_s1_translator:uav_write
	wire    [2:0] counter_tx_fifo_s1_agent_m0_burstcount;                      // counter_tx_fifo_s1_agent:m0_burstcount -> counter_tx_fifo_s1_translator:uav_burstcount
	wire          counter_tx_fifo_s1_agent_rf_source_valid;                    // counter_tx_fifo_s1_agent:rf_source_valid -> counter_tx_fifo_s1_agent_rsp_fifo:in_valid
	wire  [129:0] counter_tx_fifo_s1_agent_rf_source_data;                     // counter_tx_fifo_s1_agent:rf_source_data -> counter_tx_fifo_s1_agent_rsp_fifo:in_data
	wire          counter_tx_fifo_s1_agent_rf_source_ready;                    // counter_tx_fifo_s1_agent_rsp_fifo:in_ready -> counter_tx_fifo_s1_agent:rf_source_ready
	wire          counter_tx_fifo_s1_agent_rf_source_startofpacket;            // counter_tx_fifo_s1_agent:rf_source_startofpacket -> counter_tx_fifo_s1_agent_rsp_fifo:in_startofpacket
	wire          counter_tx_fifo_s1_agent_rf_source_endofpacket;              // counter_tx_fifo_s1_agent:rf_source_endofpacket -> counter_tx_fifo_s1_agent_rsp_fifo:in_endofpacket
	wire          counter_tx_fifo_s1_agent_rsp_fifo_out_valid;                 // counter_tx_fifo_s1_agent_rsp_fifo:out_valid -> counter_tx_fifo_s1_agent:rf_sink_valid
	wire  [129:0] counter_tx_fifo_s1_agent_rsp_fifo_out_data;                  // counter_tx_fifo_s1_agent_rsp_fifo:out_data -> counter_tx_fifo_s1_agent:rf_sink_data
	wire          counter_tx_fifo_s1_agent_rsp_fifo_out_ready;                 // counter_tx_fifo_s1_agent:rf_sink_ready -> counter_tx_fifo_s1_agent_rsp_fifo:out_ready
	wire          counter_tx_fifo_s1_agent_rsp_fifo_out_startofpacket;         // counter_tx_fifo_s1_agent_rsp_fifo:out_startofpacket -> counter_tx_fifo_s1_agent:rf_sink_startofpacket
	wire          counter_tx_fifo_s1_agent_rsp_fifo_out_endofpacket;           // counter_tx_fifo_s1_agent_rsp_fifo:out_endofpacket -> counter_tx_fifo_s1_agent:rf_sink_endofpacket
	wire          counter_tx_fifo_s1_agent_rdata_fifo_src_valid;               // counter_tx_fifo_s1_agent:rdata_fifo_src_valid -> counter_tx_fifo_s1_agent_rdata_fifo:in_valid
	wire   [33:0] counter_tx_fifo_s1_agent_rdata_fifo_src_data;                // counter_tx_fifo_s1_agent:rdata_fifo_src_data -> counter_tx_fifo_s1_agent_rdata_fifo:in_data
	wire          counter_tx_fifo_s1_agent_rdata_fifo_src_ready;               // counter_tx_fifo_s1_agent_rdata_fifo:in_ready -> counter_tx_fifo_s1_agent:rdata_fifo_src_ready
	wire   [31:0] counter_rx_fifo_s1_agent_m0_readdata;                        // counter_rx_fifo_s1_translator:uav_readdata -> counter_rx_fifo_s1_agent:m0_readdata
	wire          counter_rx_fifo_s1_agent_m0_waitrequest;                     // counter_rx_fifo_s1_translator:uav_waitrequest -> counter_rx_fifo_s1_agent:m0_waitrequest
	wire          counter_rx_fifo_s1_agent_m0_debugaccess;                     // counter_rx_fifo_s1_agent:m0_debugaccess -> counter_rx_fifo_s1_translator:uav_debugaccess
	wire   [29:0] counter_rx_fifo_s1_agent_m0_address;                         // counter_rx_fifo_s1_agent:m0_address -> counter_rx_fifo_s1_translator:uav_address
	wire    [3:0] counter_rx_fifo_s1_agent_m0_byteenable;                      // counter_rx_fifo_s1_agent:m0_byteenable -> counter_rx_fifo_s1_translator:uav_byteenable
	wire          counter_rx_fifo_s1_agent_m0_read;                            // counter_rx_fifo_s1_agent:m0_read -> counter_rx_fifo_s1_translator:uav_read
	wire          counter_rx_fifo_s1_agent_m0_readdatavalid;                   // counter_rx_fifo_s1_translator:uav_readdatavalid -> counter_rx_fifo_s1_agent:m0_readdatavalid
	wire          counter_rx_fifo_s1_agent_m0_lock;                            // counter_rx_fifo_s1_agent:m0_lock -> counter_rx_fifo_s1_translator:uav_lock
	wire   [31:0] counter_rx_fifo_s1_agent_m0_writedata;                       // counter_rx_fifo_s1_agent:m0_writedata -> counter_rx_fifo_s1_translator:uav_writedata
	wire          counter_rx_fifo_s1_agent_m0_write;                           // counter_rx_fifo_s1_agent:m0_write -> counter_rx_fifo_s1_translator:uav_write
	wire    [2:0] counter_rx_fifo_s1_agent_m0_burstcount;                      // counter_rx_fifo_s1_agent:m0_burstcount -> counter_rx_fifo_s1_translator:uav_burstcount
	wire          counter_rx_fifo_s1_agent_rf_source_valid;                    // counter_rx_fifo_s1_agent:rf_source_valid -> counter_rx_fifo_s1_agent_rsp_fifo:in_valid
	wire  [129:0] counter_rx_fifo_s1_agent_rf_source_data;                     // counter_rx_fifo_s1_agent:rf_source_data -> counter_rx_fifo_s1_agent_rsp_fifo:in_data
	wire          counter_rx_fifo_s1_agent_rf_source_ready;                    // counter_rx_fifo_s1_agent_rsp_fifo:in_ready -> counter_rx_fifo_s1_agent:rf_source_ready
	wire          counter_rx_fifo_s1_agent_rf_source_startofpacket;            // counter_rx_fifo_s1_agent:rf_source_startofpacket -> counter_rx_fifo_s1_agent_rsp_fifo:in_startofpacket
	wire          counter_rx_fifo_s1_agent_rf_source_endofpacket;              // counter_rx_fifo_s1_agent:rf_source_endofpacket -> counter_rx_fifo_s1_agent_rsp_fifo:in_endofpacket
	wire          counter_rx_fifo_s1_agent_rsp_fifo_out_valid;                 // counter_rx_fifo_s1_agent_rsp_fifo:out_valid -> counter_rx_fifo_s1_agent:rf_sink_valid
	wire  [129:0] counter_rx_fifo_s1_agent_rsp_fifo_out_data;                  // counter_rx_fifo_s1_agent_rsp_fifo:out_data -> counter_rx_fifo_s1_agent:rf_sink_data
	wire          counter_rx_fifo_s1_agent_rsp_fifo_out_ready;                 // counter_rx_fifo_s1_agent:rf_sink_ready -> counter_rx_fifo_s1_agent_rsp_fifo:out_ready
	wire          counter_rx_fifo_s1_agent_rsp_fifo_out_startofpacket;         // counter_rx_fifo_s1_agent_rsp_fifo:out_startofpacket -> counter_rx_fifo_s1_agent:rf_sink_startofpacket
	wire          counter_rx_fifo_s1_agent_rsp_fifo_out_endofpacket;           // counter_rx_fifo_s1_agent_rsp_fifo:out_endofpacket -> counter_rx_fifo_s1_agent:rf_sink_endofpacket
	wire          counter_rx_fifo_s1_agent_rdata_fifo_src_valid;               // counter_rx_fifo_s1_agent:rdata_fifo_src_valid -> counter_rx_fifo_s1_agent_rdata_fifo:in_valid
	wire   [33:0] counter_rx_fifo_s1_agent_rdata_fifo_src_data;                // counter_rx_fifo_s1_agent:rdata_fifo_src_data -> counter_rx_fifo_s1_agent_rdata_fifo:in_data
	wire          counter_rx_fifo_s1_agent_rdata_fifo_src_ready;               // counter_rx_fifo_s1_agent_rdata_fifo:in_ready -> counter_rx_fifo_s1_agent:rdata_fifo_src_ready
	wire          hps_0_h2f_axi_master_agent_write_cp_valid;                   // hps_0_h2f_axi_master_agent:write_cp_valid -> router:sink_valid
	wire  [128:0] hps_0_h2f_axi_master_agent_write_cp_data;                    // hps_0_h2f_axi_master_agent:write_cp_data -> router:sink_data
	wire          hps_0_h2f_axi_master_agent_write_cp_ready;                   // router:sink_ready -> hps_0_h2f_axi_master_agent:write_cp_ready
	wire          hps_0_h2f_axi_master_agent_write_cp_startofpacket;           // hps_0_h2f_axi_master_agent:write_cp_startofpacket -> router:sink_startofpacket
	wire          hps_0_h2f_axi_master_agent_write_cp_endofpacket;             // hps_0_h2f_axi_master_agent:write_cp_endofpacket -> router:sink_endofpacket
	wire          hps_0_h2f_axi_master_agent_read_cp_valid;                    // hps_0_h2f_axi_master_agent:read_cp_valid -> router_001:sink_valid
	wire  [128:0] hps_0_h2f_axi_master_agent_read_cp_data;                     // hps_0_h2f_axi_master_agent:read_cp_data -> router_001:sink_data
	wire          hps_0_h2f_axi_master_agent_read_cp_ready;                    // router_001:sink_ready -> hps_0_h2f_axi_master_agent:read_cp_ready
	wire          hps_0_h2f_axi_master_agent_read_cp_startofpacket;            // hps_0_h2f_axi_master_agent:read_cp_startofpacket -> router_001:sink_startofpacket
	wire          hps_0_h2f_axi_master_agent_read_cp_endofpacket;              // hps_0_h2f_axi_master_agent:read_cp_endofpacket -> router_001:sink_endofpacket
	wire          led_pio_test_s1_agent_rp_valid;                              // led_pio_test_s1_agent:rp_valid -> router_002:sink_valid
	wire  [128:0] led_pio_test_s1_agent_rp_data;                               // led_pio_test_s1_agent:rp_data -> router_002:sink_data
	wire          led_pio_test_s1_agent_rp_ready;                              // router_002:sink_ready -> led_pio_test_s1_agent:rp_ready
	wire          led_pio_test_s1_agent_rp_startofpacket;                      // led_pio_test_s1_agent:rp_startofpacket -> router_002:sink_startofpacket
	wire          led_pio_test_s1_agent_rp_endofpacket;                        // led_pio_test_s1_agent:rp_endofpacket -> router_002:sink_endofpacket
	wire          router_002_src_valid;                                        // router_002:src_valid -> rsp_demux:sink_valid
	wire  [128:0] router_002_src_data;                                         // router_002:src_data -> rsp_demux:sink_data
	wire          router_002_src_ready;                                        // rsp_demux:sink_ready -> router_002:src_ready
	wire   [21:0] router_002_src_channel;                                      // router_002:src_channel -> rsp_demux:sink_channel
	wire          router_002_src_startofpacket;                                // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
	wire          router_002_src_endofpacket;                                  // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
	wire          timecode_rx_s1_agent_rp_valid;                               // timecode_rx_s1_agent:rp_valid -> router_003:sink_valid
	wire  [128:0] timecode_rx_s1_agent_rp_data;                                // timecode_rx_s1_agent:rp_data -> router_003:sink_data
	wire          timecode_rx_s1_agent_rp_ready;                               // router_003:sink_ready -> timecode_rx_s1_agent:rp_ready
	wire          timecode_rx_s1_agent_rp_startofpacket;                       // timecode_rx_s1_agent:rp_startofpacket -> router_003:sink_startofpacket
	wire          timecode_rx_s1_agent_rp_endofpacket;                         // timecode_rx_s1_agent:rp_endofpacket -> router_003:sink_endofpacket
	wire          router_003_src_valid;                                        // router_003:src_valid -> rsp_demux_001:sink_valid
	wire  [128:0] router_003_src_data;                                         // router_003:src_data -> rsp_demux_001:sink_data
	wire          router_003_src_ready;                                        // rsp_demux_001:sink_ready -> router_003:src_ready
	wire   [21:0] router_003_src_channel;                                      // router_003:src_channel -> rsp_demux_001:sink_channel
	wire          router_003_src_startofpacket;                                // router_003:src_startofpacket -> rsp_demux_001:sink_startofpacket
	wire          router_003_src_endofpacket;                                  // router_003:src_endofpacket -> rsp_demux_001:sink_endofpacket
	wire          timecode_ready_rx_s1_agent_rp_valid;                         // timecode_ready_rx_s1_agent:rp_valid -> router_004:sink_valid
	wire  [128:0] timecode_ready_rx_s1_agent_rp_data;                          // timecode_ready_rx_s1_agent:rp_data -> router_004:sink_data
	wire          timecode_ready_rx_s1_agent_rp_ready;                         // router_004:sink_ready -> timecode_ready_rx_s1_agent:rp_ready
	wire          timecode_ready_rx_s1_agent_rp_startofpacket;                 // timecode_ready_rx_s1_agent:rp_startofpacket -> router_004:sink_startofpacket
	wire          timecode_ready_rx_s1_agent_rp_endofpacket;                   // timecode_ready_rx_s1_agent:rp_endofpacket -> router_004:sink_endofpacket
	wire          router_004_src_valid;                                        // router_004:src_valid -> rsp_demux_002:sink_valid
	wire  [128:0] router_004_src_data;                                         // router_004:src_data -> rsp_demux_002:sink_data
	wire          router_004_src_ready;                                        // rsp_demux_002:sink_ready -> router_004:src_ready
	wire   [21:0] router_004_src_channel;                                      // router_004:src_channel -> rsp_demux_002:sink_channel
	wire          router_004_src_startofpacket;                                // router_004:src_startofpacket -> rsp_demux_002:sink_startofpacket
	wire          router_004_src_endofpacket;                                  // router_004:src_endofpacket -> rsp_demux_002:sink_endofpacket
	wire          data_flag_rx_s1_agent_rp_valid;                              // data_flag_rx_s1_agent:rp_valid -> router_005:sink_valid
	wire  [128:0] data_flag_rx_s1_agent_rp_data;                               // data_flag_rx_s1_agent:rp_data -> router_005:sink_data
	wire          data_flag_rx_s1_agent_rp_ready;                              // router_005:sink_ready -> data_flag_rx_s1_agent:rp_ready
	wire          data_flag_rx_s1_agent_rp_startofpacket;                      // data_flag_rx_s1_agent:rp_startofpacket -> router_005:sink_startofpacket
	wire          data_flag_rx_s1_agent_rp_endofpacket;                        // data_flag_rx_s1_agent:rp_endofpacket -> router_005:sink_endofpacket
	wire          router_005_src_valid;                                        // router_005:src_valid -> rsp_demux_003:sink_valid
	wire  [128:0] router_005_src_data;                                         // router_005:src_data -> rsp_demux_003:sink_data
	wire          router_005_src_ready;                                        // rsp_demux_003:sink_ready -> router_005:src_ready
	wire   [21:0] router_005_src_channel;                                      // router_005:src_channel -> rsp_demux_003:sink_channel
	wire          router_005_src_startofpacket;                                // router_005:src_startofpacket -> rsp_demux_003:sink_startofpacket
	wire          router_005_src_endofpacket;                                  // router_005:src_endofpacket -> rsp_demux_003:sink_endofpacket
	wire          data_read_en_rx_s1_agent_rp_valid;                           // data_read_en_rx_s1_agent:rp_valid -> router_006:sink_valid
	wire  [128:0] data_read_en_rx_s1_agent_rp_data;                            // data_read_en_rx_s1_agent:rp_data -> router_006:sink_data
	wire          data_read_en_rx_s1_agent_rp_ready;                           // router_006:sink_ready -> data_read_en_rx_s1_agent:rp_ready
	wire          data_read_en_rx_s1_agent_rp_startofpacket;                   // data_read_en_rx_s1_agent:rp_startofpacket -> router_006:sink_startofpacket
	wire          data_read_en_rx_s1_agent_rp_endofpacket;                     // data_read_en_rx_s1_agent:rp_endofpacket -> router_006:sink_endofpacket
	wire          router_006_src_valid;                                        // router_006:src_valid -> rsp_demux_004:sink_valid
	wire  [128:0] router_006_src_data;                                         // router_006:src_data -> rsp_demux_004:sink_data
	wire          router_006_src_ready;                                        // rsp_demux_004:sink_ready -> router_006:src_ready
	wire   [21:0] router_006_src_channel;                                      // router_006:src_channel -> rsp_demux_004:sink_channel
	wire          router_006_src_startofpacket;                                // router_006:src_startofpacket -> rsp_demux_004:sink_startofpacket
	wire          router_006_src_endofpacket;                                  // router_006:src_endofpacket -> rsp_demux_004:sink_endofpacket
	wire          fifo_full_rx_status_s1_agent_rp_valid;                       // fifo_full_rx_status_s1_agent:rp_valid -> router_007:sink_valid
	wire  [128:0] fifo_full_rx_status_s1_agent_rp_data;                        // fifo_full_rx_status_s1_agent:rp_data -> router_007:sink_data
	wire          fifo_full_rx_status_s1_agent_rp_ready;                       // router_007:sink_ready -> fifo_full_rx_status_s1_agent:rp_ready
	wire          fifo_full_rx_status_s1_agent_rp_startofpacket;               // fifo_full_rx_status_s1_agent:rp_startofpacket -> router_007:sink_startofpacket
	wire          fifo_full_rx_status_s1_agent_rp_endofpacket;                 // fifo_full_rx_status_s1_agent:rp_endofpacket -> router_007:sink_endofpacket
	wire          router_007_src_valid;                                        // router_007:src_valid -> rsp_demux_005:sink_valid
	wire  [128:0] router_007_src_data;                                         // router_007:src_data -> rsp_demux_005:sink_data
	wire          router_007_src_ready;                                        // rsp_demux_005:sink_ready -> router_007:src_ready
	wire   [21:0] router_007_src_channel;                                      // router_007:src_channel -> rsp_demux_005:sink_channel
	wire          router_007_src_startofpacket;                                // router_007:src_startofpacket -> rsp_demux_005:sink_startofpacket
	wire          router_007_src_endofpacket;                                  // router_007:src_endofpacket -> rsp_demux_005:sink_endofpacket
	wire          fifo_empty_rx_status_s1_agent_rp_valid;                      // fifo_empty_rx_status_s1_agent:rp_valid -> router_008:sink_valid
	wire  [128:0] fifo_empty_rx_status_s1_agent_rp_data;                       // fifo_empty_rx_status_s1_agent:rp_data -> router_008:sink_data
	wire          fifo_empty_rx_status_s1_agent_rp_ready;                      // router_008:sink_ready -> fifo_empty_rx_status_s1_agent:rp_ready
	wire          fifo_empty_rx_status_s1_agent_rp_startofpacket;              // fifo_empty_rx_status_s1_agent:rp_startofpacket -> router_008:sink_startofpacket
	wire          fifo_empty_rx_status_s1_agent_rp_endofpacket;                // fifo_empty_rx_status_s1_agent:rp_endofpacket -> router_008:sink_endofpacket
	wire          router_008_src_valid;                                        // router_008:src_valid -> rsp_demux_006:sink_valid
	wire  [128:0] router_008_src_data;                                         // router_008:src_data -> rsp_demux_006:sink_data
	wire          router_008_src_ready;                                        // rsp_demux_006:sink_ready -> router_008:src_ready
	wire   [21:0] router_008_src_channel;                                      // router_008:src_channel -> rsp_demux_006:sink_channel
	wire          router_008_src_startofpacket;                                // router_008:src_startofpacket -> rsp_demux_006:sink_startofpacket
	wire          router_008_src_endofpacket;                                  // router_008:src_endofpacket -> rsp_demux_006:sink_endofpacket
	wire          link_start_s1_agent_rp_valid;                                // link_start_s1_agent:rp_valid -> router_009:sink_valid
	wire  [128:0] link_start_s1_agent_rp_data;                                 // link_start_s1_agent:rp_data -> router_009:sink_data
	wire          link_start_s1_agent_rp_ready;                                // router_009:sink_ready -> link_start_s1_agent:rp_ready
	wire          link_start_s1_agent_rp_startofpacket;                        // link_start_s1_agent:rp_startofpacket -> router_009:sink_startofpacket
	wire          link_start_s1_agent_rp_endofpacket;                          // link_start_s1_agent:rp_endofpacket -> router_009:sink_endofpacket
	wire          router_009_src_valid;                                        // router_009:src_valid -> rsp_demux_007:sink_valid
	wire  [128:0] router_009_src_data;                                         // router_009:src_data -> rsp_demux_007:sink_data
	wire          router_009_src_ready;                                        // rsp_demux_007:sink_ready -> router_009:src_ready
	wire   [21:0] router_009_src_channel;                                      // router_009:src_channel -> rsp_demux_007:sink_channel
	wire          router_009_src_startofpacket;                                // router_009:src_startofpacket -> rsp_demux_007:sink_startofpacket
	wire          router_009_src_endofpacket;                                  // router_009:src_endofpacket -> rsp_demux_007:sink_endofpacket
	wire          auto_start_s1_agent_rp_valid;                                // auto_start_s1_agent:rp_valid -> router_010:sink_valid
	wire  [128:0] auto_start_s1_agent_rp_data;                                 // auto_start_s1_agent:rp_data -> router_010:sink_data
	wire          auto_start_s1_agent_rp_ready;                                // router_010:sink_ready -> auto_start_s1_agent:rp_ready
	wire          auto_start_s1_agent_rp_startofpacket;                        // auto_start_s1_agent:rp_startofpacket -> router_010:sink_startofpacket
	wire          auto_start_s1_agent_rp_endofpacket;                          // auto_start_s1_agent:rp_endofpacket -> router_010:sink_endofpacket
	wire          router_010_src_valid;                                        // router_010:src_valid -> rsp_demux_008:sink_valid
	wire  [128:0] router_010_src_data;                                         // router_010:src_data -> rsp_demux_008:sink_data
	wire          router_010_src_ready;                                        // rsp_demux_008:sink_ready -> router_010:src_ready
	wire   [21:0] router_010_src_channel;                                      // router_010:src_channel -> rsp_demux_008:sink_channel
	wire          router_010_src_startofpacket;                                // router_010:src_startofpacket -> rsp_demux_008:sink_startofpacket
	wire          router_010_src_endofpacket;                                  // router_010:src_endofpacket -> rsp_demux_008:sink_endofpacket
	wire          link_disable_s1_agent_rp_valid;                              // link_disable_s1_agent:rp_valid -> router_011:sink_valid
	wire  [128:0] link_disable_s1_agent_rp_data;                               // link_disable_s1_agent:rp_data -> router_011:sink_data
	wire          link_disable_s1_agent_rp_ready;                              // router_011:sink_ready -> link_disable_s1_agent:rp_ready
	wire          link_disable_s1_agent_rp_startofpacket;                      // link_disable_s1_agent:rp_startofpacket -> router_011:sink_startofpacket
	wire          link_disable_s1_agent_rp_endofpacket;                        // link_disable_s1_agent:rp_endofpacket -> router_011:sink_endofpacket
	wire          router_011_src_valid;                                        // router_011:src_valid -> rsp_demux_009:sink_valid
	wire  [128:0] router_011_src_data;                                         // router_011:src_data -> rsp_demux_009:sink_data
	wire          router_011_src_ready;                                        // rsp_demux_009:sink_ready -> router_011:src_ready
	wire   [21:0] router_011_src_channel;                                      // router_011:src_channel -> rsp_demux_009:sink_channel
	wire          router_011_src_startofpacket;                                // router_011:src_startofpacket -> rsp_demux_009:sink_startofpacket
	wire          router_011_src_endofpacket;                                  // router_011:src_endofpacket -> rsp_demux_009:sink_endofpacket
	wire          write_data_fifo_tx_s1_agent_rp_valid;                        // write_data_fifo_tx_s1_agent:rp_valid -> router_012:sink_valid
	wire  [128:0] write_data_fifo_tx_s1_agent_rp_data;                         // write_data_fifo_tx_s1_agent:rp_data -> router_012:sink_data
	wire          write_data_fifo_tx_s1_agent_rp_ready;                        // router_012:sink_ready -> write_data_fifo_tx_s1_agent:rp_ready
	wire          write_data_fifo_tx_s1_agent_rp_startofpacket;                // write_data_fifo_tx_s1_agent:rp_startofpacket -> router_012:sink_startofpacket
	wire          write_data_fifo_tx_s1_agent_rp_endofpacket;                  // write_data_fifo_tx_s1_agent:rp_endofpacket -> router_012:sink_endofpacket
	wire          router_012_src_valid;                                        // router_012:src_valid -> rsp_demux_010:sink_valid
	wire  [128:0] router_012_src_data;                                         // router_012:src_data -> rsp_demux_010:sink_data
	wire          router_012_src_ready;                                        // rsp_demux_010:sink_ready -> router_012:src_ready
	wire   [21:0] router_012_src_channel;                                      // router_012:src_channel -> rsp_demux_010:sink_channel
	wire          router_012_src_startofpacket;                                // router_012:src_startofpacket -> rsp_demux_010:sink_startofpacket
	wire          router_012_src_endofpacket;                                  // router_012:src_endofpacket -> rsp_demux_010:sink_endofpacket
	wire          write_en_tx_s1_agent_rp_valid;                               // write_en_tx_s1_agent:rp_valid -> router_013:sink_valid
	wire  [128:0] write_en_tx_s1_agent_rp_data;                                // write_en_tx_s1_agent:rp_data -> router_013:sink_data
	wire          write_en_tx_s1_agent_rp_ready;                               // router_013:sink_ready -> write_en_tx_s1_agent:rp_ready
	wire          write_en_tx_s1_agent_rp_startofpacket;                       // write_en_tx_s1_agent:rp_startofpacket -> router_013:sink_startofpacket
	wire          write_en_tx_s1_agent_rp_endofpacket;                         // write_en_tx_s1_agent:rp_endofpacket -> router_013:sink_endofpacket
	wire          router_013_src_valid;                                        // router_013:src_valid -> rsp_demux_011:sink_valid
	wire  [128:0] router_013_src_data;                                         // router_013:src_data -> rsp_demux_011:sink_data
	wire          router_013_src_ready;                                        // rsp_demux_011:sink_ready -> router_013:src_ready
	wire   [21:0] router_013_src_channel;                                      // router_013:src_channel -> rsp_demux_011:sink_channel
	wire          router_013_src_startofpacket;                                // router_013:src_startofpacket -> rsp_demux_011:sink_startofpacket
	wire          router_013_src_endofpacket;                                  // router_013:src_endofpacket -> rsp_demux_011:sink_endofpacket
	wire          fifo_full_tx_status_s1_agent_rp_valid;                       // fifo_full_tx_status_s1_agent:rp_valid -> router_014:sink_valid
	wire  [128:0] fifo_full_tx_status_s1_agent_rp_data;                        // fifo_full_tx_status_s1_agent:rp_data -> router_014:sink_data
	wire          fifo_full_tx_status_s1_agent_rp_ready;                       // router_014:sink_ready -> fifo_full_tx_status_s1_agent:rp_ready
	wire          fifo_full_tx_status_s1_agent_rp_startofpacket;               // fifo_full_tx_status_s1_agent:rp_startofpacket -> router_014:sink_startofpacket
	wire          fifo_full_tx_status_s1_agent_rp_endofpacket;                 // fifo_full_tx_status_s1_agent:rp_endofpacket -> router_014:sink_endofpacket
	wire          router_014_src_valid;                                        // router_014:src_valid -> rsp_demux_012:sink_valid
	wire  [128:0] router_014_src_data;                                         // router_014:src_data -> rsp_demux_012:sink_data
	wire          router_014_src_ready;                                        // rsp_demux_012:sink_ready -> router_014:src_ready
	wire   [21:0] router_014_src_channel;                                      // router_014:src_channel -> rsp_demux_012:sink_channel
	wire          router_014_src_startofpacket;                                // router_014:src_startofpacket -> rsp_demux_012:sink_startofpacket
	wire          router_014_src_endofpacket;                                  // router_014:src_endofpacket -> rsp_demux_012:sink_endofpacket
	wire          fifo_empty_tx_status_s1_agent_rp_valid;                      // fifo_empty_tx_status_s1_agent:rp_valid -> router_015:sink_valid
	wire  [128:0] fifo_empty_tx_status_s1_agent_rp_data;                       // fifo_empty_tx_status_s1_agent:rp_data -> router_015:sink_data
	wire          fifo_empty_tx_status_s1_agent_rp_ready;                      // router_015:sink_ready -> fifo_empty_tx_status_s1_agent:rp_ready
	wire          fifo_empty_tx_status_s1_agent_rp_startofpacket;              // fifo_empty_tx_status_s1_agent:rp_startofpacket -> router_015:sink_startofpacket
	wire          fifo_empty_tx_status_s1_agent_rp_endofpacket;                // fifo_empty_tx_status_s1_agent:rp_endofpacket -> router_015:sink_endofpacket
	wire          router_015_src_valid;                                        // router_015:src_valid -> rsp_demux_013:sink_valid
	wire  [128:0] router_015_src_data;                                         // router_015:src_data -> rsp_demux_013:sink_data
	wire          router_015_src_ready;                                        // rsp_demux_013:sink_ready -> router_015:src_ready
	wire   [21:0] router_015_src_channel;                                      // router_015:src_channel -> rsp_demux_013:sink_channel
	wire          router_015_src_startofpacket;                                // router_015:src_startofpacket -> rsp_demux_013:sink_startofpacket
	wire          router_015_src_endofpacket;                                  // router_015:src_endofpacket -> rsp_demux_013:sink_endofpacket
	wire          timecode_tx_data_s1_agent_rp_valid;                          // timecode_tx_data_s1_agent:rp_valid -> router_016:sink_valid
	wire  [128:0] timecode_tx_data_s1_agent_rp_data;                           // timecode_tx_data_s1_agent:rp_data -> router_016:sink_data
	wire          timecode_tx_data_s1_agent_rp_ready;                          // router_016:sink_ready -> timecode_tx_data_s1_agent:rp_ready
	wire          timecode_tx_data_s1_agent_rp_startofpacket;                  // timecode_tx_data_s1_agent:rp_startofpacket -> router_016:sink_startofpacket
	wire          timecode_tx_data_s1_agent_rp_endofpacket;                    // timecode_tx_data_s1_agent:rp_endofpacket -> router_016:sink_endofpacket
	wire          router_016_src_valid;                                        // router_016:src_valid -> rsp_demux_014:sink_valid
	wire  [128:0] router_016_src_data;                                         // router_016:src_data -> rsp_demux_014:sink_data
	wire          router_016_src_ready;                                        // rsp_demux_014:sink_ready -> router_016:src_ready
	wire   [21:0] router_016_src_channel;                                      // router_016:src_channel -> rsp_demux_014:sink_channel
	wire          router_016_src_startofpacket;                                // router_016:src_startofpacket -> rsp_demux_014:sink_startofpacket
	wire          router_016_src_endofpacket;                                  // router_016:src_endofpacket -> rsp_demux_014:sink_endofpacket
	wire          timecode_tx_enable_s1_agent_rp_valid;                        // timecode_tx_enable_s1_agent:rp_valid -> router_017:sink_valid
	wire  [128:0] timecode_tx_enable_s1_agent_rp_data;                         // timecode_tx_enable_s1_agent:rp_data -> router_017:sink_data
	wire          timecode_tx_enable_s1_agent_rp_ready;                        // router_017:sink_ready -> timecode_tx_enable_s1_agent:rp_ready
	wire          timecode_tx_enable_s1_agent_rp_startofpacket;                // timecode_tx_enable_s1_agent:rp_startofpacket -> router_017:sink_startofpacket
	wire          timecode_tx_enable_s1_agent_rp_endofpacket;                  // timecode_tx_enable_s1_agent:rp_endofpacket -> router_017:sink_endofpacket
	wire          router_017_src_valid;                                        // router_017:src_valid -> rsp_demux_015:sink_valid
	wire  [128:0] router_017_src_data;                                         // router_017:src_data -> rsp_demux_015:sink_data
	wire          router_017_src_ready;                                        // rsp_demux_015:sink_ready -> router_017:src_ready
	wire   [21:0] router_017_src_channel;                                      // router_017:src_channel -> rsp_demux_015:sink_channel
	wire          router_017_src_startofpacket;                                // router_017:src_startofpacket -> rsp_demux_015:sink_startofpacket
	wire          router_017_src_endofpacket;                                  // router_017:src_endofpacket -> rsp_demux_015:sink_endofpacket
	wire          timecode_tx_ready_s1_agent_rp_valid;                         // timecode_tx_ready_s1_agent:rp_valid -> router_018:sink_valid
	wire  [128:0] timecode_tx_ready_s1_agent_rp_data;                          // timecode_tx_ready_s1_agent:rp_data -> router_018:sink_data
	wire          timecode_tx_ready_s1_agent_rp_ready;                         // router_018:sink_ready -> timecode_tx_ready_s1_agent:rp_ready
	wire          timecode_tx_ready_s1_agent_rp_startofpacket;                 // timecode_tx_ready_s1_agent:rp_startofpacket -> router_018:sink_startofpacket
	wire          timecode_tx_ready_s1_agent_rp_endofpacket;                   // timecode_tx_ready_s1_agent:rp_endofpacket -> router_018:sink_endofpacket
	wire          router_018_src_valid;                                        // router_018:src_valid -> rsp_demux_016:sink_valid
	wire  [128:0] router_018_src_data;                                         // router_018:src_data -> rsp_demux_016:sink_data
	wire          router_018_src_ready;                                        // rsp_demux_016:sink_ready -> router_018:src_ready
	wire   [21:0] router_018_src_channel;                                      // router_018:src_channel -> rsp_demux_016:sink_channel
	wire          router_018_src_startofpacket;                                // router_018:src_startofpacket -> rsp_demux_016:sink_startofpacket
	wire          router_018_src_endofpacket;                                  // router_018:src_endofpacket -> rsp_demux_016:sink_endofpacket
	wire          data_info_s1_agent_rp_valid;                                 // data_info_s1_agent:rp_valid -> router_019:sink_valid
	wire  [128:0] data_info_s1_agent_rp_data;                                  // data_info_s1_agent:rp_data -> router_019:sink_data
	wire          data_info_s1_agent_rp_ready;                                 // router_019:sink_ready -> data_info_s1_agent:rp_ready
	wire          data_info_s1_agent_rp_startofpacket;                         // data_info_s1_agent:rp_startofpacket -> router_019:sink_startofpacket
	wire          data_info_s1_agent_rp_endofpacket;                           // data_info_s1_agent:rp_endofpacket -> router_019:sink_endofpacket
	wire          router_019_src_valid;                                        // router_019:src_valid -> rsp_demux_017:sink_valid
	wire  [128:0] router_019_src_data;                                         // router_019:src_data -> rsp_demux_017:sink_data
	wire          router_019_src_ready;                                        // rsp_demux_017:sink_ready -> router_019:src_ready
	wire   [21:0] router_019_src_channel;                                      // router_019:src_channel -> rsp_demux_017:sink_channel
	wire          router_019_src_startofpacket;                                // router_019:src_startofpacket -> rsp_demux_017:sink_startofpacket
	wire          router_019_src_endofpacket;                                  // router_019:src_endofpacket -> rsp_demux_017:sink_endofpacket
	wire          clock_sel_s1_agent_rp_valid;                                 // clock_sel_s1_agent:rp_valid -> router_020:sink_valid
	wire  [128:0] clock_sel_s1_agent_rp_data;                                  // clock_sel_s1_agent:rp_data -> router_020:sink_data
	wire          clock_sel_s1_agent_rp_ready;                                 // router_020:sink_ready -> clock_sel_s1_agent:rp_ready
	wire          clock_sel_s1_agent_rp_startofpacket;                         // clock_sel_s1_agent:rp_startofpacket -> router_020:sink_startofpacket
	wire          clock_sel_s1_agent_rp_endofpacket;                           // clock_sel_s1_agent:rp_endofpacket -> router_020:sink_endofpacket
	wire          router_020_src_valid;                                        // router_020:src_valid -> rsp_demux_018:sink_valid
	wire  [128:0] router_020_src_data;                                         // router_020:src_data -> rsp_demux_018:sink_data
	wire          router_020_src_ready;                                        // rsp_demux_018:sink_ready -> router_020:src_ready
	wire   [21:0] router_020_src_channel;                                      // router_020:src_channel -> rsp_demux_018:sink_channel
	wire          router_020_src_startofpacket;                                // router_020:src_startofpacket -> rsp_demux_018:sink_startofpacket
	wire          router_020_src_endofpacket;                                  // router_020:src_endofpacket -> rsp_demux_018:sink_endofpacket
	wire          fsm_info_s1_agent_rp_valid;                                  // fsm_info_s1_agent:rp_valid -> router_021:sink_valid
	wire  [128:0] fsm_info_s1_agent_rp_data;                                   // fsm_info_s1_agent:rp_data -> router_021:sink_data
	wire          fsm_info_s1_agent_rp_ready;                                  // router_021:sink_ready -> fsm_info_s1_agent:rp_ready
	wire          fsm_info_s1_agent_rp_startofpacket;                          // fsm_info_s1_agent:rp_startofpacket -> router_021:sink_startofpacket
	wire          fsm_info_s1_agent_rp_endofpacket;                            // fsm_info_s1_agent:rp_endofpacket -> router_021:sink_endofpacket
	wire          router_021_src_valid;                                        // router_021:src_valid -> rsp_demux_019:sink_valid
	wire  [128:0] router_021_src_data;                                         // router_021:src_data -> rsp_demux_019:sink_data
	wire          router_021_src_ready;                                        // rsp_demux_019:sink_ready -> router_021:src_ready
	wire   [21:0] router_021_src_channel;                                      // router_021:src_channel -> rsp_demux_019:sink_channel
	wire          router_021_src_startofpacket;                                // router_021:src_startofpacket -> rsp_demux_019:sink_startofpacket
	wire          router_021_src_endofpacket;                                  // router_021:src_endofpacket -> rsp_demux_019:sink_endofpacket
	wire          counter_tx_fifo_s1_agent_rp_valid;                           // counter_tx_fifo_s1_agent:rp_valid -> router_022:sink_valid
	wire  [128:0] counter_tx_fifo_s1_agent_rp_data;                            // counter_tx_fifo_s1_agent:rp_data -> router_022:sink_data
	wire          counter_tx_fifo_s1_agent_rp_ready;                           // router_022:sink_ready -> counter_tx_fifo_s1_agent:rp_ready
	wire          counter_tx_fifo_s1_agent_rp_startofpacket;                   // counter_tx_fifo_s1_agent:rp_startofpacket -> router_022:sink_startofpacket
	wire          counter_tx_fifo_s1_agent_rp_endofpacket;                     // counter_tx_fifo_s1_agent:rp_endofpacket -> router_022:sink_endofpacket
	wire          router_022_src_valid;                                        // router_022:src_valid -> rsp_demux_020:sink_valid
	wire  [128:0] router_022_src_data;                                         // router_022:src_data -> rsp_demux_020:sink_data
	wire          router_022_src_ready;                                        // rsp_demux_020:sink_ready -> router_022:src_ready
	wire   [21:0] router_022_src_channel;                                      // router_022:src_channel -> rsp_demux_020:sink_channel
	wire          router_022_src_startofpacket;                                // router_022:src_startofpacket -> rsp_demux_020:sink_startofpacket
	wire          router_022_src_endofpacket;                                  // router_022:src_endofpacket -> rsp_demux_020:sink_endofpacket
	wire          counter_rx_fifo_s1_agent_rp_valid;                           // counter_rx_fifo_s1_agent:rp_valid -> router_023:sink_valid
	wire  [128:0] counter_rx_fifo_s1_agent_rp_data;                            // counter_rx_fifo_s1_agent:rp_data -> router_023:sink_data
	wire          counter_rx_fifo_s1_agent_rp_ready;                           // router_023:sink_ready -> counter_rx_fifo_s1_agent:rp_ready
	wire          counter_rx_fifo_s1_agent_rp_startofpacket;                   // counter_rx_fifo_s1_agent:rp_startofpacket -> router_023:sink_startofpacket
	wire          counter_rx_fifo_s1_agent_rp_endofpacket;                     // counter_rx_fifo_s1_agent:rp_endofpacket -> router_023:sink_endofpacket
	wire          router_023_src_valid;                                        // router_023:src_valid -> rsp_demux_021:sink_valid
	wire  [128:0] router_023_src_data;                                         // router_023:src_data -> rsp_demux_021:sink_data
	wire          router_023_src_ready;                                        // rsp_demux_021:sink_ready -> router_023:src_ready
	wire   [21:0] router_023_src_channel;                                      // router_023:src_channel -> rsp_demux_021:sink_channel
	wire          router_023_src_startofpacket;                                // router_023:src_startofpacket -> rsp_demux_021:sink_startofpacket
	wire          router_023_src_endofpacket;                                  // router_023:src_endofpacket -> rsp_demux_021:sink_endofpacket
	wire          router_src_valid;                                            // router:src_valid -> hps_0_h2f_axi_master_wr_limiter:cmd_sink_valid
	wire  [128:0] router_src_data;                                             // router:src_data -> hps_0_h2f_axi_master_wr_limiter:cmd_sink_data
	wire          router_src_ready;                                            // hps_0_h2f_axi_master_wr_limiter:cmd_sink_ready -> router:src_ready
	wire   [21:0] router_src_channel;                                          // router:src_channel -> hps_0_h2f_axi_master_wr_limiter:cmd_sink_channel
	wire          router_src_startofpacket;                                    // router:src_startofpacket -> hps_0_h2f_axi_master_wr_limiter:cmd_sink_startofpacket
	wire          router_src_endofpacket;                                      // router:src_endofpacket -> hps_0_h2f_axi_master_wr_limiter:cmd_sink_endofpacket
	wire  [128:0] hps_0_h2f_axi_master_wr_limiter_cmd_src_data;                // hps_0_h2f_axi_master_wr_limiter:cmd_src_data -> cmd_demux:sink_data
	wire          hps_0_h2f_axi_master_wr_limiter_cmd_src_ready;               // cmd_demux:sink_ready -> hps_0_h2f_axi_master_wr_limiter:cmd_src_ready
	wire   [21:0] hps_0_h2f_axi_master_wr_limiter_cmd_src_channel;             // hps_0_h2f_axi_master_wr_limiter:cmd_src_channel -> cmd_demux:sink_channel
	wire          hps_0_h2f_axi_master_wr_limiter_cmd_src_startofpacket;       // hps_0_h2f_axi_master_wr_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
	wire          hps_0_h2f_axi_master_wr_limiter_cmd_src_endofpacket;         // hps_0_h2f_axi_master_wr_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
	wire          rsp_mux_src_valid;                                           // rsp_mux:src_valid -> hps_0_h2f_axi_master_wr_limiter:rsp_sink_valid
	wire  [128:0] rsp_mux_src_data;                                            // rsp_mux:src_data -> hps_0_h2f_axi_master_wr_limiter:rsp_sink_data
	wire          rsp_mux_src_ready;                                           // hps_0_h2f_axi_master_wr_limiter:rsp_sink_ready -> rsp_mux:src_ready
	wire   [21:0] rsp_mux_src_channel;                                         // rsp_mux:src_channel -> hps_0_h2f_axi_master_wr_limiter:rsp_sink_channel
	wire          rsp_mux_src_startofpacket;                                   // rsp_mux:src_startofpacket -> hps_0_h2f_axi_master_wr_limiter:rsp_sink_startofpacket
	wire          rsp_mux_src_endofpacket;                                     // rsp_mux:src_endofpacket -> hps_0_h2f_axi_master_wr_limiter:rsp_sink_endofpacket
	wire          hps_0_h2f_axi_master_wr_limiter_rsp_src_valid;               // hps_0_h2f_axi_master_wr_limiter:rsp_src_valid -> hps_0_h2f_axi_master_agent:write_rp_valid
	wire  [128:0] hps_0_h2f_axi_master_wr_limiter_rsp_src_data;                // hps_0_h2f_axi_master_wr_limiter:rsp_src_data -> hps_0_h2f_axi_master_agent:write_rp_data
	wire          hps_0_h2f_axi_master_wr_limiter_rsp_src_ready;               // hps_0_h2f_axi_master_agent:write_rp_ready -> hps_0_h2f_axi_master_wr_limiter:rsp_src_ready
	wire   [21:0] hps_0_h2f_axi_master_wr_limiter_rsp_src_channel;             // hps_0_h2f_axi_master_wr_limiter:rsp_src_channel -> hps_0_h2f_axi_master_agent:write_rp_channel
	wire          hps_0_h2f_axi_master_wr_limiter_rsp_src_startofpacket;       // hps_0_h2f_axi_master_wr_limiter:rsp_src_startofpacket -> hps_0_h2f_axi_master_agent:write_rp_startofpacket
	wire          hps_0_h2f_axi_master_wr_limiter_rsp_src_endofpacket;         // hps_0_h2f_axi_master_wr_limiter:rsp_src_endofpacket -> hps_0_h2f_axi_master_agent:write_rp_endofpacket
	wire          router_001_src_valid;                                        // router_001:src_valid -> hps_0_h2f_axi_master_rd_limiter:cmd_sink_valid
	wire  [128:0] router_001_src_data;                                         // router_001:src_data -> hps_0_h2f_axi_master_rd_limiter:cmd_sink_data
	wire          router_001_src_ready;                                        // hps_0_h2f_axi_master_rd_limiter:cmd_sink_ready -> router_001:src_ready
	wire   [21:0] router_001_src_channel;                                      // router_001:src_channel -> hps_0_h2f_axi_master_rd_limiter:cmd_sink_channel
	wire          router_001_src_startofpacket;                                // router_001:src_startofpacket -> hps_0_h2f_axi_master_rd_limiter:cmd_sink_startofpacket
	wire          router_001_src_endofpacket;                                  // router_001:src_endofpacket -> hps_0_h2f_axi_master_rd_limiter:cmd_sink_endofpacket
	wire  [128:0] hps_0_h2f_axi_master_rd_limiter_cmd_src_data;                // hps_0_h2f_axi_master_rd_limiter:cmd_src_data -> cmd_demux_001:sink_data
	wire          hps_0_h2f_axi_master_rd_limiter_cmd_src_ready;               // cmd_demux_001:sink_ready -> hps_0_h2f_axi_master_rd_limiter:cmd_src_ready
	wire   [21:0] hps_0_h2f_axi_master_rd_limiter_cmd_src_channel;             // hps_0_h2f_axi_master_rd_limiter:cmd_src_channel -> cmd_demux_001:sink_channel
	wire          hps_0_h2f_axi_master_rd_limiter_cmd_src_startofpacket;       // hps_0_h2f_axi_master_rd_limiter:cmd_src_startofpacket -> cmd_demux_001:sink_startofpacket
	wire          hps_0_h2f_axi_master_rd_limiter_cmd_src_endofpacket;         // hps_0_h2f_axi_master_rd_limiter:cmd_src_endofpacket -> cmd_demux_001:sink_endofpacket
	wire          rsp_mux_001_src_valid;                                       // rsp_mux_001:src_valid -> hps_0_h2f_axi_master_rd_limiter:rsp_sink_valid
	wire  [128:0] rsp_mux_001_src_data;                                        // rsp_mux_001:src_data -> hps_0_h2f_axi_master_rd_limiter:rsp_sink_data
	wire          rsp_mux_001_src_ready;                                       // hps_0_h2f_axi_master_rd_limiter:rsp_sink_ready -> rsp_mux_001:src_ready
	wire   [21:0] rsp_mux_001_src_channel;                                     // rsp_mux_001:src_channel -> hps_0_h2f_axi_master_rd_limiter:rsp_sink_channel
	wire          rsp_mux_001_src_startofpacket;                               // rsp_mux_001:src_startofpacket -> hps_0_h2f_axi_master_rd_limiter:rsp_sink_startofpacket
	wire          rsp_mux_001_src_endofpacket;                                 // rsp_mux_001:src_endofpacket -> hps_0_h2f_axi_master_rd_limiter:rsp_sink_endofpacket
	wire          hps_0_h2f_axi_master_rd_limiter_rsp_src_valid;               // hps_0_h2f_axi_master_rd_limiter:rsp_src_valid -> hps_0_h2f_axi_master_agent:read_rp_valid
	wire  [128:0] hps_0_h2f_axi_master_rd_limiter_rsp_src_data;                // hps_0_h2f_axi_master_rd_limiter:rsp_src_data -> hps_0_h2f_axi_master_agent:read_rp_data
	wire          hps_0_h2f_axi_master_rd_limiter_rsp_src_ready;               // hps_0_h2f_axi_master_agent:read_rp_ready -> hps_0_h2f_axi_master_rd_limiter:rsp_src_ready
	wire   [21:0] hps_0_h2f_axi_master_rd_limiter_rsp_src_channel;             // hps_0_h2f_axi_master_rd_limiter:rsp_src_channel -> hps_0_h2f_axi_master_agent:read_rp_channel
	wire          hps_0_h2f_axi_master_rd_limiter_rsp_src_startofpacket;       // hps_0_h2f_axi_master_rd_limiter:rsp_src_startofpacket -> hps_0_h2f_axi_master_agent:read_rp_startofpacket
	wire          hps_0_h2f_axi_master_rd_limiter_rsp_src_endofpacket;         // hps_0_h2f_axi_master_rd_limiter:rsp_src_endofpacket -> hps_0_h2f_axi_master_agent:read_rp_endofpacket
	wire          cmd_mux_src_valid;                                           // cmd_mux:src_valid -> led_pio_test_s1_burst_adapter:sink0_valid
	wire  [128:0] cmd_mux_src_data;                                            // cmd_mux:src_data -> led_pio_test_s1_burst_adapter:sink0_data
	wire          cmd_mux_src_ready;                                           // led_pio_test_s1_burst_adapter:sink0_ready -> cmd_mux:src_ready
	wire   [21:0] cmd_mux_src_channel;                                         // cmd_mux:src_channel -> led_pio_test_s1_burst_adapter:sink0_channel
	wire          cmd_mux_src_startofpacket;                                   // cmd_mux:src_startofpacket -> led_pio_test_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_src_endofpacket;                                     // cmd_mux:src_endofpacket -> led_pio_test_s1_burst_adapter:sink0_endofpacket
	wire          led_pio_test_s1_burst_adapter_source0_valid;                 // led_pio_test_s1_burst_adapter:source0_valid -> led_pio_test_s1_agent:cp_valid
	wire  [128:0] led_pio_test_s1_burst_adapter_source0_data;                  // led_pio_test_s1_burst_adapter:source0_data -> led_pio_test_s1_agent:cp_data
	wire          led_pio_test_s1_burst_adapter_source0_ready;                 // led_pio_test_s1_agent:cp_ready -> led_pio_test_s1_burst_adapter:source0_ready
	wire   [21:0] led_pio_test_s1_burst_adapter_source0_channel;               // led_pio_test_s1_burst_adapter:source0_channel -> led_pio_test_s1_agent:cp_channel
	wire          led_pio_test_s1_burst_adapter_source0_startofpacket;         // led_pio_test_s1_burst_adapter:source0_startofpacket -> led_pio_test_s1_agent:cp_startofpacket
	wire          led_pio_test_s1_burst_adapter_source0_endofpacket;           // led_pio_test_s1_burst_adapter:source0_endofpacket -> led_pio_test_s1_agent:cp_endofpacket
	wire          cmd_mux_001_src_valid;                                       // cmd_mux_001:src_valid -> timecode_rx_s1_burst_adapter:sink0_valid
	wire  [128:0] cmd_mux_001_src_data;                                        // cmd_mux_001:src_data -> timecode_rx_s1_burst_adapter:sink0_data
	wire          cmd_mux_001_src_ready;                                       // timecode_rx_s1_burst_adapter:sink0_ready -> cmd_mux_001:src_ready
	wire   [21:0] cmd_mux_001_src_channel;                                     // cmd_mux_001:src_channel -> timecode_rx_s1_burst_adapter:sink0_channel
	wire          cmd_mux_001_src_startofpacket;                               // cmd_mux_001:src_startofpacket -> timecode_rx_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_001_src_endofpacket;                                 // cmd_mux_001:src_endofpacket -> timecode_rx_s1_burst_adapter:sink0_endofpacket
	wire          timecode_rx_s1_burst_adapter_source0_valid;                  // timecode_rx_s1_burst_adapter:source0_valid -> timecode_rx_s1_agent:cp_valid
	wire  [128:0] timecode_rx_s1_burst_adapter_source0_data;                   // timecode_rx_s1_burst_adapter:source0_data -> timecode_rx_s1_agent:cp_data
	wire          timecode_rx_s1_burst_adapter_source0_ready;                  // timecode_rx_s1_agent:cp_ready -> timecode_rx_s1_burst_adapter:source0_ready
	wire   [21:0] timecode_rx_s1_burst_adapter_source0_channel;                // timecode_rx_s1_burst_adapter:source0_channel -> timecode_rx_s1_agent:cp_channel
	wire          timecode_rx_s1_burst_adapter_source0_startofpacket;          // timecode_rx_s1_burst_adapter:source0_startofpacket -> timecode_rx_s1_agent:cp_startofpacket
	wire          timecode_rx_s1_burst_adapter_source0_endofpacket;            // timecode_rx_s1_burst_adapter:source0_endofpacket -> timecode_rx_s1_agent:cp_endofpacket
	wire          cmd_mux_002_src_valid;                                       // cmd_mux_002:src_valid -> timecode_ready_rx_s1_burst_adapter:sink0_valid
	wire  [128:0] cmd_mux_002_src_data;                                        // cmd_mux_002:src_data -> timecode_ready_rx_s1_burst_adapter:sink0_data
	wire          cmd_mux_002_src_ready;                                       // timecode_ready_rx_s1_burst_adapter:sink0_ready -> cmd_mux_002:src_ready
	wire   [21:0] cmd_mux_002_src_channel;                                     // cmd_mux_002:src_channel -> timecode_ready_rx_s1_burst_adapter:sink0_channel
	wire          cmd_mux_002_src_startofpacket;                               // cmd_mux_002:src_startofpacket -> timecode_ready_rx_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_002_src_endofpacket;                                 // cmd_mux_002:src_endofpacket -> timecode_ready_rx_s1_burst_adapter:sink0_endofpacket
	wire          timecode_ready_rx_s1_burst_adapter_source0_valid;            // timecode_ready_rx_s1_burst_adapter:source0_valid -> timecode_ready_rx_s1_agent:cp_valid
	wire  [128:0] timecode_ready_rx_s1_burst_adapter_source0_data;             // timecode_ready_rx_s1_burst_adapter:source0_data -> timecode_ready_rx_s1_agent:cp_data
	wire          timecode_ready_rx_s1_burst_adapter_source0_ready;            // timecode_ready_rx_s1_agent:cp_ready -> timecode_ready_rx_s1_burst_adapter:source0_ready
	wire   [21:0] timecode_ready_rx_s1_burst_adapter_source0_channel;          // timecode_ready_rx_s1_burst_adapter:source0_channel -> timecode_ready_rx_s1_agent:cp_channel
	wire          timecode_ready_rx_s1_burst_adapter_source0_startofpacket;    // timecode_ready_rx_s1_burst_adapter:source0_startofpacket -> timecode_ready_rx_s1_agent:cp_startofpacket
	wire          timecode_ready_rx_s1_burst_adapter_source0_endofpacket;      // timecode_ready_rx_s1_burst_adapter:source0_endofpacket -> timecode_ready_rx_s1_agent:cp_endofpacket
	wire          cmd_mux_003_src_valid;                                       // cmd_mux_003:src_valid -> data_flag_rx_s1_burst_adapter:sink0_valid
	wire  [128:0] cmd_mux_003_src_data;                                        // cmd_mux_003:src_data -> data_flag_rx_s1_burst_adapter:sink0_data
	wire          cmd_mux_003_src_ready;                                       // data_flag_rx_s1_burst_adapter:sink0_ready -> cmd_mux_003:src_ready
	wire   [21:0] cmd_mux_003_src_channel;                                     // cmd_mux_003:src_channel -> data_flag_rx_s1_burst_adapter:sink0_channel
	wire          cmd_mux_003_src_startofpacket;                               // cmd_mux_003:src_startofpacket -> data_flag_rx_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_003_src_endofpacket;                                 // cmd_mux_003:src_endofpacket -> data_flag_rx_s1_burst_adapter:sink0_endofpacket
	wire          data_flag_rx_s1_burst_adapter_source0_valid;                 // data_flag_rx_s1_burst_adapter:source0_valid -> data_flag_rx_s1_agent:cp_valid
	wire  [128:0] data_flag_rx_s1_burst_adapter_source0_data;                  // data_flag_rx_s1_burst_adapter:source0_data -> data_flag_rx_s1_agent:cp_data
	wire          data_flag_rx_s1_burst_adapter_source0_ready;                 // data_flag_rx_s1_agent:cp_ready -> data_flag_rx_s1_burst_adapter:source0_ready
	wire   [21:0] data_flag_rx_s1_burst_adapter_source0_channel;               // data_flag_rx_s1_burst_adapter:source0_channel -> data_flag_rx_s1_agent:cp_channel
	wire          data_flag_rx_s1_burst_adapter_source0_startofpacket;         // data_flag_rx_s1_burst_adapter:source0_startofpacket -> data_flag_rx_s1_agent:cp_startofpacket
	wire          data_flag_rx_s1_burst_adapter_source0_endofpacket;           // data_flag_rx_s1_burst_adapter:source0_endofpacket -> data_flag_rx_s1_agent:cp_endofpacket
	wire          cmd_mux_004_src_valid;                                       // cmd_mux_004:src_valid -> data_read_en_rx_s1_burst_adapter:sink0_valid
	wire  [128:0] cmd_mux_004_src_data;                                        // cmd_mux_004:src_data -> data_read_en_rx_s1_burst_adapter:sink0_data
	wire          cmd_mux_004_src_ready;                                       // data_read_en_rx_s1_burst_adapter:sink0_ready -> cmd_mux_004:src_ready
	wire   [21:0] cmd_mux_004_src_channel;                                     // cmd_mux_004:src_channel -> data_read_en_rx_s1_burst_adapter:sink0_channel
	wire          cmd_mux_004_src_startofpacket;                               // cmd_mux_004:src_startofpacket -> data_read_en_rx_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_004_src_endofpacket;                                 // cmd_mux_004:src_endofpacket -> data_read_en_rx_s1_burst_adapter:sink0_endofpacket
	wire          data_read_en_rx_s1_burst_adapter_source0_valid;              // data_read_en_rx_s1_burst_adapter:source0_valid -> data_read_en_rx_s1_agent:cp_valid
	wire  [128:0] data_read_en_rx_s1_burst_adapter_source0_data;               // data_read_en_rx_s1_burst_adapter:source0_data -> data_read_en_rx_s1_agent:cp_data
	wire          data_read_en_rx_s1_burst_adapter_source0_ready;              // data_read_en_rx_s1_agent:cp_ready -> data_read_en_rx_s1_burst_adapter:source0_ready
	wire   [21:0] data_read_en_rx_s1_burst_adapter_source0_channel;            // data_read_en_rx_s1_burst_adapter:source0_channel -> data_read_en_rx_s1_agent:cp_channel
	wire          data_read_en_rx_s1_burst_adapter_source0_startofpacket;      // data_read_en_rx_s1_burst_adapter:source0_startofpacket -> data_read_en_rx_s1_agent:cp_startofpacket
	wire          data_read_en_rx_s1_burst_adapter_source0_endofpacket;        // data_read_en_rx_s1_burst_adapter:source0_endofpacket -> data_read_en_rx_s1_agent:cp_endofpacket
	wire          cmd_mux_005_src_valid;                                       // cmd_mux_005:src_valid -> fifo_full_rx_status_s1_burst_adapter:sink0_valid
	wire  [128:0] cmd_mux_005_src_data;                                        // cmd_mux_005:src_data -> fifo_full_rx_status_s1_burst_adapter:sink0_data
	wire          cmd_mux_005_src_ready;                                       // fifo_full_rx_status_s1_burst_adapter:sink0_ready -> cmd_mux_005:src_ready
	wire   [21:0] cmd_mux_005_src_channel;                                     // cmd_mux_005:src_channel -> fifo_full_rx_status_s1_burst_adapter:sink0_channel
	wire          cmd_mux_005_src_startofpacket;                               // cmd_mux_005:src_startofpacket -> fifo_full_rx_status_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_005_src_endofpacket;                                 // cmd_mux_005:src_endofpacket -> fifo_full_rx_status_s1_burst_adapter:sink0_endofpacket
	wire          fifo_full_rx_status_s1_burst_adapter_source0_valid;          // fifo_full_rx_status_s1_burst_adapter:source0_valid -> fifo_full_rx_status_s1_agent:cp_valid
	wire  [128:0] fifo_full_rx_status_s1_burst_adapter_source0_data;           // fifo_full_rx_status_s1_burst_adapter:source0_data -> fifo_full_rx_status_s1_agent:cp_data
	wire          fifo_full_rx_status_s1_burst_adapter_source0_ready;          // fifo_full_rx_status_s1_agent:cp_ready -> fifo_full_rx_status_s1_burst_adapter:source0_ready
	wire   [21:0] fifo_full_rx_status_s1_burst_adapter_source0_channel;        // fifo_full_rx_status_s1_burst_adapter:source0_channel -> fifo_full_rx_status_s1_agent:cp_channel
	wire          fifo_full_rx_status_s1_burst_adapter_source0_startofpacket;  // fifo_full_rx_status_s1_burst_adapter:source0_startofpacket -> fifo_full_rx_status_s1_agent:cp_startofpacket
	wire          fifo_full_rx_status_s1_burst_adapter_source0_endofpacket;    // fifo_full_rx_status_s1_burst_adapter:source0_endofpacket -> fifo_full_rx_status_s1_agent:cp_endofpacket
	wire          cmd_mux_006_src_valid;                                       // cmd_mux_006:src_valid -> fifo_empty_rx_status_s1_burst_adapter:sink0_valid
	wire  [128:0] cmd_mux_006_src_data;                                        // cmd_mux_006:src_data -> fifo_empty_rx_status_s1_burst_adapter:sink0_data
	wire          cmd_mux_006_src_ready;                                       // fifo_empty_rx_status_s1_burst_adapter:sink0_ready -> cmd_mux_006:src_ready
	wire   [21:0] cmd_mux_006_src_channel;                                     // cmd_mux_006:src_channel -> fifo_empty_rx_status_s1_burst_adapter:sink0_channel
	wire          cmd_mux_006_src_startofpacket;                               // cmd_mux_006:src_startofpacket -> fifo_empty_rx_status_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_006_src_endofpacket;                                 // cmd_mux_006:src_endofpacket -> fifo_empty_rx_status_s1_burst_adapter:sink0_endofpacket
	wire          fifo_empty_rx_status_s1_burst_adapter_source0_valid;         // fifo_empty_rx_status_s1_burst_adapter:source0_valid -> fifo_empty_rx_status_s1_agent:cp_valid
	wire  [128:0] fifo_empty_rx_status_s1_burst_adapter_source0_data;          // fifo_empty_rx_status_s1_burst_adapter:source0_data -> fifo_empty_rx_status_s1_agent:cp_data
	wire          fifo_empty_rx_status_s1_burst_adapter_source0_ready;         // fifo_empty_rx_status_s1_agent:cp_ready -> fifo_empty_rx_status_s1_burst_adapter:source0_ready
	wire   [21:0] fifo_empty_rx_status_s1_burst_adapter_source0_channel;       // fifo_empty_rx_status_s1_burst_adapter:source0_channel -> fifo_empty_rx_status_s1_agent:cp_channel
	wire          fifo_empty_rx_status_s1_burst_adapter_source0_startofpacket; // fifo_empty_rx_status_s1_burst_adapter:source0_startofpacket -> fifo_empty_rx_status_s1_agent:cp_startofpacket
	wire          fifo_empty_rx_status_s1_burst_adapter_source0_endofpacket;   // fifo_empty_rx_status_s1_burst_adapter:source0_endofpacket -> fifo_empty_rx_status_s1_agent:cp_endofpacket
	wire          cmd_mux_007_src_valid;                                       // cmd_mux_007:src_valid -> link_start_s1_burst_adapter:sink0_valid
	wire  [128:0] cmd_mux_007_src_data;                                        // cmd_mux_007:src_data -> link_start_s1_burst_adapter:sink0_data
	wire          cmd_mux_007_src_ready;                                       // link_start_s1_burst_adapter:sink0_ready -> cmd_mux_007:src_ready
	wire   [21:0] cmd_mux_007_src_channel;                                     // cmd_mux_007:src_channel -> link_start_s1_burst_adapter:sink0_channel
	wire          cmd_mux_007_src_startofpacket;                               // cmd_mux_007:src_startofpacket -> link_start_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_007_src_endofpacket;                                 // cmd_mux_007:src_endofpacket -> link_start_s1_burst_adapter:sink0_endofpacket
	wire          link_start_s1_burst_adapter_source0_valid;                   // link_start_s1_burst_adapter:source0_valid -> link_start_s1_agent:cp_valid
	wire  [128:0] link_start_s1_burst_adapter_source0_data;                    // link_start_s1_burst_adapter:source0_data -> link_start_s1_agent:cp_data
	wire          link_start_s1_burst_adapter_source0_ready;                   // link_start_s1_agent:cp_ready -> link_start_s1_burst_adapter:source0_ready
	wire   [21:0] link_start_s1_burst_adapter_source0_channel;                 // link_start_s1_burst_adapter:source0_channel -> link_start_s1_agent:cp_channel
	wire          link_start_s1_burst_adapter_source0_startofpacket;           // link_start_s1_burst_adapter:source0_startofpacket -> link_start_s1_agent:cp_startofpacket
	wire          link_start_s1_burst_adapter_source0_endofpacket;             // link_start_s1_burst_adapter:source0_endofpacket -> link_start_s1_agent:cp_endofpacket
	wire          cmd_mux_008_src_valid;                                       // cmd_mux_008:src_valid -> auto_start_s1_burst_adapter:sink0_valid
	wire  [128:0] cmd_mux_008_src_data;                                        // cmd_mux_008:src_data -> auto_start_s1_burst_adapter:sink0_data
	wire          cmd_mux_008_src_ready;                                       // auto_start_s1_burst_adapter:sink0_ready -> cmd_mux_008:src_ready
	wire   [21:0] cmd_mux_008_src_channel;                                     // cmd_mux_008:src_channel -> auto_start_s1_burst_adapter:sink0_channel
	wire          cmd_mux_008_src_startofpacket;                               // cmd_mux_008:src_startofpacket -> auto_start_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_008_src_endofpacket;                                 // cmd_mux_008:src_endofpacket -> auto_start_s1_burst_adapter:sink0_endofpacket
	wire          auto_start_s1_burst_adapter_source0_valid;                   // auto_start_s1_burst_adapter:source0_valid -> auto_start_s1_agent:cp_valid
	wire  [128:0] auto_start_s1_burst_adapter_source0_data;                    // auto_start_s1_burst_adapter:source0_data -> auto_start_s1_agent:cp_data
	wire          auto_start_s1_burst_adapter_source0_ready;                   // auto_start_s1_agent:cp_ready -> auto_start_s1_burst_adapter:source0_ready
	wire   [21:0] auto_start_s1_burst_adapter_source0_channel;                 // auto_start_s1_burst_adapter:source0_channel -> auto_start_s1_agent:cp_channel
	wire          auto_start_s1_burst_adapter_source0_startofpacket;           // auto_start_s1_burst_adapter:source0_startofpacket -> auto_start_s1_agent:cp_startofpacket
	wire          auto_start_s1_burst_adapter_source0_endofpacket;             // auto_start_s1_burst_adapter:source0_endofpacket -> auto_start_s1_agent:cp_endofpacket
	wire          cmd_mux_009_src_valid;                                       // cmd_mux_009:src_valid -> link_disable_s1_burst_adapter:sink0_valid
	wire  [128:0] cmd_mux_009_src_data;                                        // cmd_mux_009:src_data -> link_disable_s1_burst_adapter:sink0_data
	wire          cmd_mux_009_src_ready;                                       // link_disable_s1_burst_adapter:sink0_ready -> cmd_mux_009:src_ready
	wire   [21:0] cmd_mux_009_src_channel;                                     // cmd_mux_009:src_channel -> link_disable_s1_burst_adapter:sink0_channel
	wire          cmd_mux_009_src_startofpacket;                               // cmd_mux_009:src_startofpacket -> link_disable_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_009_src_endofpacket;                                 // cmd_mux_009:src_endofpacket -> link_disable_s1_burst_adapter:sink0_endofpacket
	wire          link_disable_s1_burst_adapter_source0_valid;                 // link_disable_s1_burst_adapter:source0_valid -> link_disable_s1_agent:cp_valid
	wire  [128:0] link_disable_s1_burst_adapter_source0_data;                  // link_disable_s1_burst_adapter:source0_data -> link_disable_s1_agent:cp_data
	wire          link_disable_s1_burst_adapter_source0_ready;                 // link_disable_s1_agent:cp_ready -> link_disable_s1_burst_adapter:source0_ready
	wire   [21:0] link_disable_s1_burst_adapter_source0_channel;               // link_disable_s1_burst_adapter:source0_channel -> link_disable_s1_agent:cp_channel
	wire          link_disable_s1_burst_adapter_source0_startofpacket;         // link_disable_s1_burst_adapter:source0_startofpacket -> link_disable_s1_agent:cp_startofpacket
	wire          link_disable_s1_burst_adapter_source0_endofpacket;           // link_disable_s1_burst_adapter:source0_endofpacket -> link_disable_s1_agent:cp_endofpacket
	wire          cmd_mux_010_src_valid;                                       // cmd_mux_010:src_valid -> write_data_fifo_tx_s1_burst_adapter:sink0_valid
	wire  [128:0] cmd_mux_010_src_data;                                        // cmd_mux_010:src_data -> write_data_fifo_tx_s1_burst_adapter:sink0_data
	wire          cmd_mux_010_src_ready;                                       // write_data_fifo_tx_s1_burst_adapter:sink0_ready -> cmd_mux_010:src_ready
	wire   [21:0] cmd_mux_010_src_channel;                                     // cmd_mux_010:src_channel -> write_data_fifo_tx_s1_burst_adapter:sink0_channel
	wire          cmd_mux_010_src_startofpacket;                               // cmd_mux_010:src_startofpacket -> write_data_fifo_tx_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_010_src_endofpacket;                                 // cmd_mux_010:src_endofpacket -> write_data_fifo_tx_s1_burst_adapter:sink0_endofpacket
	wire          write_data_fifo_tx_s1_burst_adapter_source0_valid;           // write_data_fifo_tx_s1_burst_adapter:source0_valid -> write_data_fifo_tx_s1_agent:cp_valid
	wire  [128:0] write_data_fifo_tx_s1_burst_adapter_source0_data;            // write_data_fifo_tx_s1_burst_adapter:source0_data -> write_data_fifo_tx_s1_agent:cp_data
	wire          write_data_fifo_tx_s1_burst_adapter_source0_ready;           // write_data_fifo_tx_s1_agent:cp_ready -> write_data_fifo_tx_s1_burst_adapter:source0_ready
	wire   [21:0] write_data_fifo_tx_s1_burst_adapter_source0_channel;         // write_data_fifo_tx_s1_burst_adapter:source0_channel -> write_data_fifo_tx_s1_agent:cp_channel
	wire          write_data_fifo_tx_s1_burst_adapter_source0_startofpacket;   // write_data_fifo_tx_s1_burst_adapter:source0_startofpacket -> write_data_fifo_tx_s1_agent:cp_startofpacket
	wire          write_data_fifo_tx_s1_burst_adapter_source0_endofpacket;     // write_data_fifo_tx_s1_burst_adapter:source0_endofpacket -> write_data_fifo_tx_s1_agent:cp_endofpacket
	wire          cmd_mux_011_src_valid;                                       // cmd_mux_011:src_valid -> write_en_tx_s1_burst_adapter:sink0_valid
	wire  [128:0] cmd_mux_011_src_data;                                        // cmd_mux_011:src_data -> write_en_tx_s1_burst_adapter:sink0_data
	wire          cmd_mux_011_src_ready;                                       // write_en_tx_s1_burst_adapter:sink0_ready -> cmd_mux_011:src_ready
	wire   [21:0] cmd_mux_011_src_channel;                                     // cmd_mux_011:src_channel -> write_en_tx_s1_burst_adapter:sink0_channel
	wire          cmd_mux_011_src_startofpacket;                               // cmd_mux_011:src_startofpacket -> write_en_tx_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_011_src_endofpacket;                                 // cmd_mux_011:src_endofpacket -> write_en_tx_s1_burst_adapter:sink0_endofpacket
	wire          write_en_tx_s1_burst_adapter_source0_valid;                  // write_en_tx_s1_burst_adapter:source0_valid -> write_en_tx_s1_agent:cp_valid
	wire  [128:0] write_en_tx_s1_burst_adapter_source0_data;                   // write_en_tx_s1_burst_adapter:source0_data -> write_en_tx_s1_agent:cp_data
	wire          write_en_tx_s1_burst_adapter_source0_ready;                  // write_en_tx_s1_agent:cp_ready -> write_en_tx_s1_burst_adapter:source0_ready
	wire   [21:0] write_en_tx_s1_burst_adapter_source0_channel;                // write_en_tx_s1_burst_adapter:source0_channel -> write_en_tx_s1_agent:cp_channel
	wire          write_en_tx_s1_burst_adapter_source0_startofpacket;          // write_en_tx_s1_burst_adapter:source0_startofpacket -> write_en_tx_s1_agent:cp_startofpacket
	wire          write_en_tx_s1_burst_adapter_source0_endofpacket;            // write_en_tx_s1_burst_adapter:source0_endofpacket -> write_en_tx_s1_agent:cp_endofpacket
	wire          cmd_mux_012_src_valid;                                       // cmd_mux_012:src_valid -> fifo_full_tx_status_s1_burst_adapter:sink0_valid
	wire  [128:0] cmd_mux_012_src_data;                                        // cmd_mux_012:src_data -> fifo_full_tx_status_s1_burst_adapter:sink0_data
	wire          cmd_mux_012_src_ready;                                       // fifo_full_tx_status_s1_burst_adapter:sink0_ready -> cmd_mux_012:src_ready
	wire   [21:0] cmd_mux_012_src_channel;                                     // cmd_mux_012:src_channel -> fifo_full_tx_status_s1_burst_adapter:sink0_channel
	wire          cmd_mux_012_src_startofpacket;                               // cmd_mux_012:src_startofpacket -> fifo_full_tx_status_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_012_src_endofpacket;                                 // cmd_mux_012:src_endofpacket -> fifo_full_tx_status_s1_burst_adapter:sink0_endofpacket
	wire          fifo_full_tx_status_s1_burst_adapter_source0_valid;          // fifo_full_tx_status_s1_burst_adapter:source0_valid -> fifo_full_tx_status_s1_agent:cp_valid
	wire  [128:0] fifo_full_tx_status_s1_burst_adapter_source0_data;           // fifo_full_tx_status_s1_burst_adapter:source0_data -> fifo_full_tx_status_s1_agent:cp_data
	wire          fifo_full_tx_status_s1_burst_adapter_source0_ready;          // fifo_full_tx_status_s1_agent:cp_ready -> fifo_full_tx_status_s1_burst_adapter:source0_ready
	wire   [21:0] fifo_full_tx_status_s1_burst_adapter_source0_channel;        // fifo_full_tx_status_s1_burst_adapter:source0_channel -> fifo_full_tx_status_s1_agent:cp_channel
	wire          fifo_full_tx_status_s1_burst_adapter_source0_startofpacket;  // fifo_full_tx_status_s1_burst_adapter:source0_startofpacket -> fifo_full_tx_status_s1_agent:cp_startofpacket
	wire          fifo_full_tx_status_s1_burst_adapter_source0_endofpacket;    // fifo_full_tx_status_s1_burst_adapter:source0_endofpacket -> fifo_full_tx_status_s1_agent:cp_endofpacket
	wire          cmd_mux_013_src_valid;                                       // cmd_mux_013:src_valid -> fifo_empty_tx_status_s1_burst_adapter:sink0_valid
	wire  [128:0] cmd_mux_013_src_data;                                        // cmd_mux_013:src_data -> fifo_empty_tx_status_s1_burst_adapter:sink0_data
	wire          cmd_mux_013_src_ready;                                       // fifo_empty_tx_status_s1_burst_adapter:sink0_ready -> cmd_mux_013:src_ready
	wire   [21:0] cmd_mux_013_src_channel;                                     // cmd_mux_013:src_channel -> fifo_empty_tx_status_s1_burst_adapter:sink0_channel
	wire          cmd_mux_013_src_startofpacket;                               // cmd_mux_013:src_startofpacket -> fifo_empty_tx_status_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_013_src_endofpacket;                                 // cmd_mux_013:src_endofpacket -> fifo_empty_tx_status_s1_burst_adapter:sink0_endofpacket
	wire          fifo_empty_tx_status_s1_burst_adapter_source0_valid;         // fifo_empty_tx_status_s1_burst_adapter:source0_valid -> fifo_empty_tx_status_s1_agent:cp_valid
	wire  [128:0] fifo_empty_tx_status_s1_burst_adapter_source0_data;          // fifo_empty_tx_status_s1_burst_adapter:source0_data -> fifo_empty_tx_status_s1_agent:cp_data
	wire          fifo_empty_tx_status_s1_burst_adapter_source0_ready;         // fifo_empty_tx_status_s1_agent:cp_ready -> fifo_empty_tx_status_s1_burst_adapter:source0_ready
	wire   [21:0] fifo_empty_tx_status_s1_burst_adapter_source0_channel;       // fifo_empty_tx_status_s1_burst_adapter:source0_channel -> fifo_empty_tx_status_s1_agent:cp_channel
	wire          fifo_empty_tx_status_s1_burst_adapter_source0_startofpacket; // fifo_empty_tx_status_s1_burst_adapter:source0_startofpacket -> fifo_empty_tx_status_s1_agent:cp_startofpacket
	wire          fifo_empty_tx_status_s1_burst_adapter_source0_endofpacket;   // fifo_empty_tx_status_s1_burst_adapter:source0_endofpacket -> fifo_empty_tx_status_s1_agent:cp_endofpacket
	wire          cmd_mux_014_src_valid;                                       // cmd_mux_014:src_valid -> timecode_tx_data_s1_burst_adapter:sink0_valid
	wire  [128:0] cmd_mux_014_src_data;                                        // cmd_mux_014:src_data -> timecode_tx_data_s1_burst_adapter:sink0_data
	wire          cmd_mux_014_src_ready;                                       // timecode_tx_data_s1_burst_adapter:sink0_ready -> cmd_mux_014:src_ready
	wire   [21:0] cmd_mux_014_src_channel;                                     // cmd_mux_014:src_channel -> timecode_tx_data_s1_burst_adapter:sink0_channel
	wire          cmd_mux_014_src_startofpacket;                               // cmd_mux_014:src_startofpacket -> timecode_tx_data_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_014_src_endofpacket;                                 // cmd_mux_014:src_endofpacket -> timecode_tx_data_s1_burst_adapter:sink0_endofpacket
	wire          timecode_tx_data_s1_burst_adapter_source0_valid;             // timecode_tx_data_s1_burst_adapter:source0_valid -> timecode_tx_data_s1_agent:cp_valid
	wire  [128:0] timecode_tx_data_s1_burst_adapter_source0_data;              // timecode_tx_data_s1_burst_adapter:source0_data -> timecode_tx_data_s1_agent:cp_data
	wire          timecode_tx_data_s1_burst_adapter_source0_ready;             // timecode_tx_data_s1_agent:cp_ready -> timecode_tx_data_s1_burst_adapter:source0_ready
	wire   [21:0] timecode_tx_data_s1_burst_adapter_source0_channel;           // timecode_tx_data_s1_burst_adapter:source0_channel -> timecode_tx_data_s1_agent:cp_channel
	wire          timecode_tx_data_s1_burst_adapter_source0_startofpacket;     // timecode_tx_data_s1_burst_adapter:source0_startofpacket -> timecode_tx_data_s1_agent:cp_startofpacket
	wire          timecode_tx_data_s1_burst_adapter_source0_endofpacket;       // timecode_tx_data_s1_burst_adapter:source0_endofpacket -> timecode_tx_data_s1_agent:cp_endofpacket
	wire          cmd_mux_015_src_valid;                                       // cmd_mux_015:src_valid -> timecode_tx_enable_s1_burst_adapter:sink0_valid
	wire  [128:0] cmd_mux_015_src_data;                                        // cmd_mux_015:src_data -> timecode_tx_enable_s1_burst_adapter:sink0_data
	wire          cmd_mux_015_src_ready;                                       // timecode_tx_enable_s1_burst_adapter:sink0_ready -> cmd_mux_015:src_ready
	wire   [21:0] cmd_mux_015_src_channel;                                     // cmd_mux_015:src_channel -> timecode_tx_enable_s1_burst_adapter:sink0_channel
	wire          cmd_mux_015_src_startofpacket;                               // cmd_mux_015:src_startofpacket -> timecode_tx_enable_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_015_src_endofpacket;                                 // cmd_mux_015:src_endofpacket -> timecode_tx_enable_s1_burst_adapter:sink0_endofpacket
	wire          timecode_tx_enable_s1_burst_adapter_source0_valid;           // timecode_tx_enable_s1_burst_adapter:source0_valid -> timecode_tx_enable_s1_agent:cp_valid
	wire  [128:0] timecode_tx_enable_s1_burst_adapter_source0_data;            // timecode_tx_enable_s1_burst_adapter:source0_data -> timecode_tx_enable_s1_agent:cp_data
	wire          timecode_tx_enable_s1_burst_adapter_source0_ready;           // timecode_tx_enable_s1_agent:cp_ready -> timecode_tx_enable_s1_burst_adapter:source0_ready
	wire   [21:0] timecode_tx_enable_s1_burst_adapter_source0_channel;         // timecode_tx_enable_s1_burst_adapter:source0_channel -> timecode_tx_enable_s1_agent:cp_channel
	wire          timecode_tx_enable_s1_burst_adapter_source0_startofpacket;   // timecode_tx_enable_s1_burst_adapter:source0_startofpacket -> timecode_tx_enable_s1_agent:cp_startofpacket
	wire          timecode_tx_enable_s1_burst_adapter_source0_endofpacket;     // timecode_tx_enable_s1_burst_adapter:source0_endofpacket -> timecode_tx_enable_s1_agent:cp_endofpacket
	wire          cmd_mux_016_src_valid;                                       // cmd_mux_016:src_valid -> timecode_tx_ready_s1_burst_adapter:sink0_valid
	wire  [128:0] cmd_mux_016_src_data;                                        // cmd_mux_016:src_data -> timecode_tx_ready_s1_burst_adapter:sink0_data
	wire          cmd_mux_016_src_ready;                                       // timecode_tx_ready_s1_burst_adapter:sink0_ready -> cmd_mux_016:src_ready
	wire   [21:0] cmd_mux_016_src_channel;                                     // cmd_mux_016:src_channel -> timecode_tx_ready_s1_burst_adapter:sink0_channel
	wire          cmd_mux_016_src_startofpacket;                               // cmd_mux_016:src_startofpacket -> timecode_tx_ready_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_016_src_endofpacket;                                 // cmd_mux_016:src_endofpacket -> timecode_tx_ready_s1_burst_adapter:sink0_endofpacket
	wire          timecode_tx_ready_s1_burst_adapter_source0_valid;            // timecode_tx_ready_s1_burst_adapter:source0_valid -> timecode_tx_ready_s1_agent:cp_valid
	wire  [128:0] timecode_tx_ready_s1_burst_adapter_source0_data;             // timecode_tx_ready_s1_burst_adapter:source0_data -> timecode_tx_ready_s1_agent:cp_data
	wire          timecode_tx_ready_s1_burst_adapter_source0_ready;            // timecode_tx_ready_s1_agent:cp_ready -> timecode_tx_ready_s1_burst_adapter:source0_ready
	wire   [21:0] timecode_tx_ready_s1_burst_adapter_source0_channel;          // timecode_tx_ready_s1_burst_adapter:source0_channel -> timecode_tx_ready_s1_agent:cp_channel
	wire          timecode_tx_ready_s1_burst_adapter_source0_startofpacket;    // timecode_tx_ready_s1_burst_adapter:source0_startofpacket -> timecode_tx_ready_s1_agent:cp_startofpacket
	wire          timecode_tx_ready_s1_burst_adapter_source0_endofpacket;      // timecode_tx_ready_s1_burst_adapter:source0_endofpacket -> timecode_tx_ready_s1_agent:cp_endofpacket
	wire          cmd_mux_017_src_valid;                                       // cmd_mux_017:src_valid -> data_info_s1_burst_adapter:sink0_valid
	wire  [128:0] cmd_mux_017_src_data;                                        // cmd_mux_017:src_data -> data_info_s1_burst_adapter:sink0_data
	wire          cmd_mux_017_src_ready;                                       // data_info_s1_burst_adapter:sink0_ready -> cmd_mux_017:src_ready
	wire   [21:0] cmd_mux_017_src_channel;                                     // cmd_mux_017:src_channel -> data_info_s1_burst_adapter:sink0_channel
	wire          cmd_mux_017_src_startofpacket;                               // cmd_mux_017:src_startofpacket -> data_info_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_017_src_endofpacket;                                 // cmd_mux_017:src_endofpacket -> data_info_s1_burst_adapter:sink0_endofpacket
	wire          data_info_s1_burst_adapter_source0_valid;                    // data_info_s1_burst_adapter:source0_valid -> data_info_s1_agent:cp_valid
	wire  [128:0] data_info_s1_burst_adapter_source0_data;                     // data_info_s1_burst_adapter:source0_data -> data_info_s1_agent:cp_data
	wire          data_info_s1_burst_adapter_source0_ready;                    // data_info_s1_agent:cp_ready -> data_info_s1_burst_adapter:source0_ready
	wire   [21:0] data_info_s1_burst_adapter_source0_channel;                  // data_info_s1_burst_adapter:source0_channel -> data_info_s1_agent:cp_channel
	wire          data_info_s1_burst_adapter_source0_startofpacket;            // data_info_s1_burst_adapter:source0_startofpacket -> data_info_s1_agent:cp_startofpacket
	wire          data_info_s1_burst_adapter_source0_endofpacket;              // data_info_s1_burst_adapter:source0_endofpacket -> data_info_s1_agent:cp_endofpacket
	wire          cmd_mux_018_src_valid;                                       // cmd_mux_018:src_valid -> clock_sel_s1_burst_adapter:sink0_valid
	wire  [128:0] cmd_mux_018_src_data;                                        // cmd_mux_018:src_data -> clock_sel_s1_burst_adapter:sink0_data
	wire          cmd_mux_018_src_ready;                                       // clock_sel_s1_burst_adapter:sink0_ready -> cmd_mux_018:src_ready
	wire   [21:0] cmd_mux_018_src_channel;                                     // cmd_mux_018:src_channel -> clock_sel_s1_burst_adapter:sink0_channel
	wire          cmd_mux_018_src_startofpacket;                               // cmd_mux_018:src_startofpacket -> clock_sel_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_018_src_endofpacket;                                 // cmd_mux_018:src_endofpacket -> clock_sel_s1_burst_adapter:sink0_endofpacket
	wire          clock_sel_s1_burst_adapter_source0_valid;                    // clock_sel_s1_burst_adapter:source0_valid -> clock_sel_s1_agent:cp_valid
	wire  [128:0] clock_sel_s1_burst_adapter_source0_data;                     // clock_sel_s1_burst_adapter:source0_data -> clock_sel_s1_agent:cp_data
	wire          clock_sel_s1_burst_adapter_source0_ready;                    // clock_sel_s1_agent:cp_ready -> clock_sel_s1_burst_adapter:source0_ready
	wire   [21:0] clock_sel_s1_burst_adapter_source0_channel;                  // clock_sel_s1_burst_adapter:source0_channel -> clock_sel_s1_agent:cp_channel
	wire          clock_sel_s1_burst_adapter_source0_startofpacket;            // clock_sel_s1_burst_adapter:source0_startofpacket -> clock_sel_s1_agent:cp_startofpacket
	wire          clock_sel_s1_burst_adapter_source0_endofpacket;              // clock_sel_s1_burst_adapter:source0_endofpacket -> clock_sel_s1_agent:cp_endofpacket
	wire          cmd_mux_019_src_valid;                                       // cmd_mux_019:src_valid -> fsm_info_s1_burst_adapter:sink0_valid
	wire  [128:0] cmd_mux_019_src_data;                                        // cmd_mux_019:src_data -> fsm_info_s1_burst_adapter:sink0_data
	wire          cmd_mux_019_src_ready;                                       // fsm_info_s1_burst_adapter:sink0_ready -> cmd_mux_019:src_ready
	wire   [21:0] cmd_mux_019_src_channel;                                     // cmd_mux_019:src_channel -> fsm_info_s1_burst_adapter:sink0_channel
	wire          cmd_mux_019_src_startofpacket;                               // cmd_mux_019:src_startofpacket -> fsm_info_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_019_src_endofpacket;                                 // cmd_mux_019:src_endofpacket -> fsm_info_s1_burst_adapter:sink0_endofpacket
	wire          fsm_info_s1_burst_adapter_source0_valid;                     // fsm_info_s1_burst_adapter:source0_valid -> fsm_info_s1_agent:cp_valid
	wire  [128:0] fsm_info_s1_burst_adapter_source0_data;                      // fsm_info_s1_burst_adapter:source0_data -> fsm_info_s1_agent:cp_data
	wire          fsm_info_s1_burst_adapter_source0_ready;                     // fsm_info_s1_agent:cp_ready -> fsm_info_s1_burst_adapter:source0_ready
	wire   [21:0] fsm_info_s1_burst_adapter_source0_channel;                   // fsm_info_s1_burst_adapter:source0_channel -> fsm_info_s1_agent:cp_channel
	wire          fsm_info_s1_burst_adapter_source0_startofpacket;             // fsm_info_s1_burst_adapter:source0_startofpacket -> fsm_info_s1_agent:cp_startofpacket
	wire          fsm_info_s1_burst_adapter_source0_endofpacket;               // fsm_info_s1_burst_adapter:source0_endofpacket -> fsm_info_s1_agent:cp_endofpacket
	wire          cmd_mux_020_src_valid;                                       // cmd_mux_020:src_valid -> counter_tx_fifo_s1_burst_adapter:sink0_valid
	wire  [128:0] cmd_mux_020_src_data;                                        // cmd_mux_020:src_data -> counter_tx_fifo_s1_burst_adapter:sink0_data
	wire          cmd_mux_020_src_ready;                                       // counter_tx_fifo_s1_burst_adapter:sink0_ready -> cmd_mux_020:src_ready
	wire   [21:0] cmd_mux_020_src_channel;                                     // cmd_mux_020:src_channel -> counter_tx_fifo_s1_burst_adapter:sink0_channel
	wire          cmd_mux_020_src_startofpacket;                               // cmd_mux_020:src_startofpacket -> counter_tx_fifo_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_020_src_endofpacket;                                 // cmd_mux_020:src_endofpacket -> counter_tx_fifo_s1_burst_adapter:sink0_endofpacket
	wire          counter_tx_fifo_s1_burst_adapter_source0_valid;              // counter_tx_fifo_s1_burst_adapter:source0_valid -> counter_tx_fifo_s1_agent:cp_valid
	wire  [128:0] counter_tx_fifo_s1_burst_adapter_source0_data;               // counter_tx_fifo_s1_burst_adapter:source0_data -> counter_tx_fifo_s1_agent:cp_data
	wire          counter_tx_fifo_s1_burst_adapter_source0_ready;              // counter_tx_fifo_s1_agent:cp_ready -> counter_tx_fifo_s1_burst_adapter:source0_ready
	wire   [21:0] counter_tx_fifo_s1_burst_adapter_source0_channel;            // counter_tx_fifo_s1_burst_adapter:source0_channel -> counter_tx_fifo_s1_agent:cp_channel
	wire          counter_tx_fifo_s1_burst_adapter_source0_startofpacket;      // counter_tx_fifo_s1_burst_adapter:source0_startofpacket -> counter_tx_fifo_s1_agent:cp_startofpacket
	wire          counter_tx_fifo_s1_burst_adapter_source0_endofpacket;        // counter_tx_fifo_s1_burst_adapter:source0_endofpacket -> counter_tx_fifo_s1_agent:cp_endofpacket
	wire          cmd_mux_021_src_valid;                                       // cmd_mux_021:src_valid -> counter_rx_fifo_s1_burst_adapter:sink0_valid
	wire  [128:0] cmd_mux_021_src_data;                                        // cmd_mux_021:src_data -> counter_rx_fifo_s1_burst_adapter:sink0_data
	wire          cmd_mux_021_src_ready;                                       // counter_rx_fifo_s1_burst_adapter:sink0_ready -> cmd_mux_021:src_ready
	wire   [21:0] cmd_mux_021_src_channel;                                     // cmd_mux_021:src_channel -> counter_rx_fifo_s1_burst_adapter:sink0_channel
	wire          cmd_mux_021_src_startofpacket;                               // cmd_mux_021:src_startofpacket -> counter_rx_fifo_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_021_src_endofpacket;                                 // cmd_mux_021:src_endofpacket -> counter_rx_fifo_s1_burst_adapter:sink0_endofpacket
	wire          counter_rx_fifo_s1_burst_adapter_source0_valid;              // counter_rx_fifo_s1_burst_adapter:source0_valid -> counter_rx_fifo_s1_agent:cp_valid
	wire  [128:0] counter_rx_fifo_s1_burst_adapter_source0_data;               // counter_rx_fifo_s1_burst_adapter:source0_data -> counter_rx_fifo_s1_agent:cp_data
	wire          counter_rx_fifo_s1_burst_adapter_source0_ready;              // counter_rx_fifo_s1_agent:cp_ready -> counter_rx_fifo_s1_burst_adapter:source0_ready
	wire   [21:0] counter_rx_fifo_s1_burst_adapter_source0_channel;            // counter_rx_fifo_s1_burst_adapter:source0_channel -> counter_rx_fifo_s1_agent:cp_channel
	wire          counter_rx_fifo_s1_burst_adapter_source0_startofpacket;      // counter_rx_fifo_s1_burst_adapter:source0_startofpacket -> counter_rx_fifo_s1_agent:cp_startofpacket
	wire          counter_rx_fifo_s1_burst_adapter_source0_endofpacket;        // counter_rx_fifo_s1_burst_adapter:source0_endofpacket -> counter_rx_fifo_s1_agent:cp_endofpacket
	wire          cmd_demux_src0_valid;                                        // cmd_demux:src0_valid -> cmd_mux:sink0_valid
	wire  [128:0] cmd_demux_src0_data;                                         // cmd_demux:src0_data -> cmd_mux:sink0_data
	wire          cmd_demux_src0_ready;                                        // cmd_mux:sink0_ready -> cmd_demux:src0_ready
	wire   [21:0] cmd_demux_src0_channel;                                      // cmd_demux:src0_channel -> cmd_mux:sink0_channel
	wire          cmd_demux_src0_startofpacket;                                // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
	wire          cmd_demux_src0_endofpacket;                                  // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
	wire          cmd_demux_src1_valid;                                        // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
	wire  [128:0] cmd_demux_src1_data;                                         // cmd_demux:src1_data -> cmd_mux_001:sink0_data
	wire          cmd_demux_src1_ready;                                        // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
	wire   [21:0] cmd_demux_src1_channel;                                      // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
	wire          cmd_demux_src1_startofpacket;                                // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
	wire          cmd_demux_src1_endofpacket;                                  // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
	wire          cmd_demux_src2_valid;                                        // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
	wire  [128:0] cmd_demux_src2_data;                                         // cmd_demux:src2_data -> cmd_mux_002:sink0_data
	wire          cmd_demux_src2_ready;                                        // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
	wire   [21:0] cmd_demux_src2_channel;                                      // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
	wire          cmd_demux_src2_startofpacket;                                // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
	wire          cmd_demux_src2_endofpacket;                                  // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
	wire          cmd_demux_src3_valid;                                        // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
	wire  [128:0] cmd_demux_src3_data;                                         // cmd_demux:src3_data -> cmd_mux_003:sink0_data
	wire          cmd_demux_src3_ready;                                        // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
	wire   [21:0] cmd_demux_src3_channel;                                      // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
	wire          cmd_demux_src3_startofpacket;                                // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
	wire          cmd_demux_src3_endofpacket;                                  // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
	wire          cmd_demux_src4_valid;                                        // cmd_demux:src4_valid -> cmd_mux_004:sink0_valid
	wire  [128:0] cmd_demux_src4_data;                                         // cmd_demux:src4_data -> cmd_mux_004:sink0_data
	wire          cmd_demux_src4_ready;                                        // cmd_mux_004:sink0_ready -> cmd_demux:src4_ready
	wire   [21:0] cmd_demux_src4_channel;                                      // cmd_demux:src4_channel -> cmd_mux_004:sink0_channel
	wire          cmd_demux_src4_startofpacket;                                // cmd_demux:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
	wire          cmd_demux_src4_endofpacket;                                  // cmd_demux:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
	wire          cmd_demux_src5_valid;                                        // cmd_demux:src5_valid -> cmd_mux_005:sink0_valid
	wire  [128:0] cmd_demux_src5_data;                                         // cmd_demux:src5_data -> cmd_mux_005:sink0_data
	wire          cmd_demux_src5_ready;                                        // cmd_mux_005:sink0_ready -> cmd_demux:src5_ready
	wire   [21:0] cmd_demux_src5_channel;                                      // cmd_demux:src5_channel -> cmd_mux_005:sink0_channel
	wire          cmd_demux_src5_startofpacket;                                // cmd_demux:src5_startofpacket -> cmd_mux_005:sink0_startofpacket
	wire          cmd_demux_src5_endofpacket;                                  // cmd_demux:src5_endofpacket -> cmd_mux_005:sink0_endofpacket
	wire          cmd_demux_src6_valid;                                        // cmd_demux:src6_valid -> cmd_mux_006:sink0_valid
	wire  [128:0] cmd_demux_src6_data;                                         // cmd_demux:src6_data -> cmd_mux_006:sink0_data
	wire          cmd_demux_src6_ready;                                        // cmd_mux_006:sink0_ready -> cmd_demux:src6_ready
	wire   [21:0] cmd_demux_src6_channel;                                      // cmd_demux:src6_channel -> cmd_mux_006:sink0_channel
	wire          cmd_demux_src6_startofpacket;                                // cmd_demux:src6_startofpacket -> cmd_mux_006:sink0_startofpacket
	wire          cmd_demux_src6_endofpacket;                                  // cmd_demux:src6_endofpacket -> cmd_mux_006:sink0_endofpacket
	wire          cmd_demux_src7_valid;                                        // cmd_demux:src7_valid -> cmd_mux_007:sink0_valid
	wire  [128:0] cmd_demux_src7_data;                                         // cmd_demux:src7_data -> cmd_mux_007:sink0_data
	wire          cmd_demux_src7_ready;                                        // cmd_mux_007:sink0_ready -> cmd_demux:src7_ready
	wire   [21:0] cmd_demux_src7_channel;                                      // cmd_demux:src7_channel -> cmd_mux_007:sink0_channel
	wire          cmd_demux_src7_startofpacket;                                // cmd_demux:src7_startofpacket -> cmd_mux_007:sink0_startofpacket
	wire          cmd_demux_src7_endofpacket;                                  // cmd_demux:src7_endofpacket -> cmd_mux_007:sink0_endofpacket
	wire          cmd_demux_src8_valid;                                        // cmd_demux:src8_valid -> cmd_mux_008:sink0_valid
	wire  [128:0] cmd_demux_src8_data;                                         // cmd_demux:src8_data -> cmd_mux_008:sink0_data
	wire          cmd_demux_src8_ready;                                        // cmd_mux_008:sink0_ready -> cmd_demux:src8_ready
	wire   [21:0] cmd_demux_src8_channel;                                      // cmd_demux:src8_channel -> cmd_mux_008:sink0_channel
	wire          cmd_demux_src8_startofpacket;                                // cmd_demux:src8_startofpacket -> cmd_mux_008:sink0_startofpacket
	wire          cmd_demux_src8_endofpacket;                                  // cmd_demux:src8_endofpacket -> cmd_mux_008:sink0_endofpacket
	wire          cmd_demux_src9_valid;                                        // cmd_demux:src9_valid -> cmd_mux_009:sink0_valid
	wire  [128:0] cmd_demux_src9_data;                                         // cmd_demux:src9_data -> cmd_mux_009:sink0_data
	wire          cmd_demux_src9_ready;                                        // cmd_mux_009:sink0_ready -> cmd_demux:src9_ready
	wire   [21:0] cmd_demux_src9_channel;                                      // cmd_demux:src9_channel -> cmd_mux_009:sink0_channel
	wire          cmd_demux_src9_startofpacket;                                // cmd_demux:src9_startofpacket -> cmd_mux_009:sink0_startofpacket
	wire          cmd_demux_src9_endofpacket;                                  // cmd_demux:src9_endofpacket -> cmd_mux_009:sink0_endofpacket
	wire          cmd_demux_src10_valid;                                       // cmd_demux:src10_valid -> cmd_mux_010:sink0_valid
	wire  [128:0] cmd_demux_src10_data;                                        // cmd_demux:src10_data -> cmd_mux_010:sink0_data
	wire          cmd_demux_src10_ready;                                       // cmd_mux_010:sink0_ready -> cmd_demux:src10_ready
	wire   [21:0] cmd_demux_src10_channel;                                     // cmd_demux:src10_channel -> cmd_mux_010:sink0_channel
	wire          cmd_demux_src10_startofpacket;                               // cmd_demux:src10_startofpacket -> cmd_mux_010:sink0_startofpacket
	wire          cmd_demux_src10_endofpacket;                                 // cmd_demux:src10_endofpacket -> cmd_mux_010:sink0_endofpacket
	wire          cmd_demux_src11_valid;                                       // cmd_demux:src11_valid -> cmd_mux_011:sink0_valid
	wire  [128:0] cmd_demux_src11_data;                                        // cmd_demux:src11_data -> cmd_mux_011:sink0_data
	wire          cmd_demux_src11_ready;                                       // cmd_mux_011:sink0_ready -> cmd_demux:src11_ready
	wire   [21:0] cmd_demux_src11_channel;                                     // cmd_demux:src11_channel -> cmd_mux_011:sink0_channel
	wire          cmd_demux_src11_startofpacket;                               // cmd_demux:src11_startofpacket -> cmd_mux_011:sink0_startofpacket
	wire          cmd_demux_src11_endofpacket;                                 // cmd_demux:src11_endofpacket -> cmd_mux_011:sink0_endofpacket
	wire          cmd_demux_src12_valid;                                       // cmd_demux:src12_valid -> cmd_mux_012:sink0_valid
	wire  [128:0] cmd_demux_src12_data;                                        // cmd_demux:src12_data -> cmd_mux_012:sink0_data
	wire          cmd_demux_src12_ready;                                       // cmd_mux_012:sink0_ready -> cmd_demux:src12_ready
	wire   [21:0] cmd_demux_src12_channel;                                     // cmd_demux:src12_channel -> cmd_mux_012:sink0_channel
	wire          cmd_demux_src12_startofpacket;                               // cmd_demux:src12_startofpacket -> cmd_mux_012:sink0_startofpacket
	wire          cmd_demux_src12_endofpacket;                                 // cmd_demux:src12_endofpacket -> cmd_mux_012:sink0_endofpacket
	wire          cmd_demux_src13_valid;                                       // cmd_demux:src13_valid -> cmd_mux_013:sink0_valid
	wire  [128:0] cmd_demux_src13_data;                                        // cmd_demux:src13_data -> cmd_mux_013:sink0_data
	wire          cmd_demux_src13_ready;                                       // cmd_mux_013:sink0_ready -> cmd_demux:src13_ready
	wire   [21:0] cmd_demux_src13_channel;                                     // cmd_demux:src13_channel -> cmd_mux_013:sink0_channel
	wire          cmd_demux_src13_startofpacket;                               // cmd_demux:src13_startofpacket -> cmd_mux_013:sink0_startofpacket
	wire          cmd_demux_src13_endofpacket;                                 // cmd_demux:src13_endofpacket -> cmd_mux_013:sink0_endofpacket
	wire          cmd_demux_src14_valid;                                       // cmd_demux:src14_valid -> cmd_mux_014:sink0_valid
	wire  [128:0] cmd_demux_src14_data;                                        // cmd_demux:src14_data -> cmd_mux_014:sink0_data
	wire          cmd_demux_src14_ready;                                       // cmd_mux_014:sink0_ready -> cmd_demux:src14_ready
	wire   [21:0] cmd_demux_src14_channel;                                     // cmd_demux:src14_channel -> cmd_mux_014:sink0_channel
	wire          cmd_demux_src14_startofpacket;                               // cmd_demux:src14_startofpacket -> cmd_mux_014:sink0_startofpacket
	wire          cmd_demux_src14_endofpacket;                                 // cmd_demux:src14_endofpacket -> cmd_mux_014:sink0_endofpacket
	wire          cmd_demux_src15_valid;                                       // cmd_demux:src15_valid -> cmd_mux_015:sink0_valid
	wire  [128:0] cmd_demux_src15_data;                                        // cmd_demux:src15_data -> cmd_mux_015:sink0_data
	wire          cmd_demux_src15_ready;                                       // cmd_mux_015:sink0_ready -> cmd_demux:src15_ready
	wire   [21:0] cmd_demux_src15_channel;                                     // cmd_demux:src15_channel -> cmd_mux_015:sink0_channel
	wire          cmd_demux_src15_startofpacket;                               // cmd_demux:src15_startofpacket -> cmd_mux_015:sink0_startofpacket
	wire          cmd_demux_src15_endofpacket;                                 // cmd_demux:src15_endofpacket -> cmd_mux_015:sink0_endofpacket
	wire          cmd_demux_src16_valid;                                       // cmd_demux:src16_valid -> cmd_mux_016:sink0_valid
	wire  [128:0] cmd_demux_src16_data;                                        // cmd_demux:src16_data -> cmd_mux_016:sink0_data
	wire          cmd_demux_src16_ready;                                       // cmd_mux_016:sink0_ready -> cmd_demux:src16_ready
	wire   [21:0] cmd_demux_src16_channel;                                     // cmd_demux:src16_channel -> cmd_mux_016:sink0_channel
	wire          cmd_demux_src16_startofpacket;                               // cmd_demux:src16_startofpacket -> cmd_mux_016:sink0_startofpacket
	wire          cmd_demux_src16_endofpacket;                                 // cmd_demux:src16_endofpacket -> cmd_mux_016:sink0_endofpacket
	wire          cmd_demux_src17_valid;                                       // cmd_demux:src17_valid -> cmd_mux_017:sink0_valid
	wire  [128:0] cmd_demux_src17_data;                                        // cmd_demux:src17_data -> cmd_mux_017:sink0_data
	wire          cmd_demux_src17_ready;                                       // cmd_mux_017:sink0_ready -> cmd_demux:src17_ready
	wire   [21:0] cmd_demux_src17_channel;                                     // cmd_demux:src17_channel -> cmd_mux_017:sink0_channel
	wire          cmd_demux_src17_startofpacket;                               // cmd_demux:src17_startofpacket -> cmd_mux_017:sink0_startofpacket
	wire          cmd_demux_src17_endofpacket;                                 // cmd_demux:src17_endofpacket -> cmd_mux_017:sink0_endofpacket
	wire          cmd_demux_src18_valid;                                       // cmd_demux:src18_valid -> cmd_mux_018:sink0_valid
	wire  [128:0] cmd_demux_src18_data;                                        // cmd_demux:src18_data -> cmd_mux_018:sink0_data
	wire          cmd_demux_src18_ready;                                       // cmd_mux_018:sink0_ready -> cmd_demux:src18_ready
	wire   [21:0] cmd_demux_src18_channel;                                     // cmd_demux:src18_channel -> cmd_mux_018:sink0_channel
	wire          cmd_demux_src18_startofpacket;                               // cmd_demux:src18_startofpacket -> cmd_mux_018:sink0_startofpacket
	wire          cmd_demux_src18_endofpacket;                                 // cmd_demux:src18_endofpacket -> cmd_mux_018:sink0_endofpacket
	wire          cmd_demux_src19_valid;                                       // cmd_demux:src19_valid -> cmd_mux_019:sink0_valid
	wire  [128:0] cmd_demux_src19_data;                                        // cmd_demux:src19_data -> cmd_mux_019:sink0_data
	wire          cmd_demux_src19_ready;                                       // cmd_mux_019:sink0_ready -> cmd_demux:src19_ready
	wire   [21:0] cmd_demux_src19_channel;                                     // cmd_demux:src19_channel -> cmd_mux_019:sink0_channel
	wire          cmd_demux_src19_startofpacket;                               // cmd_demux:src19_startofpacket -> cmd_mux_019:sink0_startofpacket
	wire          cmd_demux_src19_endofpacket;                                 // cmd_demux:src19_endofpacket -> cmd_mux_019:sink0_endofpacket
	wire          cmd_demux_src20_valid;                                       // cmd_demux:src20_valid -> cmd_mux_020:sink0_valid
	wire  [128:0] cmd_demux_src20_data;                                        // cmd_demux:src20_data -> cmd_mux_020:sink0_data
	wire          cmd_demux_src20_ready;                                       // cmd_mux_020:sink0_ready -> cmd_demux:src20_ready
	wire   [21:0] cmd_demux_src20_channel;                                     // cmd_demux:src20_channel -> cmd_mux_020:sink0_channel
	wire          cmd_demux_src20_startofpacket;                               // cmd_demux:src20_startofpacket -> cmd_mux_020:sink0_startofpacket
	wire          cmd_demux_src20_endofpacket;                                 // cmd_demux:src20_endofpacket -> cmd_mux_020:sink0_endofpacket
	wire          cmd_demux_src21_valid;                                       // cmd_demux:src21_valid -> cmd_mux_021:sink0_valid
	wire  [128:0] cmd_demux_src21_data;                                        // cmd_demux:src21_data -> cmd_mux_021:sink0_data
	wire          cmd_demux_src21_ready;                                       // cmd_mux_021:sink0_ready -> cmd_demux:src21_ready
	wire   [21:0] cmd_demux_src21_channel;                                     // cmd_demux:src21_channel -> cmd_mux_021:sink0_channel
	wire          cmd_demux_src21_startofpacket;                               // cmd_demux:src21_startofpacket -> cmd_mux_021:sink0_startofpacket
	wire          cmd_demux_src21_endofpacket;                                 // cmd_demux:src21_endofpacket -> cmd_mux_021:sink0_endofpacket
	wire          cmd_demux_001_src0_valid;                                    // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
	wire  [128:0] cmd_demux_001_src0_data;                                     // cmd_demux_001:src0_data -> cmd_mux:sink1_data
	wire          cmd_demux_001_src0_ready;                                    // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
	wire   [21:0] cmd_demux_001_src0_channel;                                  // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
	wire          cmd_demux_001_src0_startofpacket;                            // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
	wire          cmd_demux_001_src0_endofpacket;                              // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
	wire          cmd_demux_001_src1_valid;                                    // cmd_demux_001:src1_valid -> cmd_mux_001:sink1_valid
	wire  [128:0] cmd_demux_001_src1_data;                                     // cmd_demux_001:src1_data -> cmd_mux_001:sink1_data
	wire          cmd_demux_001_src1_ready;                                    // cmd_mux_001:sink1_ready -> cmd_demux_001:src1_ready
	wire   [21:0] cmd_demux_001_src1_channel;                                  // cmd_demux_001:src1_channel -> cmd_mux_001:sink1_channel
	wire          cmd_demux_001_src1_startofpacket;                            // cmd_demux_001:src1_startofpacket -> cmd_mux_001:sink1_startofpacket
	wire          cmd_demux_001_src1_endofpacket;                              // cmd_demux_001:src1_endofpacket -> cmd_mux_001:sink1_endofpacket
	wire          cmd_demux_001_src2_valid;                                    // cmd_demux_001:src2_valid -> cmd_mux_002:sink1_valid
	wire  [128:0] cmd_demux_001_src2_data;                                     // cmd_demux_001:src2_data -> cmd_mux_002:sink1_data
	wire          cmd_demux_001_src2_ready;                                    // cmd_mux_002:sink1_ready -> cmd_demux_001:src2_ready
	wire   [21:0] cmd_demux_001_src2_channel;                                  // cmd_demux_001:src2_channel -> cmd_mux_002:sink1_channel
	wire          cmd_demux_001_src2_startofpacket;                            // cmd_demux_001:src2_startofpacket -> cmd_mux_002:sink1_startofpacket
	wire          cmd_demux_001_src2_endofpacket;                              // cmd_demux_001:src2_endofpacket -> cmd_mux_002:sink1_endofpacket
	wire          cmd_demux_001_src3_valid;                                    // cmd_demux_001:src3_valid -> cmd_mux_003:sink1_valid
	wire  [128:0] cmd_demux_001_src3_data;                                     // cmd_demux_001:src3_data -> cmd_mux_003:sink1_data
	wire          cmd_demux_001_src3_ready;                                    // cmd_mux_003:sink1_ready -> cmd_demux_001:src3_ready
	wire   [21:0] cmd_demux_001_src3_channel;                                  // cmd_demux_001:src3_channel -> cmd_mux_003:sink1_channel
	wire          cmd_demux_001_src3_startofpacket;                            // cmd_demux_001:src3_startofpacket -> cmd_mux_003:sink1_startofpacket
	wire          cmd_demux_001_src3_endofpacket;                              // cmd_demux_001:src3_endofpacket -> cmd_mux_003:sink1_endofpacket
	wire          cmd_demux_001_src4_valid;                                    // cmd_demux_001:src4_valid -> cmd_mux_004:sink1_valid
	wire  [128:0] cmd_demux_001_src4_data;                                     // cmd_demux_001:src4_data -> cmd_mux_004:sink1_data
	wire          cmd_demux_001_src4_ready;                                    // cmd_mux_004:sink1_ready -> cmd_demux_001:src4_ready
	wire   [21:0] cmd_demux_001_src4_channel;                                  // cmd_demux_001:src4_channel -> cmd_mux_004:sink1_channel
	wire          cmd_demux_001_src4_startofpacket;                            // cmd_demux_001:src4_startofpacket -> cmd_mux_004:sink1_startofpacket
	wire          cmd_demux_001_src4_endofpacket;                              // cmd_demux_001:src4_endofpacket -> cmd_mux_004:sink1_endofpacket
	wire          cmd_demux_001_src5_valid;                                    // cmd_demux_001:src5_valid -> cmd_mux_005:sink1_valid
	wire  [128:0] cmd_demux_001_src5_data;                                     // cmd_demux_001:src5_data -> cmd_mux_005:sink1_data
	wire          cmd_demux_001_src5_ready;                                    // cmd_mux_005:sink1_ready -> cmd_demux_001:src5_ready
	wire   [21:0] cmd_demux_001_src5_channel;                                  // cmd_demux_001:src5_channel -> cmd_mux_005:sink1_channel
	wire          cmd_demux_001_src5_startofpacket;                            // cmd_demux_001:src5_startofpacket -> cmd_mux_005:sink1_startofpacket
	wire          cmd_demux_001_src5_endofpacket;                              // cmd_demux_001:src5_endofpacket -> cmd_mux_005:sink1_endofpacket
	wire          cmd_demux_001_src6_valid;                                    // cmd_demux_001:src6_valid -> cmd_mux_006:sink1_valid
	wire  [128:0] cmd_demux_001_src6_data;                                     // cmd_demux_001:src6_data -> cmd_mux_006:sink1_data
	wire          cmd_demux_001_src6_ready;                                    // cmd_mux_006:sink1_ready -> cmd_demux_001:src6_ready
	wire   [21:0] cmd_demux_001_src6_channel;                                  // cmd_demux_001:src6_channel -> cmd_mux_006:sink1_channel
	wire          cmd_demux_001_src6_startofpacket;                            // cmd_demux_001:src6_startofpacket -> cmd_mux_006:sink1_startofpacket
	wire          cmd_demux_001_src6_endofpacket;                              // cmd_demux_001:src6_endofpacket -> cmd_mux_006:sink1_endofpacket
	wire          cmd_demux_001_src7_valid;                                    // cmd_demux_001:src7_valid -> cmd_mux_007:sink1_valid
	wire  [128:0] cmd_demux_001_src7_data;                                     // cmd_demux_001:src7_data -> cmd_mux_007:sink1_data
	wire          cmd_demux_001_src7_ready;                                    // cmd_mux_007:sink1_ready -> cmd_demux_001:src7_ready
	wire   [21:0] cmd_demux_001_src7_channel;                                  // cmd_demux_001:src7_channel -> cmd_mux_007:sink1_channel
	wire          cmd_demux_001_src7_startofpacket;                            // cmd_demux_001:src7_startofpacket -> cmd_mux_007:sink1_startofpacket
	wire          cmd_demux_001_src7_endofpacket;                              // cmd_demux_001:src7_endofpacket -> cmd_mux_007:sink1_endofpacket
	wire          cmd_demux_001_src8_valid;                                    // cmd_demux_001:src8_valid -> cmd_mux_008:sink1_valid
	wire  [128:0] cmd_demux_001_src8_data;                                     // cmd_demux_001:src8_data -> cmd_mux_008:sink1_data
	wire          cmd_demux_001_src8_ready;                                    // cmd_mux_008:sink1_ready -> cmd_demux_001:src8_ready
	wire   [21:0] cmd_demux_001_src8_channel;                                  // cmd_demux_001:src8_channel -> cmd_mux_008:sink1_channel
	wire          cmd_demux_001_src8_startofpacket;                            // cmd_demux_001:src8_startofpacket -> cmd_mux_008:sink1_startofpacket
	wire          cmd_demux_001_src8_endofpacket;                              // cmd_demux_001:src8_endofpacket -> cmd_mux_008:sink1_endofpacket
	wire          cmd_demux_001_src9_valid;                                    // cmd_demux_001:src9_valid -> cmd_mux_009:sink1_valid
	wire  [128:0] cmd_demux_001_src9_data;                                     // cmd_demux_001:src9_data -> cmd_mux_009:sink1_data
	wire          cmd_demux_001_src9_ready;                                    // cmd_mux_009:sink1_ready -> cmd_demux_001:src9_ready
	wire   [21:0] cmd_demux_001_src9_channel;                                  // cmd_demux_001:src9_channel -> cmd_mux_009:sink1_channel
	wire          cmd_demux_001_src9_startofpacket;                            // cmd_demux_001:src9_startofpacket -> cmd_mux_009:sink1_startofpacket
	wire          cmd_demux_001_src9_endofpacket;                              // cmd_demux_001:src9_endofpacket -> cmd_mux_009:sink1_endofpacket
	wire          cmd_demux_001_src10_valid;                                   // cmd_demux_001:src10_valid -> cmd_mux_010:sink1_valid
	wire  [128:0] cmd_demux_001_src10_data;                                    // cmd_demux_001:src10_data -> cmd_mux_010:sink1_data
	wire          cmd_demux_001_src10_ready;                                   // cmd_mux_010:sink1_ready -> cmd_demux_001:src10_ready
	wire   [21:0] cmd_demux_001_src10_channel;                                 // cmd_demux_001:src10_channel -> cmd_mux_010:sink1_channel
	wire          cmd_demux_001_src10_startofpacket;                           // cmd_demux_001:src10_startofpacket -> cmd_mux_010:sink1_startofpacket
	wire          cmd_demux_001_src10_endofpacket;                             // cmd_demux_001:src10_endofpacket -> cmd_mux_010:sink1_endofpacket
	wire          cmd_demux_001_src11_valid;                                   // cmd_demux_001:src11_valid -> cmd_mux_011:sink1_valid
	wire  [128:0] cmd_demux_001_src11_data;                                    // cmd_demux_001:src11_data -> cmd_mux_011:sink1_data
	wire          cmd_demux_001_src11_ready;                                   // cmd_mux_011:sink1_ready -> cmd_demux_001:src11_ready
	wire   [21:0] cmd_demux_001_src11_channel;                                 // cmd_demux_001:src11_channel -> cmd_mux_011:sink1_channel
	wire          cmd_demux_001_src11_startofpacket;                           // cmd_demux_001:src11_startofpacket -> cmd_mux_011:sink1_startofpacket
	wire          cmd_demux_001_src11_endofpacket;                             // cmd_demux_001:src11_endofpacket -> cmd_mux_011:sink1_endofpacket
	wire          cmd_demux_001_src12_valid;                                   // cmd_demux_001:src12_valid -> cmd_mux_012:sink1_valid
	wire  [128:0] cmd_demux_001_src12_data;                                    // cmd_demux_001:src12_data -> cmd_mux_012:sink1_data
	wire          cmd_demux_001_src12_ready;                                   // cmd_mux_012:sink1_ready -> cmd_demux_001:src12_ready
	wire   [21:0] cmd_demux_001_src12_channel;                                 // cmd_demux_001:src12_channel -> cmd_mux_012:sink1_channel
	wire          cmd_demux_001_src12_startofpacket;                           // cmd_demux_001:src12_startofpacket -> cmd_mux_012:sink1_startofpacket
	wire          cmd_demux_001_src12_endofpacket;                             // cmd_demux_001:src12_endofpacket -> cmd_mux_012:sink1_endofpacket
	wire          cmd_demux_001_src13_valid;                                   // cmd_demux_001:src13_valid -> cmd_mux_013:sink1_valid
	wire  [128:0] cmd_demux_001_src13_data;                                    // cmd_demux_001:src13_data -> cmd_mux_013:sink1_data
	wire          cmd_demux_001_src13_ready;                                   // cmd_mux_013:sink1_ready -> cmd_demux_001:src13_ready
	wire   [21:0] cmd_demux_001_src13_channel;                                 // cmd_demux_001:src13_channel -> cmd_mux_013:sink1_channel
	wire          cmd_demux_001_src13_startofpacket;                           // cmd_demux_001:src13_startofpacket -> cmd_mux_013:sink1_startofpacket
	wire          cmd_demux_001_src13_endofpacket;                             // cmd_demux_001:src13_endofpacket -> cmd_mux_013:sink1_endofpacket
	wire          cmd_demux_001_src14_valid;                                   // cmd_demux_001:src14_valid -> cmd_mux_014:sink1_valid
	wire  [128:0] cmd_demux_001_src14_data;                                    // cmd_demux_001:src14_data -> cmd_mux_014:sink1_data
	wire          cmd_demux_001_src14_ready;                                   // cmd_mux_014:sink1_ready -> cmd_demux_001:src14_ready
	wire   [21:0] cmd_demux_001_src14_channel;                                 // cmd_demux_001:src14_channel -> cmd_mux_014:sink1_channel
	wire          cmd_demux_001_src14_startofpacket;                           // cmd_demux_001:src14_startofpacket -> cmd_mux_014:sink1_startofpacket
	wire          cmd_demux_001_src14_endofpacket;                             // cmd_demux_001:src14_endofpacket -> cmd_mux_014:sink1_endofpacket
	wire          cmd_demux_001_src15_valid;                                   // cmd_demux_001:src15_valid -> cmd_mux_015:sink1_valid
	wire  [128:0] cmd_demux_001_src15_data;                                    // cmd_demux_001:src15_data -> cmd_mux_015:sink1_data
	wire          cmd_demux_001_src15_ready;                                   // cmd_mux_015:sink1_ready -> cmd_demux_001:src15_ready
	wire   [21:0] cmd_demux_001_src15_channel;                                 // cmd_demux_001:src15_channel -> cmd_mux_015:sink1_channel
	wire          cmd_demux_001_src15_startofpacket;                           // cmd_demux_001:src15_startofpacket -> cmd_mux_015:sink1_startofpacket
	wire          cmd_demux_001_src15_endofpacket;                             // cmd_demux_001:src15_endofpacket -> cmd_mux_015:sink1_endofpacket
	wire          cmd_demux_001_src16_valid;                                   // cmd_demux_001:src16_valid -> cmd_mux_016:sink1_valid
	wire  [128:0] cmd_demux_001_src16_data;                                    // cmd_demux_001:src16_data -> cmd_mux_016:sink1_data
	wire          cmd_demux_001_src16_ready;                                   // cmd_mux_016:sink1_ready -> cmd_demux_001:src16_ready
	wire   [21:0] cmd_demux_001_src16_channel;                                 // cmd_demux_001:src16_channel -> cmd_mux_016:sink1_channel
	wire          cmd_demux_001_src16_startofpacket;                           // cmd_demux_001:src16_startofpacket -> cmd_mux_016:sink1_startofpacket
	wire          cmd_demux_001_src16_endofpacket;                             // cmd_demux_001:src16_endofpacket -> cmd_mux_016:sink1_endofpacket
	wire          cmd_demux_001_src17_valid;                                   // cmd_demux_001:src17_valid -> cmd_mux_017:sink1_valid
	wire  [128:0] cmd_demux_001_src17_data;                                    // cmd_demux_001:src17_data -> cmd_mux_017:sink1_data
	wire          cmd_demux_001_src17_ready;                                   // cmd_mux_017:sink1_ready -> cmd_demux_001:src17_ready
	wire   [21:0] cmd_demux_001_src17_channel;                                 // cmd_demux_001:src17_channel -> cmd_mux_017:sink1_channel
	wire          cmd_demux_001_src17_startofpacket;                           // cmd_demux_001:src17_startofpacket -> cmd_mux_017:sink1_startofpacket
	wire          cmd_demux_001_src17_endofpacket;                             // cmd_demux_001:src17_endofpacket -> cmd_mux_017:sink1_endofpacket
	wire          cmd_demux_001_src18_valid;                                   // cmd_demux_001:src18_valid -> cmd_mux_018:sink1_valid
	wire  [128:0] cmd_demux_001_src18_data;                                    // cmd_demux_001:src18_data -> cmd_mux_018:sink1_data
	wire          cmd_demux_001_src18_ready;                                   // cmd_mux_018:sink1_ready -> cmd_demux_001:src18_ready
	wire   [21:0] cmd_demux_001_src18_channel;                                 // cmd_demux_001:src18_channel -> cmd_mux_018:sink1_channel
	wire          cmd_demux_001_src18_startofpacket;                           // cmd_demux_001:src18_startofpacket -> cmd_mux_018:sink1_startofpacket
	wire          cmd_demux_001_src18_endofpacket;                             // cmd_demux_001:src18_endofpacket -> cmd_mux_018:sink1_endofpacket
	wire          cmd_demux_001_src19_valid;                                   // cmd_demux_001:src19_valid -> cmd_mux_019:sink1_valid
	wire  [128:0] cmd_demux_001_src19_data;                                    // cmd_demux_001:src19_data -> cmd_mux_019:sink1_data
	wire          cmd_demux_001_src19_ready;                                   // cmd_mux_019:sink1_ready -> cmd_demux_001:src19_ready
	wire   [21:0] cmd_demux_001_src19_channel;                                 // cmd_demux_001:src19_channel -> cmd_mux_019:sink1_channel
	wire          cmd_demux_001_src19_startofpacket;                           // cmd_demux_001:src19_startofpacket -> cmd_mux_019:sink1_startofpacket
	wire          cmd_demux_001_src19_endofpacket;                             // cmd_demux_001:src19_endofpacket -> cmd_mux_019:sink1_endofpacket
	wire          cmd_demux_001_src20_valid;                                   // cmd_demux_001:src20_valid -> cmd_mux_020:sink1_valid
	wire  [128:0] cmd_demux_001_src20_data;                                    // cmd_demux_001:src20_data -> cmd_mux_020:sink1_data
	wire          cmd_demux_001_src20_ready;                                   // cmd_mux_020:sink1_ready -> cmd_demux_001:src20_ready
	wire   [21:0] cmd_demux_001_src20_channel;                                 // cmd_demux_001:src20_channel -> cmd_mux_020:sink1_channel
	wire          cmd_demux_001_src20_startofpacket;                           // cmd_demux_001:src20_startofpacket -> cmd_mux_020:sink1_startofpacket
	wire          cmd_demux_001_src20_endofpacket;                             // cmd_demux_001:src20_endofpacket -> cmd_mux_020:sink1_endofpacket
	wire          cmd_demux_001_src21_valid;                                   // cmd_demux_001:src21_valid -> cmd_mux_021:sink1_valid
	wire  [128:0] cmd_demux_001_src21_data;                                    // cmd_demux_001:src21_data -> cmd_mux_021:sink1_data
	wire          cmd_demux_001_src21_ready;                                   // cmd_mux_021:sink1_ready -> cmd_demux_001:src21_ready
	wire   [21:0] cmd_demux_001_src21_channel;                                 // cmd_demux_001:src21_channel -> cmd_mux_021:sink1_channel
	wire          cmd_demux_001_src21_startofpacket;                           // cmd_demux_001:src21_startofpacket -> cmd_mux_021:sink1_startofpacket
	wire          cmd_demux_001_src21_endofpacket;                             // cmd_demux_001:src21_endofpacket -> cmd_mux_021:sink1_endofpacket
	wire          rsp_demux_src0_valid;                                        // rsp_demux:src0_valid -> rsp_mux:sink0_valid
	wire  [128:0] rsp_demux_src0_data;                                         // rsp_demux:src0_data -> rsp_mux:sink0_data
	wire          rsp_demux_src0_ready;                                        // rsp_mux:sink0_ready -> rsp_demux:src0_ready
	wire   [21:0] rsp_demux_src0_channel;                                      // rsp_demux:src0_channel -> rsp_mux:sink0_channel
	wire          rsp_demux_src0_startofpacket;                                // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
	wire          rsp_demux_src0_endofpacket;                                  // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
	wire          rsp_demux_src1_valid;                                        // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
	wire  [128:0] rsp_demux_src1_data;                                         // rsp_demux:src1_data -> rsp_mux_001:sink0_data
	wire          rsp_demux_src1_ready;                                        // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
	wire   [21:0] rsp_demux_src1_channel;                                      // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
	wire          rsp_demux_src1_startofpacket;                                // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
	wire          rsp_demux_src1_endofpacket;                                  // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
	wire          rsp_demux_001_src0_valid;                                    // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
	wire  [128:0] rsp_demux_001_src0_data;                                     // rsp_demux_001:src0_data -> rsp_mux:sink1_data
	wire          rsp_demux_001_src0_ready;                                    // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
	wire   [21:0] rsp_demux_001_src0_channel;                                  // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
	wire          rsp_demux_001_src0_startofpacket;                            // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
	wire          rsp_demux_001_src0_endofpacket;                              // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
	wire          rsp_demux_001_src1_valid;                                    // rsp_demux_001:src1_valid -> rsp_mux_001:sink1_valid
	wire  [128:0] rsp_demux_001_src1_data;                                     // rsp_demux_001:src1_data -> rsp_mux_001:sink1_data
	wire          rsp_demux_001_src1_ready;                                    // rsp_mux_001:sink1_ready -> rsp_demux_001:src1_ready
	wire   [21:0] rsp_demux_001_src1_channel;                                  // rsp_demux_001:src1_channel -> rsp_mux_001:sink1_channel
	wire          rsp_demux_001_src1_startofpacket;                            // rsp_demux_001:src1_startofpacket -> rsp_mux_001:sink1_startofpacket
	wire          rsp_demux_001_src1_endofpacket;                              // rsp_demux_001:src1_endofpacket -> rsp_mux_001:sink1_endofpacket
	wire          rsp_demux_002_src0_valid;                                    // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
	wire  [128:0] rsp_demux_002_src0_data;                                     // rsp_demux_002:src0_data -> rsp_mux:sink2_data
	wire          rsp_demux_002_src0_ready;                                    // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
	wire   [21:0] rsp_demux_002_src0_channel;                                  // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
	wire          rsp_demux_002_src0_startofpacket;                            // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
	wire          rsp_demux_002_src0_endofpacket;                              // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
	wire          rsp_demux_002_src1_valid;                                    // rsp_demux_002:src1_valid -> rsp_mux_001:sink2_valid
	wire  [128:0] rsp_demux_002_src1_data;                                     // rsp_demux_002:src1_data -> rsp_mux_001:sink2_data
	wire          rsp_demux_002_src1_ready;                                    // rsp_mux_001:sink2_ready -> rsp_demux_002:src1_ready
	wire   [21:0] rsp_demux_002_src1_channel;                                  // rsp_demux_002:src1_channel -> rsp_mux_001:sink2_channel
	wire          rsp_demux_002_src1_startofpacket;                            // rsp_demux_002:src1_startofpacket -> rsp_mux_001:sink2_startofpacket
	wire          rsp_demux_002_src1_endofpacket;                              // rsp_demux_002:src1_endofpacket -> rsp_mux_001:sink2_endofpacket
	wire          rsp_demux_003_src0_valid;                                    // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
	wire  [128:0] rsp_demux_003_src0_data;                                     // rsp_demux_003:src0_data -> rsp_mux:sink3_data
	wire          rsp_demux_003_src0_ready;                                    // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
	wire   [21:0] rsp_demux_003_src0_channel;                                  // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
	wire          rsp_demux_003_src0_startofpacket;                            // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
	wire          rsp_demux_003_src0_endofpacket;                              // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
	wire          rsp_demux_003_src1_valid;                                    // rsp_demux_003:src1_valid -> rsp_mux_001:sink3_valid
	wire  [128:0] rsp_demux_003_src1_data;                                     // rsp_demux_003:src1_data -> rsp_mux_001:sink3_data
	wire          rsp_demux_003_src1_ready;                                    // rsp_mux_001:sink3_ready -> rsp_demux_003:src1_ready
	wire   [21:0] rsp_demux_003_src1_channel;                                  // rsp_demux_003:src1_channel -> rsp_mux_001:sink3_channel
	wire          rsp_demux_003_src1_startofpacket;                            // rsp_demux_003:src1_startofpacket -> rsp_mux_001:sink3_startofpacket
	wire          rsp_demux_003_src1_endofpacket;                              // rsp_demux_003:src1_endofpacket -> rsp_mux_001:sink3_endofpacket
	wire          rsp_demux_004_src0_valid;                                    // rsp_demux_004:src0_valid -> rsp_mux:sink4_valid
	wire  [128:0] rsp_demux_004_src0_data;                                     // rsp_demux_004:src0_data -> rsp_mux:sink4_data
	wire          rsp_demux_004_src0_ready;                                    // rsp_mux:sink4_ready -> rsp_demux_004:src0_ready
	wire   [21:0] rsp_demux_004_src0_channel;                                  // rsp_demux_004:src0_channel -> rsp_mux:sink4_channel
	wire          rsp_demux_004_src0_startofpacket;                            // rsp_demux_004:src0_startofpacket -> rsp_mux:sink4_startofpacket
	wire          rsp_demux_004_src0_endofpacket;                              // rsp_demux_004:src0_endofpacket -> rsp_mux:sink4_endofpacket
	wire          rsp_demux_004_src1_valid;                                    // rsp_demux_004:src1_valid -> rsp_mux_001:sink4_valid
	wire  [128:0] rsp_demux_004_src1_data;                                     // rsp_demux_004:src1_data -> rsp_mux_001:sink4_data
	wire          rsp_demux_004_src1_ready;                                    // rsp_mux_001:sink4_ready -> rsp_demux_004:src1_ready
	wire   [21:0] rsp_demux_004_src1_channel;                                  // rsp_demux_004:src1_channel -> rsp_mux_001:sink4_channel
	wire          rsp_demux_004_src1_startofpacket;                            // rsp_demux_004:src1_startofpacket -> rsp_mux_001:sink4_startofpacket
	wire          rsp_demux_004_src1_endofpacket;                              // rsp_demux_004:src1_endofpacket -> rsp_mux_001:sink4_endofpacket
	wire          rsp_demux_005_src0_valid;                                    // rsp_demux_005:src0_valid -> rsp_mux:sink5_valid
	wire  [128:0] rsp_demux_005_src0_data;                                     // rsp_demux_005:src0_data -> rsp_mux:sink5_data
	wire          rsp_demux_005_src0_ready;                                    // rsp_mux:sink5_ready -> rsp_demux_005:src0_ready
	wire   [21:0] rsp_demux_005_src0_channel;                                  // rsp_demux_005:src0_channel -> rsp_mux:sink5_channel
	wire          rsp_demux_005_src0_startofpacket;                            // rsp_demux_005:src0_startofpacket -> rsp_mux:sink5_startofpacket
	wire          rsp_demux_005_src0_endofpacket;                              // rsp_demux_005:src0_endofpacket -> rsp_mux:sink5_endofpacket
	wire          rsp_demux_005_src1_valid;                                    // rsp_demux_005:src1_valid -> rsp_mux_001:sink5_valid
	wire  [128:0] rsp_demux_005_src1_data;                                     // rsp_demux_005:src1_data -> rsp_mux_001:sink5_data
	wire          rsp_demux_005_src1_ready;                                    // rsp_mux_001:sink5_ready -> rsp_demux_005:src1_ready
	wire   [21:0] rsp_demux_005_src1_channel;                                  // rsp_demux_005:src1_channel -> rsp_mux_001:sink5_channel
	wire          rsp_demux_005_src1_startofpacket;                            // rsp_demux_005:src1_startofpacket -> rsp_mux_001:sink5_startofpacket
	wire          rsp_demux_005_src1_endofpacket;                              // rsp_demux_005:src1_endofpacket -> rsp_mux_001:sink5_endofpacket
	wire          rsp_demux_006_src0_valid;                                    // rsp_demux_006:src0_valid -> rsp_mux:sink6_valid
	wire  [128:0] rsp_demux_006_src0_data;                                     // rsp_demux_006:src0_data -> rsp_mux:sink6_data
	wire          rsp_demux_006_src0_ready;                                    // rsp_mux:sink6_ready -> rsp_demux_006:src0_ready
	wire   [21:0] rsp_demux_006_src0_channel;                                  // rsp_demux_006:src0_channel -> rsp_mux:sink6_channel
	wire          rsp_demux_006_src0_startofpacket;                            // rsp_demux_006:src0_startofpacket -> rsp_mux:sink6_startofpacket
	wire          rsp_demux_006_src0_endofpacket;                              // rsp_demux_006:src0_endofpacket -> rsp_mux:sink6_endofpacket
	wire          rsp_demux_006_src1_valid;                                    // rsp_demux_006:src1_valid -> rsp_mux_001:sink6_valid
	wire  [128:0] rsp_demux_006_src1_data;                                     // rsp_demux_006:src1_data -> rsp_mux_001:sink6_data
	wire          rsp_demux_006_src1_ready;                                    // rsp_mux_001:sink6_ready -> rsp_demux_006:src1_ready
	wire   [21:0] rsp_demux_006_src1_channel;                                  // rsp_demux_006:src1_channel -> rsp_mux_001:sink6_channel
	wire          rsp_demux_006_src1_startofpacket;                            // rsp_demux_006:src1_startofpacket -> rsp_mux_001:sink6_startofpacket
	wire          rsp_demux_006_src1_endofpacket;                              // rsp_demux_006:src1_endofpacket -> rsp_mux_001:sink6_endofpacket
	wire          rsp_demux_007_src0_valid;                                    // rsp_demux_007:src0_valid -> rsp_mux:sink7_valid
	wire  [128:0] rsp_demux_007_src0_data;                                     // rsp_demux_007:src0_data -> rsp_mux:sink7_data
	wire          rsp_demux_007_src0_ready;                                    // rsp_mux:sink7_ready -> rsp_demux_007:src0_ready
	wire   [21:0] rsp_demux_007_src0_channel;                                  // rsp_demux_007:src0_channel -> rsp_mux:sink7_channel
	wire          rsp_demux_007_src0_startofpacket;                            // rsp_demux_007:src0_startofpacket -> rsp_mux:sink7_startofpacket
	wire          rsp_demux_007_src0_endofpacket;                              // rsp_demux_007:src0_endofpacket -> rsp_mux:sink7_endofpacket
	wire          rsp_demux_007_src1_valid;                                    // rsp_demux_007:src1_valid -> rsp_mux_001:sink7_valid
	wire  [128:0] rsp_demux_007_src1_data;                                     // rsp_demux_007:src1_data -> rsp_mux_001:sink7_data
	wire          rsp_demux_007_src1_ready;                                    // rsp_mux_001:sink7_ready -> rsp_demux_007:src1_ready
	wire   [21:0] rsp_demux_007_src1_channel;                                  // rsp_demux_007:src1_channel -> rsp_mux_001:sink7_channel
	wire          rsp_demux_007_src1_startofpacket;                            // rsp_demux_007:src1_startofpacket -> rsp_mux_001:sink7_startofpacket
	wire          rsp_demux_007_src1_endofpacket;                              // rsp_demux_007:src1_endofpacket -> rsp_mux_001:sink7_endofpacket
	wire          rsp_demux_008_src0_valid;                                    // rsp_demux_008:src0_valid -> rsp_mux:sink8_valid
	wire  [128:0] rsp_demux_008_src0_data;                                     // rsp_demux_008:src0_data -> rsp_mux:sink8_data
	wire          rsp_demux_008_src0_ready;                                    // rsp_mux:sink8_ready -> rsp_demux_008:src0_ready
	wire   [21:0] rsp_demux_008_src0_channel;                                  // rsp_demux_008:src0_channel -> rsp_mux:sink8_channel
	wire          rsp_demux_008_src0_startofpacket;                            // rsp_demux_008:src0_startofpacket -> rsp_mux:sink8_startofpacket
	wire          rsp_demux_008_src0_endofpacket;                              // rsp_demux_008:src0_endofpacket -> rsp_mux:sink8_endofpacket
	wire          rsp_demux_008_src1_valid;                                    // rsp_demux_008:src1_valid -> rsp_mux_001:sink8_valid
	wire  [128:0] rsp_demux_008_src1_data;                                     // rsp_demux_008:src1_data -> rsp_mux_001:sink8_data
	wire          rsp_demux_008_src1_ready;                                    // rsp_mux_001:sink8_ready -> rsp_demux_008:src1_ready
	wire   [21:0] rsp_demux_008_src1_channel;                                  // rsp_demux_008:src1_channel -> rsp_mux_001:sink8_channel
	wire          rsp_demux_008_src1_startofpacket;                            // rsp_demux_008:src1_startofpacket -> rsp_mux_001:sink8_startofpacket
	wire          rsp_demux_008_src1_endofpacket;                              // rsp_demux_008:src1_endofpacket -> rsp_mux_001:sink8_endofpacket
	wire          rsp_demux_009_src0_valid;                                    // rsp_demux_009:src0_valid -> rsp_mux:sink9_valid
	wire  [128:0] rsp_demux_009_src0_data;                                     // rsp_demux_009:src0_data -> rsp_mux:sink9_data
	wire          rsp_demux_009_src0_ready;                                    // rsp_mux:sink9_ready -> rsp_demux_009:src0_ready
	wire   [21:0] rsp_demux_009_src0_channel;                                  // rsp_demux_009:src0_channel -> rsp_mux:sink9_channel
	wire          rsp_demux_009_src0_startofpacket;                            // rsp_demux_009:src0_startofpacket -> rsp_mux:sink9_startofpacket
	wire          rsp_demux_009_src0_endofpacket;                              // rsp_demux_009:src0_endofpacket -> rsp_mux:sink9_endofpacket
	wire          rsp_demux_009_src1_valid;                                    // rsp_demux_009:src1_valid -> rsp_mux_001:sink9_valid
	wire  [128:0] rsp_demux_009_src1_data;                                     // rsp_demux_009:src1_data -> rsp_mux_001:sink9_data
	wire          rsp_demux_009_src1_ready;                                    // rsp_mux_001:sink9_ready -> rsp_demux_009:src1_ready
	wire   [21:0] rsp_demux_009_src1_channel;                                  // rsp_demux_009:src1_channel -> rsp_mux_001:sink9_channel
	wire          rsp_demux_009_src1_startofpacket;                            // rsp_demux_009:src1_startofpacket -> rsp_mux_001:sink9_startofpacket
	wire          rsp_demux_009_src1_endofpacket;                              // rsp_demux_009:src1_endofpacket -> rsp_mux_001:sink9_endofpacket
	wire          rsp_demux_010_src0_valid;                                    // rsp_demux_010:src0_valid -> rsp_mux:sink10_valid
	wire  [128:0] rsp_demux_010_src0_data;                                     // rsp_demux_010:src0_data -> rsp_mux:sink10_data
	wire          rsp_demux_010_src0_ready;                                    // rsp_mux:sink10_ready -> rsp_demux_010:src0_ready
	wire   [21:0] rsp_demux_010_src0_channel;                                  // rsp_demux_010:src0_channel -> rsp_mux:sink10_channel
	wire          rsp_demux_010_src0_startofpacket;                            // rsp_demux_010:src0_startofpacket -> rsp_mux:sink10_startofpacket
	wire          rsp_demux_010_src0_endofpacket;                              // rsp_demux_010:src0_endofpacket -> rsp_mux:sink10_endofpacket
	wire          rsp_demux_010_src1_valid;                                    // rsp_demux_010:src1_valid -> rsp_mux_001:sink10_valid
	wire  [128:0] rsp_demux_010_src1_data;                                     // rsp_demux_010:src1_data -> rsp_mux_001:sink10_data
	wire          rsp_demux_010_src1_ready;                                    // rsp_mux_001:sink10_ready -> rsp_demux_010:src1_ready
	wire   [21:0] rsp_demux_010_src1_channel;                                  // rsp_demux_010:src1_channel -> rsp_mux_001:sink10_channel
	wire          rsp_demux_010_src1_startofpacket;                            // rsp_demux_010:src1_startofpacket -> rsp_mux_001:sink10_startofpacket
	wire          rsp_demux_010_src1_endofpacket;                              // rsp_demux_010:src1_endofpacket -> rsp_mux_001:sink10_endofpacket
	wire          rsp_demux_011_src0_valid;                                    // rsp_demux_011:src0_valid -> rsp_mux:sink11_valid
	wire  [128:0] rsp_demux_011_src0_data;                                     // rsp_demux_011:src0_data -> rsp_mux:sink11_data
	wire          rsp_demux_011_src0_ready;                                    // rsp_mux:sink11_ready -> rsp_demux_011:src0_ready
	wire   [21:0] rsp_demux_011_src0_channel;                                  // rsp_demux_011:src0_channel -> rsp_mux:sink11_channel
	wire          rsp_demux_011_src0_startofpacket;                            // rsp_demux_011:src0_startofpacket -> rsp_mux:sink11_startofpacket
	wire          rsp_demux_011_src0_endofpacket;                              // rsp_demux_011:src0_endofpacket -> rsp_mux:sink11_endofpacket
	wire          rsp_demux_011_src1_valid;                                    // rsp_demux_011:src1_valid -> rsp_mux_001:sink11_valid
	wire  [128:0] rsp_demux_011_src1_data;                                     // rsp_demux_011:src1_data -> rsp_mux_001:sink11_data
	wire          rsp_demux_011_src1_ready;                                    // rsp_mux_001:sink11_ready -> rsp_demux_011:src1_ready
	wire   [21:0] rsp_demux_011_src1_channel;                                  // rsp_demux_011:src1_channel -> rsp_mux_001:sink11_channel
	wire          rsp_demux_011_src1_startofpacket;                            // rsp_demux_011:src1_startofpacket -> rsp_mux_001:sink11_startofpacket
	wire          rsp_demux_011_src1_endofpacket;                              // rsp_demux_011:src1_endofpacket -> rsp_mux_001:sink11_endofpacket
	wire          rsp_demux_012_src0_valid;                                    // rsp_demux_012:src0_valid -> rsp_mux:sink12_valid
	wire  [128:0] rsp_demux_012_src0_data;                                     // rsp_demux_012:src0_data -> rsp_mux:sink12_data
	wire          rsp_demux_012_src0_ready;                                    // rsp_mux:sink12_ready -> rsp_demux_012:src0_ready
	wire   [21:0] rsp_demux_012_src0_channel;                                  // rsp_demux_012:src0_channel -> rsp_mux:sink12_channel
	wire          rsp_demux_012_src0_startofpacket;                            // rsp_demux_012:src0_startofpacket -> rsp_mux:sink12_startofpacket
	wire          rsp_demux_012_src0_endofpacket;                              // rsp_demux_012:src0_endofpacket -> rsp_mux:sink12_endofpacket
	wire          rsp_demux_012_src1_valid;                                    // rsp_demux_012:src1_valid -> rsp_mux_001:sink12_valid
	wire  [128:0] rsp_demux_012_src1_data;                                     // rsp_demux_012:src1_data -> rsp_mux_001:sink12_data
	wire          rsp_demux_012_src1_ready;                                    // rsp_mux_001:sink12_ready -> rsp_demux_012:src1_ready
	wire   [21:0] rsp_demux_012_src1_channel;                                  // rsp_demux_012:src1_channel -> rsp_mux_001:sink12_channel
	wire          rsp_demux_012_src1_startofpacket;                            // rsp_demux_012:src1_startofpacket -> rsp_mux_001:sink12_startofpacket
	wire          rsp_demux_012_src1_endofpacket;                              // rsp_demux_012:src1_endofpacket -> rsp_mux_001:sink12_endofpacket
	wire          rsp_demux_013_src0_valid;                                    // rsp_demux_013:src0_valid -> rsp_mux:sink13_valid
	wire  [128:0] rsp_demux_013_src0_data;                                     // rsp_demux_013:src0_data -> rsp_mux:sink13_data
	wire          rsp_demux_013_src0_ready;                                    // rsp_mux:sink13_ready -> rsp_demux_013:src0_ready
	wire   [21:0] rsp_demux_013_src0_channel;                                  // rsp_demux_013:src0_channel -> rsp_mux:sink13_channel
	wire          rsp_demux_013_src0_startofpacket;                            // rsp_demux_013:src0_startofpacket -> rsp_mux:sink13_startofpacket
	wire          rsp_demux_013_src0_endofpacket;                              // rsp_demux_013:src0_endofpacket -> rsp_mux:sink13_endofpacket
	wire          rsp_demux_013_src1_valid;                                    // rsp_demux_013:src1_valid -> rsp_mux_001:sink13_valid
	wire  [128:0] rsp_demux_013_src1_data;                                     // rsp_demux_013:src1_data -> rsp_mux_001:sink13_data
	wire          rsp_demux_013_src1_ready;                                    // rsp_mux_001:sink13_ready -> rsp_demux_013:src1_ready
	wire   [21:0] rsp_demux_013_src1_channel;                                  // rsp_demux_013:src1_channel -> rsp_mux_001:sink13_channel
	wire          rsp_demux_013_src1_startofpacket;                            // rsp_demux_013:src1_startofpacket -> rsp_mux_001:sink13_startofpacket
	wire          rsp_demux_013_src1_endofpacket;                              // rsp_demux_013:src1_endofpacket -> rsp_mux_001:sink13_endofpacket
	wire          rsp_demux_014_src0_valid;                                    // rsp_demux_014:src0_valid -> rsp_mux:sink14_valid
	wire  [128:0] rsp_demux_014_src0_data;                                     // rsp_demux_014:src0_data -> rsp_mux:sink14_data
	wire          rsp_demux_014_src0_ready;                                    // rsp_mux:sink14_ready -> rsp_demux_014:src0_ready
	wire   [21:0] rsp_demux_014_src0_channel;                                  // rsp_demux_014:src0_channel -> rsp_mux:sink14_channel
	wire          rsp_demux_014_src0_startofpacket;                            // rsp_demux_014:src0_startofpacket -> rsp_mux:sink14_startofpacket
	wire          rsp_demux_014_src0_endofpacket;                              // rsp_demux_014:src0_endofpacket -> rsp_mux:sink14_endofpacket
	wire          rsp_demux_014_src1_valid;                                    // rsp_demux_014:src1_valid -> rsp_mux_001:sink14_valid
	wire  [128:0] rsp_demux_014_src1_data;                                     // rsp_demux_014:src1_data -> rsp_mux_001:sink14_data
	wire          rsp_demux_014_src1_ready;                                    // rsp_mux_001:sink14_ready -> rsp_demux_014:src1_ready
	wire   [21:0] rsp_demux_014_src1_channel;                                  // rsp_demux_014:src1_channel -> rsp_mux_001:sink14_channel
	wire          rsp_demux_014_src1_startofpacket;                            // rsp_demux_014:src1_startofpacket -> rsp_mux_001:sink14_startofpacket
	wire          rsp_demux_014_src1_endofpacket;                              // rsp_demux_014:src1_endofpacket -> rsp_mux_001:sink14_endofpacket
	wire          rsp_demux_015_src0_valid;                                    // rsp_demux_015:src0_valid -> rsp_mux:sink15_valid
	wire  [128:0] rsp_demux_015_src0_data;                                     // rsp_demux_015:src0_data -> rsp_mux:sink15_data
	wire          rsp_demux_015_src0_ready;                                    // rsp_mux:sink15_ready -> rsp_demux_015:src0_ready
	wire   [21:0] rsp_demux_015_src0_channel;                                  // rsp_demux_015:src0_channel -> rsp_mux:sink15_channel
	wire          rsp_demux_015_src0_startofpacket;                            // rsp_demux_015:src0_startofpacket -> rsp_mux:sink15_startofpacket
	wire          rsp_demux_015_src0_endofpacket;                              // rsp_demux_015:src0_endofpacket -> rsp_mux:sink15_endofpacket
	wire          rsp_demux_015_src1_valid;                                    // rsp_demux_015:src1_valid -> rsp_mux_001:sink15_valid
	wire  [128:0] rsp_demux_015_src1_data;                                     // rsp_demux_015:src1_data -> rsp_mux_001:sink15_data
	wire          rsp_demux_015_src1_ready;                                    // rsp_mux_001:sink15_ready -> rsp_demux_015:src1_ready
	wire   [21:0] rsp_demux_015_src1_channel;                                  // rsp_demux_015:src1_channel -> rsp_mux_001:sink15_channel
	wire          rsp_demux_015_src1_startofpacket;                            // rsp_demux_015:src1_startofpacket -> rsp_mux_001:sink15_startofpacket
	wire          rsp_demux_015_src1_endofpacket;                              // rsp_demux_015:src1_endofpacket -> rsp_mux_001:sink15_endofpacket
	wire          rsp_demux_016_src0_valid;                                    // rsp_demux_016:src0_valid -> rsp_mux:sink16_valid
	wire  [128:0] rsp_demux_016_src0_data;                                     // rsp_demux_016:src0_data -> rsp_mux:sink16_data
	wire          rsp_demux_016_src0_ready;                                    // rsp_mux:sink16_ready -> rsp_demux_016:src0_ready
	wire   [21:0] rsp_demux_016_src0_channel;                                  // rsp_demux_016:src0_channel -> rsp_mux:sink16_channel
	wire          rsp_demux_016_src0_startofpacket;                            // rsp_demux_016:src0_startofpacket -> rsp_mux:sink16_startofpacket
	wire          rsp_demux_016_src0_endofpacket;                              // rsp_demux_016:src0_endofpacket -> rsp_mux:sink16_endofpacket
	wire          rsp_demux_016_src1_valid;                                    // rsp_demux_016:src1_valid -> rsp_mux_001:sink16_valid
	wire  [128:0] rsp_demux_016_src1_data;                                     // rsp_demux_016:src1_data -> rsp_mux_001:sink16_data
	wire          rsp_demux_016_src1_ready;                                    // rsp_mux_001:sink16_ready -> rsp_demux_016:src1_ready
	wire   [21:0] rsp_demux_016_src1_channel;                                  // rsp_demux_016:src1_channel -> rsp_mux_001:sink16_channel
	wire          rsp_demux_016_src1_startofpacket;                            // rsp_demux_016:src1_startofpacket -> rsp_mux_001:sink16_startofpacket
	wire          rsp_demux_016_src1_endofpacket;                              // rsp_demux_016:src1_endofpacket -> rsp_mux_001:sink16_endofpacket
	wire          rsp_demux_017_src0_valid;                                    // rsp_demux_017:src0_valid -> rsp_mux:sink17_valid
	wire  [128:0] rsp_demux_017_src0_data;                                     // rsp_demux_017:src0_data -> rsp_mux:sink17_data
	wire          rsp_demux_017_src0_ready;                                    // rsp_mux:sink17_ready -> rsp_demux_017:src0_ready
	wire   [21:0] rsp_demux_017_src0_channel;                                  // rsp_demux_017:src0_channel -> rsp_mux:sink17_channel
	wire          rsp_demux_017_src0_startofpacket;                            // rsp_demux_017:src0_startofpacket -> rsp_mux:sink17_startofpacket
	wire          rsp_demux_017_src0_endofpacket;                              // rsp_demux_017:src0_endofpacket -> rsp_mux:sink17_endofpacket
	wire          rsp_demux_017_src1_valid;                                    // rsp_demux_017:src1_valid -> rsp_mux_001:sink17_valid
	wire  [128:0] rsp_demux_017_src1_data;                                     // rsp_demux_017:src1_data -> rsp_mux_001:sink17_data
	wire          rsp_demux_017_src1_ready;                                    // rsp_mux_001:sink17_ready -> rsp_demux_017:src1_ready
	wire   [21:0] rsp_demux_017_src1_channel;                                  // rsp_demux_017:src1_channel -> rsp_mux_001:sink17_channel
	wire          rsp_demux_017_src1_startofpacket;                            // rsp_demux_017:src1_startofpacket -> rsp_mux_001:sink17_startofpacket
	wire          rsp_demux_017_src1_endofpacket;                              // rsp_demux_017:src1_endofpacket -> rsp_mux_001:sink17_endofpacket
	wire          rsp_demux_018_src0_valid;                                    // rsp_demux_018:src0_valid -> rsp_mux:sink18_valid
	wire  [128:0] rsp_demux_018_src0_data;                                     // rsp_demux_018:src0_data -> rsp_mux:sink18_data
	wire          rsp_demux_018_src0_ready;                                    // rsp_mux:sink18_ready -> rsp_demux_018:src0_ready
	wire   [21:0] rsp_demux_018_src0_channel;                                  // rsp_demux_018:src0_channel -> rsp_mux:sink18_channel
	wire          rsp_demux_018_src0_startofpacket;                            // rsp_demux_018:src0_startofpacket -> rsp_mux:sink18_startofpacket
	wire          rsp_demux_018_src0_endofpacket;                              // rsp_demux_018:src0_endofpacket -> rsp_mux:sink18_endofpacket
	wire          rsp_demux_018_src1_valid;                                    // rsp_demux_018:src1_valid -> rsp_mux_001:sink18_valid
	wire  [128:0] rsp_demux_018_src1_data;                                     // rsp_demux_018:src1_data -> rsp_mux_001:sink18_data
	wire          rsp_demux_018_src1_ready;                                    // rsp_mux_001:sink18_ready -> rsp_demux_018:src1_ready
	wire   [21:0] rsp_demux_018_src1_channel;                                  // rsp_demux_018:src1_channel -> rsp_mux_001:sink18_channel
	wire          rsp_demux_018_src1_startofpacket;                            // rsp_demux_018:src1_startofpacket -> rsp_mux_001:sink18_startofpacket
	wire          rsp_demux_018_src1_endofpacket;                              // rsp_demux_018:src1_endofpacket -> rsp_mux_001:sink18_endofpacket
	wire          rsp_demux_019_src0_valid;                                    // rsp_demux_019:src0_valid -> rsp_mux:sink19_valid
	wire  [128:0] rsp_demux_019_src0_data;                                     // rsp_demux_019:src0_data -> rsp_mux:sink19_data
	wire          rsp_demux_019_src0_ready;                                    // rsp_mux:sink19_ready -> rsp_demux_019:src0_ready
	wire   [21:0] rsp_demux_019_src0_channel;                                  // rsp_demux_019:src0_channel -> rsp_mux:sink19_channel
	wire          rsp_demux_019_src0_startofpacket;                            // rsp_demux_019:src0_startofpacket -> rsp_mux:sink19_startofpacket
	wire          rsp_demux_019_src0_endofpacket;                              // rsp_demux_019:src0_endofpacket -> rsp_mux:sink19_endofpacket
	wire          rsp_demux_019_src1_valid;                                    // rsp_demux_019:src1_valid -> rsp_mux_001:sink19_valid
	wire  [128:0] rsp_demux_019_src1_data;                                     // rsp_demux_019:src1_data -> rsp_mux_001:sink19_data
	wire          rsp_demux_019_src1_ready;                                    // rsp_mux_001:sink19_ready -> rsp_demux_019:src1_ready
	wire   [21:0] rsp_demux_019_src1_channel;                                  // rsp_demux_019:src1_channel -> rsp_mux_001:sink19_channel
	wire          rsp_demux_019_src1_startofpacket;                            // rsp_demux_019:src1_startofpacket -> rsp_mux_001:sink19_startofpacket
	wire          rsp_demux_019_src1_endofpacket;                              // rsp_demux_019:src1_endofpacket -> rsp_mux_001:sink19_endofpacket
	wire          rsp_demux_020_src0_valid;                                    // rsp_demux_020:src0_valid -> rsp_mux:sink20_valid
	wire  [128:0] rsp_demux_020_src0_data;                                     // rsp_demux_020:src0_data -> rsp_mux:sink20_data
	wire          rsp_demux_020_src0_ready;                                    // rsp_mux:sink20_ready -> rsp_demux_020:src0_ready
	wire   [21:0] rsp_demux_020_src0_channel;                                  // rsp_demux_020:src0_channel -> rsp_mux:sink20_channel
	wire          rsp_demux_020_src0_startofpacket;                            // rsp_demux_020:src0_startofpacket -> rsp_mux:sink20_startofpacket
	wire          rsp_demux_020_src0_endofpacket;                              // rsp_demux_020:src0_endofpacket -> rsp_mux:sink20_endofpacket
	wire          rsp_demux_020_src1_valid;                                    // rsp_demux_020:src1_valid -> rsp_mux_001:sink20_valid
	wire  [128:0] rsp_demux_020_src1_data;                                     // rsp_demux_020:src1_data -> rsp_mux_001:sink20_data
	wire          rsp_demux_020_src1_ready;                                    // rsp_mux_001:sink20_ready -> rsp_demux_020:src1_ready
	wire   [21:0] rsp_demux_020_src1_channel;                                  // rsp_demux_020:src1_channel -> rsp_mux_001:sink20_channel
	wire          rsp_demux_020_src1_startofpacket;                            // rsp_demux_020:src1_startofpacket -> rsp_mux_001:sink20_startofpacket
	wire          rsp_demux_020_src1_endofpacket;                              // rsp_demux_020:src1_endofpacket -> rsp_mux_001:sink20_endofpacket
	wire          rsp_demux_021_src0_valid;                                    // rsp_demux_021:src0_valid -> rsp_mux:sink21_valid
	wire  [128:0] rsp_demux_021_src0_data;                                     // rsp_demux_021:src0_data -> rsp_mux:sink21_data
	wire          rsp_demux_021_src0_ready;                                    // rsp_mux:sink21_ready -> rsp_demux_021:src0_ready
	wire   [21:0] rsp_demux_021_src0_channel;                                  // rsp_demux_021:src0_channel -> rsp_mux:sink21_channel
	wire          rsp_demux_021_src0_startofpacket;                            // rsp_demux_021:src0_startofpacket -> rsp_mux:sink21_startofpacket
	wire          rsp_demux_021_src0_endofpacket;                              // rsp_demux_021:src0_endofpacket -> rsp_mux:sink21_endofpacket
	wire          rsp_demux_021_src1_valid;                                    // rsp_demux_021:src1_valid -> rsp_mux_001:sink21_valid
	wire  [128:0] rsp_demux_021_src1_data;                                     // rsp_demux_021:src1_data -> rsp_mux_001:sink21_data
	wire          rsp_demux_021_src1_ready;                                    // rsp_mux_001:sink21_ready -> rsp_demux_021:src1_ready
	wire   [21:0] rsp_demux_021_src1_channel;                                  // rsp_demux_021:src1_channel -> rsp_mux_001:sink21_channel
	wire          rsp_demux_021_src1_startofpacket;                            // rsp_demux_021:src1_startofpacket -> rsp_mux_001:sink21_startofpacket
	wire          rsp_demux_021_src1_endofpacket;                              // rsp_demux_021:src1_endofpacket -> rsp_mux_001:sink21_endofpacket
	wire   [21:0] hps_0_h2f_axi_master_wr_limiter_cmd_valid_data;              // hps_0_h2f_axi_master_wr_limiter:cmd_src_valid -> cmd_demux:sink_valid
	wire   [21:0] hps_0_h2f_axi_master_rd_limiter_cmd_valid_data;              // hps_0_h2f_axi_master_rd_limiter:cmd_src_valid -> cmd_demux_001:sink_valid
	wire          led_pio_test_s1_agent_rdata_fifo_out_valid;                  // led_pio_test_s1_agent_rdata_fifo:out_valid -> avalon_st_adapter:in_0_valid
	wire   [33:0] led_pio_test_s1_agent_rdata_fifo_out_data;                   // led_pio_test_s1_agent_rdata_fifo:out_data -> avalon_st_adapter:in_0_data
	wire          led_pio_test_s1_agent_rdata_fifo_out_ready;                  // avalon_st_adapter:in_0_ready -> led_pio_test_s1_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_out_0_valid;                               // avalon_st_adapter:out_0_valid -> led_pio_test_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_out_0_data;                                // avalon_st_adapter:out_0_data -> led_pio_test_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_out_0_ready;                               // led_pio_test_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
	wire    [0:0] avalon_st_adapter_out_0_error;                               // avalon_st_adapter:out_0_error -> led_pio_test_s1_agent:rdata_fifo_sink_error
	wire          timecode_rx_s1_agent_rdata_fifo_out_valid;                   // timecode_rx_s1_agent_rdata_fifo:out_valid -> avalon_st_adapter_001:in_0_valid
	wire   [33:0] timecode_rx_s1_agent_rdata_fifo_out_data;                    // timecode_rx_s1_agent_rdata_fifo:out_data -> avalon_st_adapter_001:in_0_data
	wire          timecode_rx_s1_agent_rdata_fifo_out_ready;                   // avalon_st_adapter_001:in_0_ready -> timecode_rx_s1_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_001_out_0_valid;                           // avalon_st_adapter_001:out_0_valid -> timecode_rx_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_001_out_0_data;                            // avalon_st_adapter_001:out_0_data -> timecode_rx_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_001_out_0_ready;                           // timecode_rx_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
	wire    [0:0] avalon_st_adapter_001_out_0_error;                           // avalon_st_adapter_001:out_0_error -> timecode_rx_s1_agent:rdata_fifo_sink_error
	wire          timecode_ready_rx_s1_agent_rdata_fifo_out_valid;             // timecode_ready_rx_s1_agent_rdata_fifo:out_valid -> avalon_st_adapter_002:in_0_valid
	wire   [33:0] timecode_ready_rx_s1_agent_rdata_fifo_out_data;              // timecode_ready_rx_s1_agent_rdata_fifo:out_data -> avalon_st_adapter_002:in_0_data
	wire          timecode_ready_rx_s1_agent_rdata_fifo_out_ready;             // avalon_st_adapter_002:in_0_ready -> timecode_ready_rx_s1_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_002_out_0_valid;                           // avalon_st_adapter_002:out_0_valid -> timecode_ready_rx_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_002_out_0_data;                            // avalon_st_adapter_002:out_0_data -> timecode_ready_rx_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_002_out_0_ready;                           // timecode_ready_rx_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready
	wire    [0:0] avalon_st_adapter_002_out_0_error;                           // avalon_st_adapter_002:out_0_error -> timecode_ready_rx_s1_agent:rdata_fifo_sink_error
	wire          data_flag_rx_s1_agent_rdata_fifo_out_valid;                  // data_flag_rx_s1_agent_rdata_fifo:out_valid -> avalon_st_adapter_003:in_0_valid
	wire   [33:0] data_flag_rx_s1_agent_rdata_fifo_out_data;                   // data_flag_rx_s1_agent_rdata_fifo:out_data -> avalon_st_adapter_003:in_0_data
	wire          data_flag_rx_s1_agent_rdata_fifo_out_ready;                  // avalon_st_adapter_003:in_0_ready -> data_flag_rx_s1_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_003_out_0_valid;                           // avalon_st_adapter_003:out_0_valid -> data_flag_rx_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_003_out_0_data;                            // avalon_st_adapter_003:out_0_data -> data_flag_rx_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_003_out_0_ready;                           // data_flag_rx_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_003:out_0_ready
	wire    [0:0] avalon_st_adapter_003_out_0_error;                           // avalon_st_adapter_003:out_0_error -> data_flag_rx_s1_agent:rdata_fifo_sink_error
	wire          data_read_en_rx_s1_agent_rdata_fifo_out_valid;               // data_read_en_rx_s1_agent_rdata_fifo:out_valid -> avalon_st_adapter_004:in_0_valid
	wire   [33:0] data_read_en_rx_s1_agent_rdata_fifo_out_data;                // data_read_en_rx_s1_agent_rdata_fifo:out_data -> avalon_st_adapter_004:in_0_data
	wire          data_read_en_rx_s1_agent_rdata_fifo_out_ready;               // avalon_st_adapter_004:in_0_ready -> data_read_en_rx_s1_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_004_out_0_valid;                           // avalon_st_adapter_004:out_0_valid -> data_read_en_rx_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_004_out_0_data;                            // avalon_st_adapter_004:out_0_data -> data_read_en_rx_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_004_out_0_ready;                           // data_read_en_rx_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_004:out_0_ready
	wire    [0:0] avalon_st_adapter_004_out_0_error;                           // avalon_st_adapter_004:out_0_error -> data_read_en_rx_s1_agent:rdata_fifo_sink_error
	wire          fifo_full_rx_status_s1_agent_rdata_fifo_out_valid;           // fifo_full_rx_status_s1_agent_rdata_fifo:out_valid -> avalon_st_adapter_005:in_0_valid
	wire   [33:0] fifo_full_rx_status_s1_agent_rdata_fifo_out_data;            // fifo_full_rx_status_s1_agent_rdata_fifo:out_data -> avalon_st_adapter_005:in_0_data
	wire          fifo_full_rx_status_s1_agent_rdata_fifo_out_ready;           // avalon_st_adapter_005:in_0_ready -> fifo_full_rx_status_s1_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_005_out_0_valid;                           // avalon_st_adapter_005:out_0_valid -> fifo_full_rx_status_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_005_out_0_data;                            // avalon_st_adapter_005:out_0_data -> fifo_full_rx_status_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_005_out_0_ready;                           // fifo_full_rx_status_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_005:out_0_ready
	wire    [0:0] avalon_st_adapter_005_out_0_error;                           // avalon_st_adapter_005:out_0_error -> fifo_full_rx_status_s1_agent:rdata_fifo_sink_error
	wire          fifo_empty_rx_status_s1_agent_rdata_fifo_out_valid;          // fifo_empty_rx_status_s1_agent_rdata_fifo:out_valid -> avalon_st_adapter_006:in_0_valid
	wire   [33:0] fifo_empty_rx_status_s1_agent_rdata_fifo_out_data;           // fifo_empty_rx_status_s1_agent_rdata_fifo:out_data -> avalon_st_adapter_006:in_0_data
	wire          fifo_empty_rx_status_s1_agent_rdata_fifo_out_ready;          // avalon_st_adapter_006:in_0_ready -> fifo_empty_rx_status_s1_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_006_out_0_valid;                           // avalon_st_adapter_006:out_0_valid -> fifo_empty_rx_status_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_006_out_0_data;                            // avalon_st_adapter_006:out_0_data -> fifo_empty_rx_status_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_006_out_0_ready;                           // fifo_empty_rx_status_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_006:out_0_ready
	wire    [0:0] avalon_st_adapter_006_out_0_error;                           // avalon_st_adapter_006:out_0_error -> fifo_empty_rx_status_s1_agent:rdata_fifo_sink_error
	wire          link_start_s1_agent_rdata_fifo_out_valid;                    // link_start_s1_agent_rdata_fifo:out_valid -> avalon_st_adapter_007:in_0_valid
	wire   [33:0] link_start_s1_agent_rdata_fifo_out_data;                     // link_start_s1_agent_rdata_fifo:out_data -> avalon_st_adapter_007:in_0_data
	wire          link_start_s1_agent_rdata_fifo_out_ready;                    // avalon_st_adapter_007:in_0_ready -> link_start_s1_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_007_out_0_valid;                           // avalon_st_adapter_007:out_0_valid -> link_start_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_007_out_0_data;                            // avalon_st_adapter_007:out_0_data -> link_start_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_007_out_0_ready;                           // link_start_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_007:out_0_ready
	wire    [0:0] avalon_st_adapter_007_out_0_error;                           // avalon_st_adapter_007:out_0_error -> link_start_s1_agent:rdata_fifo_sink_error
	wire          auto_start_s1_agent_rdata_fifo_out_valid;                    // auto_start_s1_agent_rdata_fifo:out_valid -> avalon_st_adapter_008:in_0_valid
	wire   [33:0] auto_start_s1_agent_rdata_fifo_out_data;                     // auto_start_s1_agent_rdata_fifo:out_data -> avalon_st_adapter_008:in_0_data
	wire          auto_start_s1_agent_rdata_fifo_out_ready;                    // avalon_st_adapter_008:in_0_ready -> auto_start_s1_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_008_out_0_valid;                           // avalon_st_adapter_008:out_0_valid -> auto_start_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_008_out_0_data;                            // avalon_st_adapter_008:out_0_data -> auto_start_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_008_out_0_ready;                           // auto_start_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_008:out_0_ready
	wire    [0:0] avalon_st_adapter_008_out_0_error;                           // avalon_st_adapter_008:out_0_error -> auto_start_s1_agent:rdata_fifo_sink_error
	wire          link_disable_s1_agent_rdata_fifo_out_valid;                  // link_disable_s1_agent_rdata_fifo:out_valid -> avalon_st_adapter_009:in_0_valid
	wire   [33:0] link_disable_s1_agent_rdata_fifo_out_data;                   // link_disable_s1_agent_rdata_fifo:out_data -> avalon_st_adapter_009:in_0_data
	wire          link_disable_s1_agent_rdata_fifo_out_ready;                  // avalon_st_adapter_009:in_0_ready -> link_disable_s1_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_009_out_0_valid;                           // avalon_st_adapter_009:out_0_valid -> link_disable_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_009_out_0_data;                            // avalon_st_adapter_009:out_0_data -> link_disable_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_009_out_0_ready;                           // link_disable_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_009:out_0_ready
	wire    [0:0] avalon_st_adapter_009_out_0_error;                           // avalon_st_adapter_009:out_0_error -> link_disable_s1_agent:rdata_fifo_sink_error
	wire          write_data_fifo_tx_s1_agent_rdata_fifo_out_valid;            // write_data_fifo_tx_s1_agent_rdata_fifo:out_valid -> avalon_st_adapter_010:in_0_valid
	wire   [33:0] write_data_fifo_tx_s1_agent_rdata_fifo_out_data;             // write_data_fifo_tx_s1_agent_rdata_fifo:out_data -> avalon_st_adapter_010:in_0_data
	wire          write_data_fifo_tx_s1_agent_rdata_fifo_out_ready;            // avalon_st_adapter_010:in_0_ready -> write_data_fifo_tx_s1_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_010_out_0_valid;                           // avalon_st_adapter_010:out_0_valid -> write_data_fifo_tx_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_010_out_0_data;                            // avalon_st_adapter_010:out_0_data -> write_data_fifo_tx_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_010_out_0_ready;                           // write_data_fifo_tx_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_010:out_0_ready
	wire    [0:0] avalon_st_adapter_010_out_0_error;                           // avalon_st_adapter_010:out_0_error -> write_data_fifo_tx_s1_agent:rdata_fifo_sink_error
	wire          write_en_tx_s1_agent_rdata_fifo_out_valid;                   // write_en_tx_s1_agent_rdata_fifo:out_valid -> avalon_st_adapter_011:in_0_valid
	wire   [33:0] write_en_tx_s1_agent_rdata_fifo_out_data;                    // write_en_tx_s1_agent_rdata_fifo:out_data -> avalon_st_adapter_011:in_0_data
	wire          write_en_tx_s1_agent_rdata_fifo_out_ready;                   // avalon_st_adapter_011:in_0_ready -> write_en_tx_s1_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_011_out_0_valid;                           // avalon_st_adapter_011:out_0_valid -> write_en_tx_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_011_out_0_data;                            // avalon_st_adapter_011:out_0_data -> write_en_tx_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_011_out_0_ready;                           // write_en_tx_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_011:out_0_ready
	wire    [0:0] avalon_st_adapter_011_out_0_error;                           // avalon_st_adapter_011:out_0_error -> write_en_tx_s1_agent:rdata_fifo_sink_error
	wire          fifo_full_tx_status_s1_agent_rdata_fifo_out_valid;           // fifo_full_tx_status_s1_agent_rdata_fifo:out_valid -> avalon_st_adapter_012:in_0_valid
	wire   [33:0] fifo_full_tx_status_s1_agent_rdata_fifo_out_data;            // fifo_full_tx_status_s1_agent_rdata_fifo:out_data -> avalon_st_adapter_012:in_0_data
	wire          fifo_full_tx_status_s1_agent_rdata_fifo_out_ready;           // avalon_st_adapter_012:in_0_ready -> fifo_full_tx_status_s1_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_012_out_0_valid;                           // avalon_st_adapter_012:out_0_valid -> fifo_full_tx_status_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_012_out_0_data;                            // avalon_st_adapter_012:out_0_data -> fifo_full_tx_status_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_012_out_0_ready;                           // fifo_full_tx_status_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_012:out_0_ready
	wire    [0:0] avalon_st_adapter_012_out_0_error;                           // avalon_st_adapter_012:out_0_error -> fifo_full_tx_status_s1_agent:rdata_fifo_sink_error
	wire          fifo_empty_tx_status_s1_agent_rdata_fifo_out_valid;          // fifo_empty_tx_status_s1_agent_rdata_fifo:out_valid -> avalon_st_adapter_013:in_0_valid
	wire   [33:0] fifo_empty_tx_status_s1_agent_rdata_fifo_out_data;           // fifo_empty_tx_status_s1_agent_rdata_fifo:out_data -> avalon_st_adapter_013:in_0_data
	wire          fifo_empty_tx_status_s1_agent_rdata_fifo_out_ready;          // avalon_st_adapter_013:in_0_ready -> fifo_empty_tx_status_s1_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_013_out_0_valid;                           // avalon_st_adapter_013:out_0_valid -> fifo_empty_tx_status_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_013_out_0_data;                            // avalon_st_adapter_013:out_0_data -> fifo_empty_tx_status_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_013_out_0_ready;                           // fifo_empty_tx_status_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_013:out_0_ready
	wire    [0:0] avalon_st_adapter_013_out_0_error;                           // avalon_st_adapter_013:out_0_error -> fifo_empty_tx_status_s1_agent:rdata_fifo_sink_error
	wire          timecode_tx_data_s1_agent_rdata_fifo_out_valid;              // timecode_tx_data_s1_agent_rdata_fifo:out_valid -> avalon_st_adapter_014:in_0_valid
	wire   [33:0] timecode_tx_data_s1_agent_rdata_fifo_out_data;               // timecode_tx_data_s1_agent_rdata_fifo:out_data -> avalon_st_adapter_014:in_0_data
	wire          timecode_tx_data_s1_agent_rdata_fifo_out_ready;              // avalon_st_adapter_014:in_0_ready -> timecode_tx_data_s1_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_014_out_0_valid;                           // avalon_st_adapter_014:out_0_valid -> timecode_tx_data_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_014_out_0_data;                            // avalon_st_adapter_014:out_0_data -> timecode_tx_data_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_014_out_0_ready;                           // timecode_tx_data_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_014:out_0_ready
	wire    [0:0] avalon_st_adapter_014_out_0_error;                           // avalon_st_adapter_014:out_0_error -> timecode_tx_data_s1_agent:rdata_fifo_sink_error
	wire          timecode_tx_enable_s1_agent_rdata_fifo_out_valid;            // timecode_tx_enable_s1_agent_rdata_fifo:out_valid -> avalon_st_adapter_015:in_0_valid
	wire   [33:0] timecode_tx_enable_s1_agent_rdata_fifo_out_data;             // timecode_tx_enable_s1_agent_rdata_fifo:out_data -> avalon_st_adapter_015:in_0_data
	wire          timecode_tx_enable_s1_agent_rdata_fifo_out_ready;            // avalon_st_adapter_015:in_0_ready -> timecode_tx_enable_s1_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_015_out_0_valid;                           // avalon_st_adapter_015:out_0_valid -> timecode_tx_enable_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_015_out_0_data;                            // avalon_st_adapter_015:out_0_data -> timecode_tx_enable_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_015_out_0_ready;                           // timecode_tx_enable_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_015:out_0_ready
	wire    [0:0] avalon_st_adapter_015_out_0_error;                           // avalon_st_adapter_015:out_0_error -> timecode_tx_enable_s1_agent:rdata_fifo_sink_error
	wire          timecode_tx_ready_s1_agent_rdata_fifo_out_valid;             // timecode_tx_ready_s1_agent_rdata_fifo:out_valid -> avalon_st_adapter_016:in_0_valid
	wire   [33:0] timecode_tx_ready_s1_agent_rdata_fifo_out_data;              // timecode_tx_ready_s1_agent_rdata_fifo:out_data -> avalon_st_adapter_016:in_0_data
	wire          timecode_tx_ready_s1_agent_rdata_fifo_out_ready;             // avalon_st_adapter_016:in_0_ready -> timecode_tx_ready_s1_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_016_out_0_valid;                           // avalon_st_adapter_016:out_0_valid -> timecode_tx_ready_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_016_out_0_data;                            // avalon_st_adapter_016:out_0_data -> timecode_tx_ready_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_016_out_0_ready;                           // timecode_tx_ready_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_016:out_0_ready
	wire    [0:0] avalon_st_adapter_016_out_0_error;                           // avalon_st_adapter_016:out_0_error -> timecode_tx_ready_s1_agent:rdata_fifo_sink_error
	wire          data_info_s1_agent_rdata_fifo_out_valid;                     // data_info_s1_agent_rdata_fifo:out_valid -> avalon_st_adapter_017:in_0_valid
	wire   [33:0] data_info_s1_agent_rdata_fifo_out_data;                      // data_info_s1_agent_rdata_fifo:out_data -> avalon_st_adapter_017:in_0_data
	wire          data_info_s1_agent_rdata_fifo_out_ready;                     // avalon_st_adapter_017:in_0_ready -> data_info_s1_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_017_out_0_valid;                           // avalon_st_adapter_017:out_0_valid -> data_info_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_017_out_0_data;                            // avalon_st_adapter_017:out_0_data -> data_info_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_017_out_0_ready;                           // data_info_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_017:out_0_ready
	wire    [0:0] avalon_st_adapter_017_out_0_error;                           // avalon_st_adapter_017:out_0_error -> data_info_s1_agent:rdata_fifo_sink_error
	wire          clock_sel_s1_agent_rdata_fifo_out_valid;                     // clock_sel_s1_agent_rdata_fifo:out_valid -> avalon_st_adapter_018:in_0_valid
	wire   [33:0] clock_sel_s1_agent_rdata_fifo_out_data;                      // clock_sel_s1_agent_rdata_fifo:out_data -> avalon_st_adapter_018:in_0_data
	wire          clock_sel_s1_agent_rdata_fifo_out_ready;                     // avalon_st_adapter_018:in_0_ready -> clock_sel_s1_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_018_out_0_valid;                           // avalon_st_adapter_018:out_0_valid -> clock_sel_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_018_out_0_data;                            // avalon_st_adapter_018:out_0_data -> clock_sel_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_018_out_0_ready;                           // clock_sel_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_018:out_0_ready
	wire    [0:0] avalon_st_adapter_018_out_0_error;                           // avalon_st_adapter_018:out_0_error -> clock_sel_s1_agent:rdata_fifo_sink_error
	wire          fsm_info_s1_agent_rdata_fifo_out_valid;                      // fsm_info_s1_agent_rdata_fifo:out_valid -> avalon_st_adapter_019:in_0_valid
	wire   [33:0] fsm_info_s1_agent_rdata_fifo_out_data;                       // fsm_info_s1_agent_rdata_fifo:out_data -> avalon_st_adapter_019:in_0_data
	wire          fsm_info_s1_agent_rdata_fifo_out_ready;                      // avalon_st_adapter_019:in_0_ready -> fsm_info_s1_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_019_out_0_valid;                           // avalon_st_adapter_019:out_0_valid -> fsm_info_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_019_out_0_data;                            // avalon_st_adapter_019:out_0_data -> fsm_info_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_019_out_0_ready;                           // fsm_info_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_019:out_0_ready
	wire    [0:0] avalon_st_adapter_019_out_0_error;                           // avalon_st_adapter_019:out_0_error -> fsm_info_s1_agent:rdata_fifo_sink_error
	wire          counter_tx_fifo_s1_agent_rdata_fifo_out_valid;               // counter_tx_fifo_s1_agent_rdata_fifo:out_valid -> avalon_st_adapter_020:in_0_valid
	wire   [33:0] counter_tx_fifo_s1_agent_rdata_fifo_out_data;                // counter_tx_fifo_s1_agent_rdata_fifo:out_data -> avalon_st_adapter_020:in_0_data
	wire          counter_tx_fifo_s1_agent_rdata_fifo_out_ready;               // avalon_st_adapter_020:in_0_ready -> counter_tx_fifo_s1_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_020_out_0_valid;                           // avalon_st_adapter_020:out_0_valid -> counter_tx_fifo_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_020_out_0_data;                            // avalon_st_adapter_020:out_0_data -> counter_tx_fifo_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_020_out_0_ready;                           // counter_tx_fifo_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_020:out_0_ready
	wire    [0:0] avalon_st_adapter_020_out_0_error;                           // avalon_st_adapter_020:out_0_error -> counter_tx_fifo_s1_agent:rdata_fifo_sink_error
	wire          counter_rx_fifo_s1_agent_rdata_fifo_out_valid;               // counter_rx_fifo_s1_agent_rdata_fifo:out_valid -> avalon_st_adapter_021:in_0_valid
	wire   [33:0] counter_rx_fifo_s1_agent_rdata_fifo_out_data;                // counter_rx_fifo_s1_agent_rdata_fifo:out_data -> avalon_st_adapter_021:in_0_data
	wire          counter_rx_fifo_s1_agent_rdata_fifo_out_ready;               // avalon_st_adapter_021:in_0_ready -> counter_rx_fifo_s1_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_021_out_0_valid;                           // avalon_st_adapter_021:out_0_valid -> counter_rx_fifo_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_021_out_0_data;                            // avalon_st_adapter_021:out_0_data -> counter_rx_fifo_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_021_out_0_ready;                           // counter_rx_fifo_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_021:out_0_ready
	wire    [0:0] avalon_st_adapter_021_out_0_error;                           // avalon_st_adapter_021:out_0_error -> counter_rx_fifo_s1_agent:rdata_fifo_sink_error
 
	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (30),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) led_pio_test_s1_translator (
		.clk                    (clk_0_clk_clk),                                  //                      clk.clk
		.reset                  (led_pio_test_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (led_pio_test_s1_agent_m0_address),               // avalon_universal_slave_0.address
		.uav_burstcount         (led_pio_test_s1_agent_m0_burstcount),            //                         .burstcount
		.uav_read               (led_pio_test_s1_agent_m0_read),                  //                         .read
		.uav_write              (led_pio_test_s1_agent_m0_write),                 //                         .write
		.uav_waitrequest        (led_pio_test_s1_agent_m0_waitrequest),           //                         .waitrequest
		.uav_readdatavalid      (led_pio_test_s1_agent_m0_readdatavalid),         //                         .readdatavalid
		.uav_byteenable         (led_pio_test_s1_agent_m0_byteenable),            //                         .byteenable
		.uav_readdata           (led_pio_test_s1_agent_m0_readdata),              //                         .readdata
		.uav_writedata          (led_pio_test_s1_agent_m0_writedata),             //                         .writedata
		.uav_lock               (led_pio_test_s1_agent_m0_lock),                  //                         .lock
		.uav_debugaccess        (led_pio_test_s1_agent_m0_debugaccess),           //                         .debugaccess
		.av_address             (led_pio_test_s1_address),                        //      avalon_anti_slave_0.address
		.av_write               (led_pio_test_s1_write),                          //                         .write
		.av_readdata            (led_pio_test_s1_readdata),                       //                         .readdata
		.av_writedata           (led_pio_test_s1_writedata),                      //                         .writedata
		.av_chipselect          (led_pio_test_s1_chipselect),                     //                         .chipselect
		.av_read                (),                                               //              (terminated)
		.av_begintransfer       (),                                               //              (terminated)
		.av_beginbursttransfer  (),                                               //              (terminated)
		.av_burstcount          (),                                               //              (terminated)
		.av_byteenable          (),                                               //              (terminated)
		.av_readdatavalid       (1'b0),                                           //              (terminated)
		.av_waitrequest         (1'b0),                                           //              (terminated)
		.av_writebyteenable     (),                                               //              (terminated)
		.av_lock                (),                                               //              (terminated)
		.av_clken               (),                                               //              (terminated)
		.uav_clken              (1'b0),                                           //              (terminated)
		.av_debugaccess         (),                                               //              (terminated)
		.av_outputenable        (),                                               //              (terminated)
		.uav_response           (),                                               //              (terminated)
		.av_response            (2'b00),                                          //              (terminated)
		.uav_writeresponsevalid (),                                               //              (terminated)
		.av_writeresponsevalid  (1'b0)                                            //              (terminated)
	);
 
	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (30),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) timecode_rx_s1_translator (
		.clk                    (clk_0_clk_clk),                                  //                      clk.clk
		.reset                  (led_pio_test_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (timecode_rx_s1_agent_m0_address),                // avalon_universal_slave_0.address
		.uav_burstcount         (timecode_rx_s1_agent_m0_burstcount),             //                         .burstcount
		.uav_read               (timecode_rx_s1_agent_m0_read),                   //                         .read
		.uav_write              (timecode_rx_s1_agent_m0_write),                  //                         .write
		.uav_waitrequest        (timecode_rx_s1_agent_m0_waitrequest),            //                         .waitrequest
		.uav_readdatavalid      (timecode_rx_s1_agent_m0_readdatavalid),          //                         .readdatavalid
		.uav_byteenable         (timecode_rx_s1_agent_m0_byteenable),             //                         .byteenable
		.uav_readdata           (timecode_rx_s1_agent_m0_readdata),               //                         .readdata
		.uav_writedata          (timecode_rx_s1_agent_m0_writedata),              //                         .writedata
		.uav_lock               (timecode_rx_s1_agent_m0_lock),                   //                         .lock
		.uav_debugaccess        (timecode_rx_s1_agent_m0_debugaccess),            //                         .debugaccess
		.av_address             (timecode_rx_s1_address),                         //      avalon_anti_slave_0.address
		.av_readdata            (timecode_rx_s1_readdata),                        //                         .readdata
		.av_write               (),                                               //              (terminated)
		.av_read                (),                                               //              (terminated)
		.av_writedata           (),                                               //              (terminated)
		.av_begintransfer       (),                                               //              (terminated)
		.av_beginbursttransfer  (),                                               //              (terminated)
		.av_burstcount          (),                                               //              (terminated)
		.av_byteenable          (),                                               //              (terminated)
		.av_readdatavalid       (1'b0),                                           //              (terminated)
		.av_waitrequest         (1'b0),                                           //              (terminated)
		.av_writebyteenable     (),                                               //              (terminated)
		.av_lock                (),                                               //              (terminated)
		.av_chipselect          (),                                               //              (terminated)
		.av_clken               (),                                               //              (terminated)
		.uav_clken              (1'b0),                                           //              (terminated)
		.av_debugaccess         (),                                               //              (terminated)
		.av_outputenable        (),                                               //              (terminated)
		.uav_response           (),                                               //              (terminated)
		.av_response            (2'b00),                                          //              (terminated)
		.uav_writeresponsevalid (),                                               //              (terminated)
		.av_writeresponsevalid  (1'b0)                                            //              (terminated)
	);
 
	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (30),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) timecode_ready_rx_s1_translator (
		.clk                    (clk_0_clk_clk),                                  //                      clk.clk
		.reset                  (led_pio_test_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (timecode_ready_rx_s1_agent_m0_address),          // avalon_universal_slave_0.address
		.uav_burstcount         (timecode_ready_rx_s1_agent_m0_burstcount),       //                         .burstcount
		.uav_read               (timecode_ready_rx_s1_agent_m0_read),             //                         .read
		.uav_write              (timecode_ready_rx_s1_agent_m0_write),            //                         .write
		.uav_waitrequest        (timecode_ready_rx_s1_agent_m0_waitrequest),      //                         .waitrequest
		.uav_readdatavalid      (timecode_ready_rx_s1_agent_m0_readdatavalid),    //                         .readdatavalid
		.uav_byteenable         (timecode_ready_rx_s1_agent_m0_byteenable),       //                         .byteenable
		.uav_readdata           (timecode_ready_rx_s1_agent_m0_readdata),         //                         .readdata
		.uav_writedata          (timecode_ready_rx_s1_agent_m0_writedata),        //                         .writedata
		.uav_lock               (timecode_ready_rx_s1_agent_m0_lock),             //                         .lock
		.uav_debugaccess        (timecode_ready_rx_s1_agent_m0_debugaccess),      //                         .debugaccess
		.av_address             (timecode_ready_rx_s1_address),                   //      avalon_anti_slave_0.address
		.av_readdata            (timecode_ready_rx_s1_readdata),                  //                         .readdata
		.av_write               (),                                               //              (terminated)
		.av_read                (),                                               //              (terminated)
		.av_writedata           (),                                               //              (terminated)
		.av_begintransfer       (),                                               //              (terminated)
		.av_beginbursttransfer  (),                                               //              (terminated)
		.av_burstcount          (),                                               //              (terminated)
		.av_byteenable          (),                                               //              (terminated)
		.av_readdatavalid       (1'b0),                                           //              (terminated)
		.av_waitrequest         (1'b0),                                           //              (terminated)
		.av_writebyteenable     (),                                               //              (terminated)
		.av_lock                (),                                               //              (terminated)
		.av_chipselect          (),                                               //              (terminated)
		.av_clken               (),                                               //              (terminated)
		.uav_clken              (1'b0),                                           //              (terminated)
		.av_debugaccess         (),                                               //              (terminated)
		.av_outputenable        (),                                               //              (terminated)
		.uav_response           (),                                               //              (terminated)
		.av_response            (2'b00),                                          //              (terminated)
		.uav_writeresponsevalid (),                                               //              (terminated)
		.av_writeresponsevalid  (1'b0)                                            //              (terminated)
	);
 
	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (30),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) data_flag_rx_s1_translator (
		.clk                    (clk_0_clk_clk),                                  //                      clk.clk
		.reset                  (led_pio_test_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (data_flag_rx_s1_agent_m0_address),               // avalon_universal_slave_0.address
		.uav_burstcount         (data_flag_rx_s1_agent_m0_burstcount),            //                         .burstcount
		.uav_read               (data_flag_rx_s1_agent_m0_read),                  //                         .read
		.uav_write              (data_flag_rx_s1_agent_m0_write),                 //                         .write
		.uav_waitrequest        (data_flag_rx_s1_agent_m0_waitrequest),           //                         .waitrequest
		.uav_readdatavalid      (data_flag_rx_s1_agent_m0_readdatavalid),         //                         .readdatavalid
		.uav_byteenable         (data_flag_rx_s1_agent_m0_byteenable),            //                         .byteenable
		.uav_readdata           (data_flag_rx_s1_agent_m0_readdata),              //                         .readdata
		.uav_writedata          (data_flag_rx_s1_agent_m0_writedata),             //                         .writedata
		.uav_lock               (data_flag_rx_s1_agent_m0_lock),                  //                         .lock
		.uav_debugaccess        (data_flag_rx_s1_agent_m0_debugaccess),           //                         .debugaccess
		.av_address             (data_flag_rx_s1_address),                        //      avalon_anti_slave_0.address
		.av_readdata            (data_flag_rx_s1_readdata),                       //                         .readdata
		.av_write               (),                                               //              (terminated)
		.av_read                (),                                               //              (terminated)
		.av_writedata           (),                                               //              (terminated)
		.av_begintransfer       (),                                               //              (terminated)
		.av_beginbursttransfer  (),                                               //              (terminated)
		.av_burstcount          (),                                               //              (terminated)
		.av_byteenable          (),                                               //              (terminated)
		.av_readdatavalid       (1'b0),                                           //              (terminated)
		.av_waitrequest         (1'b0),                                           //              (terminated)
		.av_writebyteenable     (),                                               //              (terminated)
		.av_lock                (),                                               //              (terminated)
		.av_chipselect          (),                                               //              (terminated)
		.av_clken               (),                                               //              (terminated)
		.uav_clken              (1'b0),                                           //              (terminated)
		.av_debugaccess         (),                                               //              (terminated)
		.av_outputenable        (),                                               //              (terminated)
		.uav_response           (),                                               //              (terminated)
		.av_response            (2'b00),                                          //              (terminated)
		.uav_writeresponsevalid (),                                               //              (terminated)
		.av_writeresponsevalid  (1'b0)                                            //              (terminated)
	);
 
	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (30),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) data_read_en_rx_s1_translator (
		.clk                    (clk_0_clk_clk),                                  //                      clk.clk
		.reset                  (led_pio_test_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (data_read_en_rx_s1_agent_m0_address),            // avalon_universal_slave_0.address
		.uav_burstcount         (data_read_en_rx_s1_agent_m0_burstcount),         //                         .burstcount
		.uav_read               (data_read_en_rx_s1_agent_m0_read),               //                         .read
		.uav_write              (data_read_en_rx_s1_agent_m0_write),              //                         .write
		.uav_waitrequest        (data_read_en_rx_s1_agent_m0_waitrequest),        //                         .waitrequest
		.uav_readdatavalid      (data_read_en_rx_s1_agent_m0_readdatavalid),      //                         .readdatavalid
		.uav_byteenable         (data_read_en_rx_s1_agent_m0_byteenable),         //                         .byteenable
		.uav_readdata           (data_read_en_rx_s1_agent_m0_readdata),           //                         .readdata
		.uav_writedata          (data_read_en_rx_s1_agent_m0_writedata),          //                         .writedata
		.uav_lock               (data_read_en_rx_s1_agent_m0_lock),               //                         .lock
		.uav_debugaccess        (data_read_en_rx_s1_agent_m0_debugaccess),        //                         .debugaccess
		.av_address             (data_read_en_rx_s1_address),                     //      avalon_anti_slave_0.address
		.av_write               (data_read_en_rx_s1_write),                       //                         .write
		.av_readdata            (data_read_en_rx_s1_readdata),                    //                         .readdata
		.av_writedata           (data_read_en_rx_s1_writedata),                   //                         .writedata
		.av_chipselect          (data_read_en_rx_s1_chipselect),                  //                         .chipselect
		.av_read                (),                                               //              (terminated)
		.av_begintransfer       (),                                               //              (terminated)
		.av_beginbursttransfer  (),                                               //              (terminated)
		.av_burstcount          (),                                               //              (terminated)
		.av_byteenable          (),                                               //              (terminated)
		.av_readdatavalid       (1'b0),                                           //              (terminated)
		.av_waitrequest         (1'b0),                                           //              (terminated)
		.av_writebyteenable     (),                                               //              (terminated)
		.av_lock                (),                                               //              (terminated)
		.av_clken               (),                                               //              (terminated)
		.uav_clken              (1'b0),                                           //              (terminated)
		.av_debugaccess         (),                                               //              (terminated)
		.av_outputenable        (),                                               //              (terminated)
		.uav_response           (),                                               //              (terminated)
		.av_response            (2'b00),                                          //              (terminated)
		.uav_writeresponsevalid (),                                               //              (terminated)
		.av_writeresponsevalid  (1'b0)                                            //              (terminated)
	);
 
	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (30),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) fifo_full_rx_status_s1_translator (
		.clk                    (clk_0_clk_clk),                                  //                      clk.clk
		.reset                  (led_pio_test_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (fifo_full_rx_status_s1_agent_m0_address),        // avalon_universal_slave_0.address
		.uav_burstcount         (fifo_full_rx_status_s1_agent_m0_burstcount),     //                         .burstcount
		.uav_read               (fifo_full_rx_status_s1_agent_m0_read),           //                         .read
		.uav_write              (fifo_full_rx_status_s1_agent_m0_write),          //                         .write
		.uav_waitrequest        (fifo_full_rx_status_s1_agent_m0_waitrequest),    //                         .waitrequest
		.uav_readdatavalid      (fifo_full_rx_status_s1_agent_m0_readdatavalid),  //                         .readdatavalid
		.uav_byteenable         (fifo_full_rx_status_s1_agent_m0_byteenable),     //                         .byteenable
		.uav_readdata           (fifo_full_rx_status_s1_agent_m0_readdata),       //                         .readdata
		.uav_writedata          (fifo_full_rx_status_s1_agent_m0_writedata),      //                         .writedata
		.uav_lock               (fifo_full_rx_status_s1_agent_m0_lock),           //                         .lock
		.uav_debugaccess        (fifo_full_rx_status_s1_agent_m0_debugaccess),    //                         .debugaccess
		.av_address             (fifo_full_rx_status_s1_address),                 //      avalon_anti_slave_0.address
		.av_readdata            (fifo_full_rx_status_s1_readdata),                //                         .readdata
		.av_write               (),                                               //              (terminated)
		.av_read                (),                                               //              (terminated)
		.av_writedata           (),                                               //              (terminated)
		.av_begintransfer       (),                                               //              (terminated)
		.av_beginbursttransfer  (),                                               //              (terminated)
		.av_burstcount          (),                                               //              (terminated)
		.av_byteenable          (),                                               //              (terminated)
		.av_readdatavalid       (1'b0),                                           //              (terminated)
		.av_waitrequest         (1'b0),                                           //              (terminated)
		.av_writebyteenable     (),                                               //              (terminated)
		.av_lock                (),                                               //              (terminated)
		.av_chipselect          (),                                               //              (terminated)
		.av_clken               (),                                               //              (terminated)
		.uav_clken              (1'b0),                                           //              (terminated)
		.av_debugaccess         (),                                               //              (terminated)
		.av_outputenable        (),                                               //              (terminated)
		.uav_response           (),                                               //              (terminated)
		.av_response            (2'b00),                                          //              (terminated)
		.uav_writeresponsevalid (),                                               //              (terminated)
		.av_writeresponsevalid  (1'b0)                                            //              (terminated)
	);
 
	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (30),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) fifo_empty_rx_status_s1_translator (
		.clk                    (clk_0_clk_clk),                                  //                      clk.clk
		.reset                  (led_pio_test_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (fifo_empty_rx_status_s1_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount         (fifo_empty_rx_status_s1_agent_m0_burstcount),    //                         .burstcount
		.uav_read               (fifo_empty_rx_status_s1_agent_m0_read),          //                         .read
		.uav_write              (fifo_empty_rx_status_s1_agent_m0_write),         //                         .write
		.uav_waitrequest        (fifo_empty_rx_status_s1_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid      (fifo_empty_rx_status_s1_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable         (fifo_empty_rx_status_s1_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata           (fifo_empty_rx_status_s1_agent_m0_readdata),      //                         .readdata
		.uav_writedata          (fifo_empty_rx_status_s1_agent_m0_writedata),     //                         .writedata
		.uav_lock               (fifo_empty_rx_status_s1_agent_m0_lock),          //                         .lock
		.uav_debugaccess        (fifo_empty_rx_status_s1_agent_m0_debugaccess),   //                         .debugaccess
		.av_address             (fifo_empty_rx_status_s1_address),                //      avalon_anti_slave_0.address
		.av_readdata            (fifo_empty_rx_status_s1_readdata),               //                         .readdata
		.av_write               (),                                               //              (terminated)
		.av_read                (),                                               //              (terminated)
		.av_writedata           (),                                               //              (terminated)
		.av_begintransfer       (),                                               //              (terminated)
		.av_beginbursttransfer  (),                                               //              (terminated)
		.av_burstcount          (),                                               //              (terminated)
		.av_byteenable          (),                                               //              (terminated)
		.av_readdatavalid       (1'b0),                                           //              (terminated)
		.av_waitrequest         (1'b0),                                           //              (terminated)
		.av_writebyteenable     (),                                               //              (terminated)
		.av_lock                (),                                               //              (terminated)
		.av_chipselect          (),                                               //              (terminated)
		.av_clken               (),                                               //              (terminated)
		.uav_clken              (1'b0),                                           //              (terminated)
		.av_debugaccess         (),                                               //              (terminated)
		.av_outputenable        (),                                               //              (terminated)
		.uav_response           (),                                               //              (terminated)
		.av_response            (2'b00),                                          //              (terminated)
		.uav_writeresponsevalid (),                                               //              (terminated)
		.av_writeresponsevalid  (1'b0)                                            //              (terminated)
	);
 
	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (30),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) link_start_s1_translator (
		.clk                    (clk_0_clk_clk),                                  //                      clk.clk
		.reset                  (led_pio_test_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (link_start_s1_agent_m0_address),                 // avalon_universal_slave_0.address
		.uav_burstcount         (link_start_s1_agent_m0_burstcount),              //                         .burstcount
		.uav_read               (link_start_s1_agent_m0_read),                    //                         .read
		.uav_write              (link_start_s1_agent_m0_write),                   //                         .write
		.uav_waitrequest        (link_start_s1_agent_m0_waitrequest),             //                         .waitrequest
		.uav_readdatavalid      (link_start_s1_agent_m0_readdatavalid),           //                         .readdatavalid
		.uav_byteenable         (link_start_s1_agent_m0_byteenable),              //                         .byteenable
		.uav_readdata           (link_start_s1_agent_m0_readdata),                //                         .readdata
		.uav_writedata          (link_start_s1_agent_m0_writedata),               //                         .writedata
		.uav_lock               (link_start_s1_agent_m0_lock),                    //                         .lock
		.uav_debugaccess        (link_start_s1_agent_m0_debugaccess),             //                         .debugaccess
		.av_address             (link_start_s1_address),                          //      avalon_anti_slave_0.address
		.av_write               (link_start_s1_write),                            //                         .write
		.av_readdata            (link_start_s1_readdata),                         //                         .readdata
		.av_writedata           (link_start_s1_writedata),                        //                         .writedata
		.av_chipselect          (link_start_s1_chipselect),                       //                         .chipselect
		.av_read                (),                                               //              (terminated)
		.av_begintransfer       (),                                               //              (terminated)
		.av_beginbursttransfer  (),                                               //              (terminated)
		.av_burstcount          (),                                               //              (terminated)
		.av_byteenable          (),                                               //              (terminated)
		.av_readdatavalid       (1'b0),                                           //              (terminated)
		.av_waitrequest         (1'b0),                                           //              (terminated)
		.av_writebyteenable     (),                                               //              (terminated)
		.av_lock                (),                                               //              (terminated)
		.av_clken               (),                                               //              (terminated)
		.uav_clken              (1'b0),                                           //              (terminated)
		.av_debugaccess         (),                                               //              (terminated)
		.av_outputenable        (),                                               //              (terminated)
		.uav_response           (),                                               //              (terminated)
		.av_response            (2'b00),                                          //              (terminated)
		.uav_writeresponsevalid (),                                               //              (terminated)
		.av_writeresponsevalid  (1'b0)                                            //              (terminated)
	);
 
	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (30),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) auto_start_s1_translator (
		.clk                    (clk_0_clk_clk),                                  //                      clk.clk
		.reset                  (led_pio_test_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (auto_start_s1_agent_m0_address),                 // avalon_universal_slave_0.address
		.uav_burstcount         (auto_start_s1_agent_m0_burstcount),              //                         .burstcount
		.uav_read               (auto_start_s1_agent_m0_read),                    //                         .read
		.uav_write              (auto_start_s1_agent_m0_write),                   //                         .write
		.uav_waitrequest        (auto_start_s1_agent_m0_waitrequest),             //                         .waitrequest
		.uav_readdatavalid      (auto_start_s1_agent_m0_readdatavalid),           //                         .readdatavalid
		.uav_byteenable         (auto_start_s1_agent_m0_byteenable),              //                         .byteenable
		.uav_readdata           (auto_start_s1_agent_m0_readdata),                //                         .readdata
		.uav_writedata          (auto_start_s1_agent_m0_writedata),               //                         .writedata
		.uav_lock               (auto_start_s1_agent_m0_lock),                    //                         .lock
		.uav_debugaccess        (auto_start_s1_agent_m0_debugaccess),             //                         .debugaccess
		.av_address             (auto_start_s1_address),                          //      avalon_anti_slave_0.address
		.av_write               (auto_start_s1_write),                            //                         .write
		.av_readdata            (auto_start_s1_readdata),                         //                         .readdata
		.av_writedata           (auto_start_s1_writedata),                        //                         .writedata
		.av_chipselect          (auto_start_s1_chipselect),                       //                         .chipselect
		.av_read                (),                                               //              (terminated)
		.av_begintransfer       (),                                               //              (terminated)
		.av_beginbursttransfer  (),                                               //              (terminated)
		.av_burstcount          (),                                               //              (terminated)
		.av_byteenable          (),                                               //              (terminated)
		.av_readdatavalid       (1'b0),                                           //              (terminated)
		.av_waitrequest         (1'b0),                                           //              (terminated)
		.av_writebyteenable     (),                                               //              (terminated)
		.av_lock                (),                                               //              (terminated)
		.av_clken               (),                                               //              (terminated)
		.uav_clken              (1'b0),                                           //              (terminated)
		.av_debugaccess         (),                                               //              (terminated)
		.av_outputenable        (),                                               //              (terminated)
		.uav_response           (),                                               //              (terminated)
		.av_response            (2'b00),                                          //              (terminated)
		.uav_writeresponsevalid (),                                               //              (terminated)
		.av_writeresponsevalid  (1'b0)                                            //              (terminated)
	);
 
	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (30),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) link_disable_s1_translator (
		.clk                    (clk_0_clk_clk),                                  //                      clk.clk
		.reset                  (led_pio_test_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (link_disable_s1_agent_m0_address),               // avalon_universal_slave_0.address
		.uav_burstcount         (link_disable_s1_agent_m0_burstcount),            //                         .burstcount
		.uav_read               (link_disable_s1_agent_m0_read),                  //                         .read
		.uav_write              (link_disable_s1_agent_m0_write),                 //                         .write
		.uav_waitrequest        (link_disable_s1_agent_m0_waitrequest),           //                         .waitrequest
		.uav_readdatavalid      (link_disable_s1_agent_m0_readdatavalid),         //                         .readdatavalid
		.uav_byteenable         (link_disable_s1_agent_m0_byteenable),            //                         .byteenable
		.uav_readdata           (link_disable_s1_agent_m0_readdata),              //                         .readdata
		.uav_writedata          (link_disable_s1_agent_m0_writedata),             //                         .writedata
		.uav_lock               (link_disable_s1_agent_m0_lock),                  //                         .lock
		.uav_debugaccess        (link_disable_s1_agent_m0_debugaccess),           //                         .debugaccess
		.av_address             (link_disable_s1_address),                        //      avalon_anti_slave_0.address
		.av_write               (link_disable_s1_write),                          //                         .write
		.av_readdata            (link_disable_s1_readdata),                       //                         .readdata
		.av_writedata           (link_disable_s1_writedata),                      //                         .writedata
		.av_chipselect          (link_disable_s1_chipselect),                     //                         .chipselect
		.av_read                (),                                               //              (terminated)
		.av_begintransfer       (),                                               //              (terminated)
		.av_beginbursttransfer  (),                                               //              (terminated)
		.av_burstcount          (),                                               //              (terminated)
		.av_byteenable          (),                                               //              (terminated)
		.av_readdatavalid       (1'b0),                                           //              (terminated)
		.av_waitrequest         (1'b0),                                           //              (terminated)
		.av_writebyteenable     (),                                               //              (terminated)
		.av_lock                (),                                               //              (terminated)
		.av_clken               (),                                               //              (terminated)
		.uav_clken              (1'b0),                                           //              (terminated)
		.av_debugaccess         (),                                               //              (terminated)
		.av_outputenable        (),                                               //              (terminated)
		.uav_response           (),                                               //              (terminated)
		.av_response            (2'b00),                                          //              (terminated)
		.uav_writeresponsevalid (),                                               //              (terminated)
		.av_writeresponsevalid  (1'b0)                                            //              (terminated)
	);
 
	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (30),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) write_data_fifo_tx_s1_translator (
		.clk                    (clk_0_clk_clk),                                  //                      clk.clk
		.reset                  (led_pio_test_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (write_data_fifo_tx_s1_agent_m0_address),         // avalon_universal_slave_0.address
		.uav_burstcount         (write_data_fifo_tx_s1_agent_m0_burstcount),      //                         .burstcount
		.uav_read               (write_data_fifo_tx_s1_agent_m0_read),            //                         .read
		.uav_write              (write_data_fifo_tx_s1_agent_m0_write),           //                         .write
		.uav_waitrequest        (write_data_fifo_tx_s1_agent_m0_waitrequest),     //                         .waitrequest
		.uav_readdatavalid      (write_data_fifo_tx_s1_agent_m0_readdatavalid),   //                         .readdatavalid
		.uav_byteenable         (write_data_fifo_tx_s1_agent_m0_byteenable),      //                         .byteenable
		.uav_readdata           (write_data_fifo_tx_s1_agent_m0_readdata),        //                         .readdata
		.uav_writedata          (write_data_fifo_tx_s1_agent_m0_writedata),       //                         .writedata
		.uav_lock               (write_data_fifo_tx_s1_agent_m0_lock),            //                         .lock
		.uav_debugaccess        (write_data_fifo_tx_s1_agent_m0_debugaccess),     //                         .debugaccess
		.av_address             (write_data_fifo_tx_s1_address),                  //      avalon_anti_slave_0.address
		.av_write               (write_data_fifo_tx_s1_write),                    //                         .write
		.av_readdata            (write_data_fifo_tx_s1_readdata),                 //                         .readdata
		.av_writedata           (write_data_fifo_tx_s1_writedata),                //                         .writedata
		.av_chipselect          (write_data_fifo_tx_s1_chipselect),               //                         .chipselect
		.av_read                (),                                               //              (terminated)
		.av_begintransfer       (),                                               //              (terminated)
		.av_beginbursttransfer  (),                                               //              (terminated)
		.av_burstcount          (),                                               //              (terminated)
		.av_byteenable          (),                                               //              (terminated)
		.av_readdatavalid       (1'b0),                                           //              (terminated)
		.av_waitrequest         (1'b0),                                           //              (terminated)
		.av_writebyteenable     (),                                               //              (terminated)
		.av_lock                (),                                               //              (terminated)
		.av_clken               (),                                               //              (terminated)
		.uav_clken              (1'b0),                                           //              (terminated)
		.av_debugaccess         (),                                               //              (terminated)
		.av_outputenable        (),                                               //              (terminated)
		.uav_response           (),                                               //              (terminated)
		.av_response            (2'b00),                                          //              (terminated)
		.uav_writeresponsevalid (),                                               //              (terminated)
		.av_writeresponsevalid  (1'b0)                                            //              (terminated)
	);
 
	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (30),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) write_en_tx_s1_translator (
		.clk                    (clk_0_clk_clk),                                  //                      clk.clk
		.reset                  (led_pio_test_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (write_en_tx_s1_agent_m0_address),                // avalon_universal_slave_0.address
		.uav_burstcount         (write_en_tx_s1_agent_m0_burstcount),             //                         .burstcount
		.uav_read               (write_en_tx_s1_agent_m0_read),                   //                         .read
		.uav_write              (write_en_tx_s1_agent_m0_write),                  //                         .write
		.uav_waitrequest        (write_en_tx_s1_agent_m0_waitrequest),            //                         .waitrequest
		.uav_readdatavalid      (write_en_tx_s1_agent_m0_readdatavalid),          //                         .readdatavalid
		.uav_byteenable         (write_en_tx_s1_agent_m0_byteenable),             //                         .byteenable
		.uav_readdata           (write_en_tx_s1_agent_m0_readdata),               //                         .readdata
		.uav_writedata          (write_en_tx_s1_agent_m0_writedata),              //                         .writedata
		.uav_lock               (write_en_tx_s1_agent_m0_lock),                   //                         .lock
		.uav_debugaccess        (write_en_tx_s1_agent_m0_debugaccess),            //                         .debugaccess
		.av_address             (write_en_tx_s1_address),                         //      avalon_anti_slave_0.address
		.av_write               (write_en_tx_s1_write),                           //                         .write
		.av_readdata            (write_en_tx_s1_readdata),                        //                         .readdata
		.av_writedata           (write_en_tx_s1_writedata),                       //                         .writedata
		.av_chipselect          (write_en_tx_s1_chipselect),                      //                         .chipselect
		.av_read                (),                                               //              (terminated)
		.av_begintransfer       (),                                               //              (terminated)
		.av_beginbursttransfer  (),                                               //              (terminated)
		.av_burstcount          (),                                               //              (terminated)
		.av_byteenable          (),                                               //              (terminated)
		.av_readdatavalid       (1'b0),                                           //              (terminated)
		.av_waitrequest         (1'b0),                                           //              (terminated)
		.av_writebyteenable     (),                                               //              (terminated)
		.av_lock                (),                                               //              (terminated)
		.av_clken               (),                                               //              (terminated)
		.uav_clken              (1'b0),                                           //              (terminated)
		.av_debugaccess         (),                                               //              (terminated)
		.av_outputenable        (),                                               //              (terminated)
		.uav_response           (),                                               //              (terminated)
		.av_response            (2'b00),                                          //              (terminated)
		.uav_writeresponsevalid (),                                               //              (terminated)
		.av_writeresponsevalid  (1'b0)                                            //              (terminated)
	);
 
	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (30),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) fifo_full_tx_status_s1_translator (
		.clk                    (clk_0_clk_clk),                                  //                      clk.clk
		.reset                  (led_pio_test_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (fifo_full_tx_status_s1_agent_m0_address),        // avalon_universal_slave_0.address
		.uav_burstcount         (fifo_full_tx_status_s1_agent_m0_burstcount),     //                         .burstcount
		.uav_read               (fifo_full_tx_status_s1_agent_m0_read),           //                         .read
		.uav_write              (fifo_full_tx_status_s1_agent_m0_write),          //                         .write
		.uav_waitrequest        (fifo_full_tx_status_s1_agent_m0_waitrequest),    //                         .waitrequest
		.uav_readdatavalid      (fifo_full_tx_status_s1_agent_m0_readdatavalid),  //                         .readdatavalid
		.uav_byteenable         (fifo_full_tx_status_s1_agent_m0_byteenable),     //                         .byteenable
		.uav_readdata           (fifo_full_tx_status_s1_agent_m0_readdata),       //                         .readdata
		.uav_writedata          (fifo_full_tx_status_s1_agent_m0_writedata),      //                         .writedata
		.uav_lock               (fifo_full_tx_status_s1_agent_m0_lock),           //                         .lock
		.uav_debugaccess        (fifo_full_tx_status_s1_agent_m0_debugaccess),    //                         .debugaccess
		.av_address             (fifo_full_tx_status_s1_address),                 //      avalon_anti_slave_0.address
		.av_readdata            (fifo_full_tx_status_s1_readdata),                //                         .readdata
		.av_write               (),                                               //              (terminated)
		.av_read                (),                                               //              (terminated)
		.av_writedata           (),                                               //              (terminated)
		.av_begintransfer       (),                                               //              (terminated)
		.av_beginbursttransfer  (),                                               //              (terminated)
		.av_burstcount          (),                                               //              (terminated)
		.av_byteenable          (),                                               //              (terminated)
		.av_readdatavalid       (1'b0),                                           //              (terminated)
		.av_waitrequest         (1'b0),                                           //              (terminated)
		.av_writebyteenable     (),                                               //              (terminated)
		.av_lock                (),                                               //              (terminated)
		.av_chipselect          (),                                               //              (terminated)
		.av_clken               (),                                               //              (terminated)
		.uav_clken              (1'b0),                                           //              (terminated)
		.av_debugaccess         (),                                               //              (terminated)
		.av_outputenable        (),                                               //              (terminated)
		.uav_response           (),                                               //              (terminated)
		.av_response            (2'b00),                                          //              (terminated)
		.uav_writeresponsevalid (),                                               //              (terminated)
		.av_writeresponsevalid  (1'b0)                                            //              (terminated)
	);
 
	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (30),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) fifo_empty_tx_status_s1_translator (
		.clk                    (clk_0_clk_clk),                                  //                      clk.clk
		.reset                  (led_pio_test_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (fifo_empty_tx_status_s1_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount         (fifo_empty_tx_status_s1_agent_m0_burstcount),    //                         .burstcount
		.uav_read               (fifo_empty_tx_status_s1_agent_m0_read),          //                         .read
		.uav_write              (fifo_empty_tx_status_s1_agent_m0_write),         //                         .write
		.uav_waitrequest        (fifo_empty_tx_status_s1_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid      (fifo_empty_tx_status_s1_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable         (fifo_empty_tx_status_s1_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata           (fifo_empty_tx_status_s1_agent_m0_readdata),      //                         .readdata
		.uav_writedata          (fifo_empty_tx_status_s1_agent_m0_writedata),     //                         .writedata
		.uav_lock               (fifo_empty_tx_status_s1_agent_m0_lock),          //                         .lock
		.uav_debugaccess        (fifo_empty_tx_status_s1_agent_m0_debugaccess),   //                         .debugaccess
		.av_address             (fifo_empty_tx_status_s1_address),                //      avalon_anti_slave_0.address
		.av_readdata            (fifo_empty_tx_status_s1_readdata),               //                         .readdata
		.av_write               (),                                               //              (terminated)
		.av_read                (),                                               //              (terminated)
		.av_writedata           (),                                               //              (terminated)
		.av_begintransfer       (),                                               //              (terminated)
		.av_beginbursttransfer  (),                                               //              (terminated)
		.av_burstcount          (),                                               //              (terminated)
		.av_byteenable          (),                                               //              (terminated)
		.av_readdatavalid       (1'b0),                                           //              (terminated)
		.av_waitrequest         (1'b0),                                           //              (terminated)
		.av_writebyteenable     (),                                               //              (terminated)
		.av_lock                (),                                               //              (terminated)
		.av_chipselect          (),                                               //              (terminated)
		.av_clken               (),                                               //              (terminated)
		.uav_clken              (1'b0),                                           //              (terminated)
		.av_debugaccess         (),                                               //              (terminated)
		.av_outputenable        (),                                               //              (terminated)
		.uav_response           (),                                               //              (terminated)
		.av_response            (2'b00),                                          //              (terminated)
		.uav_writeresponsevalid (),                                               //              (terminated)
		.av_writeresponsevalid  (1'b0)                                            //              (terminated)
	);
 
	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (30),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) timecode_tx_data_s1_translator (
		.clk                    (clk_0_clk_clk),                                  //                      clk.clk
		.reset                  (led_pio_test_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (timecode_tx_data_s1_agent_m0_address),           // avalon_universal_slave_0.address
		.uav_burstcount         (timecode_tx_data_s1_agent_m0_burstcount),        //                         .burstcount
		.uav_read               (timecode_tx_data_s1_agent_m0_read),              //                         .read
		.uav_write              (timecode_tx_data_s1_agent_m0_write),             //                         .write
		.uav_waitrequest        (timecode_tx_data_s1_agent_m0_waitrequest),       //                         .waitrequest
		.uav_readdatavalid      (timecode_tx_data_s1_agent_m0_readdatavalid),     //                         .readdatavalid
		.uav_byteenable         (timecode_tx_data_s1_agent_m0_byteenable),        //                         .byteenable
		.uav_readdata           (timecode_tx_data_s1_agent_m0_readdata),          //                         .readdata
		.uav_writedata          (timecode_tx_data_s1_agent_m0_writedata),         //                         .writedata
		.uav_lock               (timecode_tx_data_s1_agent_m0_lock),              //                         .lock
		.uav_debugaccess        (timecode_tx_data_s1_agent_m0_debugaccess),       //                         .debugaccess
		.av_address             (timecode_tx_data_s1_address),                    //      avalon_anti_slave_0.address
		.av_write               (timecode_tx_data_s1_write),                      //                         .write
		.av_readdata            (timecode_tx_data_s1_readdata),                   //                         .readdata
		.av_writedata           (timecode_tx_data_s1_writedata),                  //                         .writedata
		.av_chipselect          (timecode_tx_data_s1_chipselect),                 //                         .chipselect
		.av_read                (),                                               //              (terminated)
		.av_begintransfer       (),                                               //              (terminated)
		.av_beginbursttransfer  (),                                               //              (terminated)
		.av_burstcount          (),                                               //              (terminated)
		.av_byteenable          (),                                               //              (terminated)
		.av_readdatavalid       (1'b0),                                           //              (terminated)
		.av_waitrequest         (1'b0),                                           //              (terminated)
		.av_writebyteenable     (),                                               //              (terminated)
		.av_lock                (),                                               //              (terminated)
		.av_clken               (),                                               //              (terminated)
		.uav_clken              (1'b0),                                           //              (terminated)
		.av_debugaccess         (),                                               //              (terminated)
		.av_outputenable        (),                                               //              (terminated)
		.uav_response           (),                                               //              (terminated)
		.av_response            (2'b00),                                          //              (terminated)
		.uav_writeresponsevalid (),                                               //              (terminated)
		.av_writeresponsevalid  (1'b0)                                            //              (terminated)
	);
 
	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (30),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) timecode_tx_enable_s1_translator (
		.clk                    (clk_0_clk_clk),                                  //                      clk.clk
		.reset                  (led_pio_test_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (timecode_tx_enable_s1_agent_m0_address),         // avalon_universal_slave_0.address
		.uav_burstcount         (timecode_tx_enable_s1_agent_m0_burstcount),      //                         .burstcount
		.uav_read               (timecode_tx_enable_s1_agent_m0_read),            //                         .read
		.uav_write              (timecode_tx_enable_s1_agent_m0_write),           //                         .write
		.uav_waitrequest        (timecode_tx_enable_s1_agent_m0_waitrequest),     //                         .waitrequest
		.uav_readdatavalid      (timecode_tx_enable_s1_agent_m0_readdatavalid),   //                         .readdatavalid
		.uav_byteenable         (timecode_tx_enable_s1_agent_m0_byteenable),      //                         .byteenable
		.uav_readdata           (timecode_tx_enable_s1_agent_m0_readdata),        //                         .readdata
		.uav_writedata          (timecode_tx_enable_s1_agent_m0_writedata),       //                         .writedata
		.uav_lock               (timecode_tx_enable_s1_agent_m0_lock),            //                         .lock
		.uav_debugaccess        (timecode_tx_enable_s1_agent_m0_debugaccess),     //                         .debugaccess
		.av_address             (timecode_tx_enable_s1_address),                  //      avalon_anti_slave_0.address
		.av_write               (timecode_tx_enable_s1_write),                    //                         .write
		.av_readdata            (timecode_tx_enable_s1_readdata),                 //                         .readdata
		.av_writedata           (timecode_tx_enable_s1_writedata),                //                         .writedata
		.av_chipselect          (timecode_tx_enable_s1_chipselect),               //                         .chipselect
		.av_read                (),                                               //              (terminated)
		.av_begintransfer       (),                                               //              (terminated)
		.av_beginbursttransfer  (),                                               //              (terminated)
		.av_burstcount          (),                                               //              (terminated)
		.av_byteenable          (),                                               //              (terminated)
		.av_readdatavalid       (1'b0),                                           //              (terminated)
		.av_waitrequest         (1'b0),                                           //              (terminated)
		.av_writebyteenable     (),                                               //              (terminated)
		.av_lock                (),                                               //              (terminated)
		.av_clken               (),                                               //              (terminated)
		.uav_clken              (1'b0),                                           //              (terminated)
		.av_debugaccess         (),                                               //              (terminated)
		.av_outputenable        (),                                               //              (terminated)
		.uav_response           (),                                               //              (terminated)
		.av_response            (2'b00),                                          //              (terminated)
		.uav_writeresponsevalid (),                                               //              (terminated)
		.av_writeresponsevalid  (1'b0)                                            //              (terminated)
	);
 
	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (30),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) timecode_tx_ready_s1_translator (
		.clk                    (clk_0_clk_clk),                                  //                      clk.clk
		.reset                  (led_pio_test_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (timecode_tx_ready_s1_agent_m0_address),          // avalon_universal_slave_0.address
		.uav_burstcount         (timecode_tx_ready_s1_agent_m0_burstcount),       //                         .burstcount
		.uav_read               (timecode_tx_ready_s1_agent_m0_read),             //                         .read
		.uav_write              (timecode_tx_ready_s1_agent_m0_write),            //                         .write
		.uav_waitrequest        (timecode_tx_ready_s1_agent_m0_waitrequest),      //                         .waitrequest
		.uav_readdatavalid      (timecode_tx_ready_s1_agent_m0_readdatavalid),    //                         .readdatavalid
		.uav_byteenable         (timecode_tx_ready_s1_agent_m0_byteenable),       //                         .byteenable
		.uav_readdata           (timecode_tx_ready_s1_agent_m0_readdata),         //                         .readdata
		.uav_writedata          (timecode_tx_ready_s1_agent_m0_writedata),        //                         .writedata
		.uav_lock               (timecode_tx_ready_s1_agent_m0_lock),             //                         .lock
		.uav_debugaccess        (timecode_tx_ready_s1_agent_m0_debugaccess),      //                         .debugaccess
		.av_address             (timecode_tx_ready_s1_address),                   //      avalon_anti_slave_0.address
		.av_readdata            (timecode_tx_ready_s1_readdata),                  //                         .readdata
		.av_write               (),                                               //              (terminated)
		.av_read                (),                                               //              (terminated)
		.av_writedata           (),                                               //              (terminated)
		.av_begintransfer       (),                                               //              (terminated)
		.av_beginbursttransfer  (),                                               //              (terminated)
		.av_burstcount          (),                                               //              (terminated)
		.av_byteenable          (),                                               //              (terminated)
		.av_readdatavalid       (1'b0),                                           //              (terminated)
		.av_waitrequest         (1'b0),                                           //              (terminated)
		.av_writebyteenable     (),                                               //              (terminated)
		.av_lock                (),                                               //              (terminated)
		.av_chipselect          (),                                               //              (terminated)
		.av_clken               (),                                               //              (terminated)
		.uav_clken              (1'b0),                                           //              (terminated)
		.av_debugaccess         (),                                               //              (terminated)
		.av_outputenable        (),                                               //              (terminated)
		.uav_response           (),                                               //              (terminated)
		.av_response            (2'b00),                                          //              (terminated)
		.uav_writeresponsevalid (),                                               //              (terminated)
		.av_writeresponsevalid  (1'b0)                                            //              (terminated)
	);
 
	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                &