Subversion Repositories t6507lp

////////////////////////////////////////////////////////////////////////////
////									////
//// T6507LP IP Core	 						////
////									////
//// This file is part of the T6507LP project				////
//// http://www.opencores.org/cores/t6507lp/				////
////									////
//// Description							////
//// 6507 FSM								////
////									////
//// TODO:								////
//// - Perform simple tests before going into serious verification	////
//// 									////
//// Author(s):								////
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com			////
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com	////
////									////
////////////////////////////////////////////////////////////////////////////
////									////
//// Copyright (C) 2001 Authors and OPENCORES.ORG			////
////									////
//// This source file may be used and distributed without		////
//// restriction provided that this copyright statement is not		////
//// removed from the file and that any derivative work contains	////
//// the original copyright notice and the associated disclaimer.	////
////									////
//// This source file is free software; you can redistribute it		////
//// and/or modify it under the terms of the GNU Lesser General		////
//// Public License as published by the Free Software Foundation;	////
//// either version 2.1 of the License, or (at your option) any		////
//// later version.							////
////									////
//// This source is distributed in the hope that it will be		////
//// useful, but WITHOUT ANY WARRANTY; without even the implied		////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR		////
//// PURPOSE. See the GNU Lesser General Public License for more	////
//// details.								////
////									////
//// You should have received a copy of the GNU Lesser General		////
//// Public License along with this source; if not, download it		////
//// from http://www.opencores.org/lgpl.shtml				////
////									////
////////////////////////////////////////////////////////////////////////////
 
 
`timescale 1ns / 1ps
 
module t6507lp_fsm_tb();
	reg clk_in;
	reg rst_in_n;
	reg [7:0] alu_result;
	reg [7:0] alu_status;
	reg [7:0] data_in;
 
	wire [12:0] address;
	wire control; // one bit is enough? read = 0, write = 1
	wire [7:0] data_out;
	wire [7:0] alu_opcode;
	wire [7:0] alu_a;
	wire alu_enable;
 
	`include "../T6507LP_Package.v"
 
	t6507lp_fsm #(8,13) my_dut(clk_in, rst_in_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable);
 
	always #10 clk_in = ~clk_in;
 
	initial begin
		clk_in = 0;
		data_in = ASL_ACC;
		rst_in_n = 1'b0;
		alu_result = 0;
		alu_status = 0;
 
		@(negedge clk_in) //will wait for next negative edge of the clock (t=20)
		rst_in_n=1'b1;
 
		@(negedge clk_in) //will wait for next negative edge of the clock (t=40)
		data_in = ROL_ACC;
 
		@(negedge clk_in) //will wait for next negative edge of the clock (t=60)
		data_in = ROR_ACC;
 
		@(negedge clk_in) //will wait for next negative edge of the clock (t=80)
		@(negedge clk_in) //will wait for next negative edge of the clock (t=100)
		@(negedge clk_in) //will wait for next negative edge of the clock (t=120)
		$finish; // to shut down the simulation
	end //initial
 
 
endmodule