Subversion Repositories uart2bus_testbench

//-----------------------------------------------------------------------------
//
//                             UART2BUS VERIFICATION
//
//-----------------------------------------------------------------------------
// CREATOR    : HANY SALAH
// PROJECT    : UART2BUS UVM TEST BENCH
// UNIT       : CONFIGURATION
//-----------------------------------------------------------------------------
// TITLE      : UART Configuration
// DESCRIPTION: This 
//-----------------------------------------------------------------------------
// LOG DETAILS
//-------------
// VERSION      NAME        DATE        DESCRIPTION
//    1       HANY SALAH    02012016    FILE CREATION
//-----------------------------------------------------------------------------
// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR
// OPENCORES MEMBERS ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE 
// CREATOR'S PERMISSION
//-----------------------------------------------------------------------------

class uart_config extends uvm_object;
  
  virtual uart_interface    uart_inf;

  virtual rf_interface      rf_inf;

  virtual uart_arbiter      arb_inf;

  act_edge      _edge;

  start_bit     _start;

  data_mode                     _datamode;

  int                                   num_stop_bits;

  int                                   num_of_bits;

  parity_mode           _paritymode;

  time          response_time;

  `uvm_object_utils(uart_config)

  function new (string name = "uart_config");
    super.new(name);
  endfunction:new
endclass:uart_config