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https://opencores.org/ocsvn/uart2bus_testbench/uart2bus_testbench/trunk
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[/] [uart2bus_testbench/] [trunk/] [tb/] [analysis/] [uart_scoreboard.svh] - Rev 2
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//-----------------------------------------------------------------------------
//
// UART2BUS VERIFICATION
//
//-----------------------------------------------------------------------------
// CREATOR : HANY SALAH
// PROJECT : UART2BUS UVM TEST BENCH
// UNIT : ANALYSIS
//-----------------------------------------------------------------------------
// TITLE : UART ANALYSIS
// DESCRIPTION: This
//-----------------------------------------------------------------------------
// LOG DETAILS
//-------------
// VERSION NAME DATE DESCRIPTION
// 1 HANY SALAH 22012016 FILE CREATION
//-----------------------------------------------------------------------------
// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR
// OPENCORES MEMBERS ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE
// CREATOR'S PERMISSION
//-----------------------------------------------------------------------------
class uart_scoreboard extends uvm_scoreboard;
uvm_tlm_analysis_fifo #(uart_transaction) mon_fifo;
uvm_analysis_export #(uart_transaction) scbd_mon;
uvm_tlm_analysis_fifo #(uart_transaction) drv_fifo;
uvm_analysis_export #(uart_transaction) scbd_drv;
uart_transaction frm_drv,frm_drv_tmp;
uart_transaction frm_mon,frm_mon_tmp;
`uvm_component_utils(uart_scoreboard)
function new (string name , uvm_component parent);
super.new(name,parent);
endfunction:new
extern function void build_phase (uvm_phase phase);
extern function void connect_phase (uvm_phase phase);
extern task run_phase (uvm_phase phase);
endclass:uart_scoreboard
function void uart_scoreboard::build_phase (uvm_phase phase);
super.build_phase(phase);
frm_drv = uart_transaction::type_id::create("frm_drv");
frm_drv_tmp = uart_transaction::type_id::create("frm_drv_tmp");
frm_mon = uart_transaction::type_id::create("frm_mon");
frm_mon_tmp = uart_transaction::type_id::create("frm_mon_tmp");
mon_fifo = new ("mon_fifo",this);
scbd_mon = new ("scbd_mon",this);
drv_fifo = new ("drv_fifo",this);
scbd_drv = new ("scbd_drv",this);
endfunction:build_phase
function void uart_scoreboard::connect_phase (uvm_phase phase);
scbd_mon.connect(mon_fifo.analysis_export);
scbd_drv.connect(drv_fifo.analysis_export);
endfunction:connect_phase
task uart_scoreboard::run_phase (uvm_phase phase);
int iteration;
iteration = 0;
forever
begin
iteration++;
drv_fifo.get(frm_drv_tmp);
$cast(frm_drv,frm_drv_tmp.clone());
mon_fifo.get(frm_mon_tmp);
$cast(frm_mon,frm_mon_tmp.clone());
if (frm_drv._mode != frm_mon._mode)
begin
`uvm_fatal("Testbench Bug",$sformatf("Modes aren't similiar .. @time=%0t, It was requested to use %p mode and the applied mode is %p ",$time,frm_drv._mode,frm_mon._mode))
end
else
begin
case (frm_drv._mode)
text:
begin
if(frm_drv._command != frm_mon._command)
begin
`uvm_fatal("Testbench Bug",$sformatf("Commands aren't identical .. @time=%0t, It was requested to drive %p command and the applied command is %p ",$time,frm_drv._command,frm_mon._command))
end
else
begin
case(frm_drv._command)
read:
begin
if (frm_drv._data != frm_mon._data)
begin
`uvm_error("Failed Read Text Mode",$sformatf("Data fields aren't identical ,, @time=%0t It was requested to drive %p and dut reply with the data %p",$time,frm_drv._data,frm_mon._data))
end
else if((frm_drv._data == frm_mon._data) &&
(frm_drv.address == frm_mon.address) &&
(frm_drv._spacetype1 == frm_mon._spacetype1) &&
(frm_drv._eoltype == frm_mon._eoltype) &&
(frm_drv._chartype == frm_mon._chartype))
begin
`uvm_info("Passed Read Text Mode",$sformatf("Data fields are identical ,, @time=%0t It was requested to read from the address %h and dut reply with the data %p using white space = %p and %p prefix character and %p as end of line character",$time,frm_drv.address,frm_mon._data,frm_drv._spacetype1,frm_drv._chartype,
frm_drv._eoltype),UVM_NONE)
end
else
begin
`uvm_error("Failed Read Text Mode",$sformatf("@time=%0t .. It is Requested to request to read data = %p address of %h with character prefix : %p using white space = %p and end of line character %p .. and found data = %p and address=%h with character prefix : %p using white space = %p and end of line character %p",$time, frm_drv._data,frm_drv.address,frm_drv._chartype,frm_drv._spacetype1,frm_drv._eoltype,
frm_mon._data,frm_mon.address,frm_mon._chartype,frm_mon._spacetype1,frm_mon._eoltype))
end
end
write:
begin
if (frm_drv._data != frm_mon._data)
begin
`uvm_error("Failed Write Text Mode",$sformatf("Data fields aren't identical ,, @time=%0t It was requested to drive %p and dut register the data %p",$time,frm_drv._data,frm_mon._data))
end
else if((frm_drv._data == frm_mon._data) &&
(frm_drv.address == frm_mon.address) &&
(frm_drv._spacetype1 == frm_mon._spacetype1) &&
(frm_drv._eoltype == frm_mon._eoltype) &&
(frm_drv._chartype == frm_mon._chartype))
begin
`uvm_info("Passed write Text Mode",$sformatf("Data fields are identical ,, @time=%0t It was requested to write to the address %h and dut register the data %p using white space = %p and %p prefix character and %p as end of line character",$time,frm_drv.address,frm_mon._data,frm_drv._spacetype1,frm_drv._chartype,
frm_drv._eoltype),UVM_NONE)
end
else
begin
`uvm_error("Failed write Text Mode",$sformatf("@time=%0t .. It is Requested to request to write data = %p address of %h with character prefix : %p using white space = %p and end of line character %p .. and found data = %p and address=%h with character prefix : %p using white space = %p and end of line character %p",$time, frm_drv._data,frm_drv.address,frm_drv._chartype,frm_drv._spacetype1,frm_drv._eoltype,
frm_mon._data,frm_mon.address,frm_mon._chartype,frm_mon._spacetype1,frm_mon._eoltype))
end
end
default:
begin
`uvm_fatal("Testbench Bug",$sformatf("@time = %0t .. It isn't allowablt to drive %p command through text mode",$time,frm_drv._command))
end
endcase
end
end
binary:
begin
end
wrong_mode:
begin
end
default:
begin
`uvm_fatal("Testbench Bug",$sformatf("Mode is undefined = %p",frm_drv._mode))
end
endcase
end
end
endtask:run_phase
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