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Subversion Repositories uart2bus_testbench

[/] [uart2bus_testbench/] [trunk/] [tb/] [draft] - Rev 11

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view wave

add wave  \
sim:/uart_top_tb/uart_inf/ser_in \
sim:/uart_top_tb/uart_inf/ser_out \
sim:/uart_top_tb/uart_inf/clock \
sim:/uart_top_tb/uart_inf/start_trans \
sim:/uart_top_tb/rf_inf/int_address \
sim:/uart_top_tb/rf_inf/int_wr_data \
sim:/uart_top_tb/rf_inf/int_write \
sim:/uart_top_tb/rf_inf/int_rd_data \
sim:/uart_top_tb/rf_inf/int_read \
sim:/uart_top_tb/rf_inf/int_gnt \
sim:/uart_top_tb/rf_inf/int_req

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