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                Core name: Xilinx LogiCORE Block Memory Generator
                Version: 6.2
                Release Date: June 22, 2011


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This document contains the following sections:

1. Introduction
2. New Features
3. Supported Devices
4. Resolved Issues
5. Known Issues
6. Technical Support
7. Core Release History
8. Legal Disclaimer

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1. INTRODUCTION

For installation instructions for this release, please go to:

  http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm

For system requirements:

   http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm

This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v6.2 
solution. For the latest core updates, see the product page at:
 
 http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm


2. NEW FEATURES

  - ISE 13.2 software support
  - Virtex-7L, Kintex-7L, Artix-7* and Zynq-7000* device support

3. SUPPORTED DEVICES

The following device families are supported by the core for this release.

Zynq-7000*

Virtex-7 
Virtex-7 XT (7vx485t)
Virtex-7 -2L

Kintex-7
Kintex-7 -2L 

Artix-7*

Virtex-6 XC CXT/LXT/SXT/HXT
Virtex-6 XQ LXT/SXT                                                       
Virtex-6 -1L XQ LXT/SXT 

Spartan-6 XC LX/LXT 
Spartan-6 XA 
Spartan-6 XQ LX/LXT       
Spartan-6 -1L XQ LX

Virtex-5 XC LX/LXT/SXT/TXT/FXT
Virtex-5 XQ LX/ LXT/SXT/FXT                                                

Virtex-4 XC LX/SX/FX
Virtex-4 XQ LX/SX/FX
Virtex-4 XQR LX/SX/FX                                                  

Spartan-3 XC
Spartan-3 XA                                                                      
Spartan-3A XC 3A / 3A DSP / 3AN DSP                                      
Spartan-3A XA 3A / 3A DSP                                                    
Spartan-3E XC                                        
Spartan-3E XA 

*To access these devices in the ISE Design Suite, contact your Xilinx FAE.

4. RESOLVED ISSUES

The following issues are resolved in Block Memory Generator v6.2: 
  
  1. Core errors in NGDBuild when the depth is too large (especially for Spartan-6 devices)
   Version Fixed: v6.2 
   - CR 587481
   - AR 39718

5. KNOWN ISSUES 

The following are known issues for v6.2 of this core at time of release:

  1. Virtex-6 and Spartan-6: BRAM Memory collision error, when the user selects TDP (write_mode= Read First)
    Work around: The user must review the possible scenarios that causes the collission and revise 
     their design to avoid those situations.
    - CR588505
  
    Note: Refer to UG383, 'Conflict Avoidance' section when using TDP Memory - with 
          Write Mode = Read First in conjunction with asynchronous clocking
   
  2. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3.

  3. Core does not generate for large memories. Depending on the
     machine the ISE CORE Generator software runs on, the maximum size of the memory that
     can be generated will vary.  For example, a Dual Pentium-4 server 
     with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes
    - CR 415768
    - AR 24034
  
The most recent information, including known issues, workarounds, and resolutions for 
this version is provided in the IP Release Notes User Guide located at
  
       www.xilinx.com/support/documentation/user_guides/xtp025.pdf
   
6. TECHNICAL SUPPORT 

To obtain technical support, create a WebCase at www.xilinx.com/support.
Questions are routed to a team with expertise using this product.

Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.

7. CORE RELEASE HISTORY 

Date        By            Version      Description
================================================================================
06/22/2011  Xilinx, Inc.  6.2          ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support;
03/01/2011  Xilinx, Inc.  6.1          ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support
09/21/2010  Xilinx, Inc.  4.3          ISE 12.3 support
07/23/2010  Xilinx, Inc.  4.2          ISE 12.2 support
04/19/2010  Xilinx, Inc.  4.1          ISE 12.1 support
03/09/2010  Xilinx, Inc.  3.3 rev 2    Fix for V6 Memory collision issue 
12/02/2009  Xilinx, Inc.  3.3 rev 1    ISE 11.4 support; Spartan-6 Low Power
                                       Device support; Automotive Spartan 3A
                                       DSP device support
09/16/2009  Xilinx, Inc.  3.3          Revised to v3.3
06/24/2009  Xilinx, Inc.  3.2          Revised to v3.2
04/24/2009  Xilinx, Inc.  3.1          Revised to v3.1
09/19/2008  Xilinx, Inc.  2.8          Revised to v2.8
03/24/2008  Xilinx, Inc.  2.7          10.1 support; Revised to v2.7
10/03/2007  Xilinx, Inc.  2.6          Revised to v2.6
07/2007     Xilinx, Inc.  2.5          Revised to v2.5
04/2007     Xilinx, Inc.  2.4          Revised to v2.4 rev 1
02/2007     Xilinx, Inc.  2.4          Revised to v2.4
11/2006     Xilinx, Inc.  2.3          Revised to v2.3
09/2006     Xilinx, Inc.  2.2          Revised to v2.2
06/2006     Xilinx, Inc.  2.1          Revised to v2.1
01/2006     Xilinx, Inc.  1.1          Initial release
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8. Legal Disclaimer

 (c) Copyright 2006 - 2011 Xilinx, Inc. All rights reserved.
 
 This file contains confidential and proprietary information
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 laws.
 
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 WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
 AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
 BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
 INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
 (2) Xilinx shall not be liable (whether in contract or tort,
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 materials, including for any direct, or any indirect,
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