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https://opencores.org/ocsvn/vspi/vspi/trunk
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[/] [vspi/] [trunk/] [projnav/] [xps/] [pcores/] [spiifc_v1_00_a/] [devl/] [projnav/] [ipcore_dir/] [coregen.cgp] - Rev 14
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SET busformat = BusFormatAngleBracketNotRipped
SET designentry = Verilog
SET device = xc6slx45
SET devicefamily = spartan6
SET flowvendor = Other
SET package = csg324
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false