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################################################################################
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# (c) Copyright 2002 - 2010 Xilinx, Inc. All rights reserved.
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# Tx Core Period Constraint. This constraint can be modified, and is
# valid as long as it is met after place and route.
NET "CLKA" TNM_NET = "CLKA";
NET "CLKB" TNM_NET = "CLKB";
TIMESPEC "TS_CLKA" = PERIOD "CLKA" 25 MHZ;
TIMESPEC "TS_CLKB" = PERIOD "CLKB" 25 MHZ;
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