URL
https://opencores.org/ocsvn/vspi/vspi/trunk
Subversion Repositories vspi
[/] [vspi/] [trunk/] [projnav/] [xps/] [pcores/] [spiifc_v1_00_a/] [devl/] [projnav/] [ipcore_dir/] [tmp/] [_cg/] [_dbg/] [xil_53.in] - Rev 14
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SET_FLAG DEBUG FALSESET_FLAG MODE INTERACTIVESET_FLAG STANDALONE_MODE FALSESET_PREFERENCE devicefamily spartan6SET_PREFERENCE device xc6slx45SET_PREFERENCE speedgrade -2SET_PREFERENCE package csg324SET_PREFERENCE verilogsim trueSET_PREFERENCE vhdlsim falseSET_PREFERENCE simulationfiles BehavioralSET_PREFERENCE busformat BusFormatAngleBracketNotRippedSET_PREFERENCE outputdirectory C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/SET_PREFERENCE workingdirectory C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/SET_PREFERENCE subworkingdirectory C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/SET_PREFERENCE transientdirectory C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/SET_PREFERENCE designentry VerilogSET_PREFERENCE flowvendor OtherSET_PREFERENCE addpads falseSET_PREFERENCE projectname coregenSET_PREFERENCE formalverification falseSET_PREFERENCE asysymbol falseSET_PREFERENCE implementationfiletype NgcSET_PREFERENCE foundationsym falseSET_PREFERENCE createndf falseSET_PREFERENCE removerpms falseSET_PARAMETER Component_Name spiloopmemSET_PARAMETER Interface_Type NativeSET_PARAMETER AXI_Type AXI4_FullSET_PARAMETER AXI_Slave_Type Memory_SlaveSET_PARAMETER Use_AXI_ID falseSET_PARAMETER AXI_ID_Width 4SET_PARAMETER Memory_Type Simple_Dual_Port_RAMSET_PARAMETER ecctype No_ECCSET_PARAMETER ECC falseSET_PARAMETER softecc falseSET_PARAMETER Use_Error_Injection_Pins falseSET_PARAMETER Error_Injection_Type Single_Bit_Error_InjectionSET_PARAMETER Use_Byte_Write_Enable falseSET_PARAMETER Byte_Size 9SET_PARAMETER Algorithm Minimum_AreaSET_PARAMETER Primitive 8kx2SET_PARAMETER Assume_Synchronous_Clk falseSET_PARAMETER Write_Width_A 8SET_PARAMETER Write_Depth_A 4096SET_PARAMETER Read_Width_A 8SET_PARAMETER Operating_Mode_A WRITE_FIRSTSET_PARAMETER Enable_A Use_ENA_PinSET_PARAMETER Write_Width_B 8SET_PARAMETER Read_Width_B 8SET_PARAMETER Operating_Mode_B WRITE_FIRSTSET_PARAMETER Enable_B Use_ENB_PinSET_PARAMETER Register_PortA_Output_of_Memory_Primitives falseSET_PARAMETER Register_PortA_Output_of_Memory_Core falseSET_PARAMETER Use_REGCEA_Pin falseSET_PARAMETER Register_PortB_Output_of_Memory_Primitives falseSET_PARAMETER Register_PortB_Output_of_Memory_Core falseSET_PARAMETER Use_REGCEB_Pin falseSET_PARAMETER register_porta_input_of_softecc falseSET_PARAMETER register_portb_output_of_softecc falseSET_PARAMETER Pipeline_Stages 0SET_PARAMETER Load_Init_File falseSET_PARAMETER Coe_File no_coe_file_loadedSET_PARAMETER Fill_Remaining_Memory_Locations falseSET_PARAMETER Remaining_Memory_Locations 0SET_PARAMETER Use_RSTA_Pin falseSET_PARAMETER Reset_Memory_Latch_A falseSET_PARAMETER Reset_Priority_A CESET_PARAMETER Output_Reset_Value_A 0SET_PARAMETER Use_RSTB_Pin falseSET_PARAMETER Reset_Memory_Latch_B falseSET_PARAMETER Reset_Priority_B CESET_PARAMETER Output_Reset_Value_B 0SET_PARAMETER Reset_Type SYNCSET_PARAMETER Additional_Inputs_for_Power_Estimation falseSET_PARAMETER Port_A_Clock 100SET_PARAMETER Port_A_Write_Rate 50SET_PARAMETER Port_B_Clock 100SET_PARAMETER Port_B_Write_Rate 0SET_PARAMETER Port_A_Enable_Rate 100SET_PARAMETER Port_B_Enable_Rate 100SET_PARAMETER Collision_Warnings ALLSET_PARAMETER Disable_Collision_Warnings falseSET_PARAMETER Disable_Out_of_Range_Warnings falseSET_CORE_NAME Block Memory GeneratorSET_CORE_VERSION 6.2SET_CORE_VLNV xilinx.com:ip:blk_mem_gen:6.2SET_CORE_CLASS com.xilinx.ip.blk_mem_gen_v6_2.blk_mem_gen_v6_2SET_CORE_PATH C:/Xilinx/13.2/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/blk_mem_gen_v6_2SET_CORE_GUIPATH C:/Xilinx/13.2/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/blk_mem_gen_v6_2/gui/blk_mem_gen_v6_2.tclSET_CORE_DATASHEET C:\Xilinx\13.2\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\doc\blk_mem_gen_ds512.pdfADD_CORE_DOCUMENT <C:\Xilinx\13.2\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\doc\blk_mem_gen_ds512.pdf><blk_mem_gen_ds512.pdf>ADD_CORE_DOCUMENT <C:\Xilinx\13.2\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\doc\blk_mem_gen_v6_2_vinfo.html><blk_mem_gen_v6_2_vinfo.html>