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[/] [vspi/] [trunk/] [projnav/] [xps/] [pcores/] [spiifc_v1_00_a/] [devl/] [projnav/] [spiloop_isim_beh1.wdb] - Rev 14

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kspace/vSPI/src/spi_base/spiloop.vC:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/spiloopmem.vC:/Xilinx/13.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V6_2.vC:/Users/mjlyons/workspace/vSPI/src/spi_base/spiifc.vC:/Xilinx/13.2/ISE_DS/ISE/verilog/src/glbl.v_top_topspiloopspiloopResetSysClkspi_ssspi_mosispi_clkspi_misoledsdebug_outtxMemAddrtxMemDatarcMemAddrrcMemDatarcMemWEglblglblGSRGTSGWEPRLDp_up_tmpPLL_LOCKGPROGB_GLBLJTAG_TDO_GLBLJTAG_TCK_GLBLJTAG_TDI_GLBLJTAG_TMS_GLBLJTAG_TRST_GLBLGSR_intGTS_intPRLD_intJTAG_CAPTURE_GLBLJTAG_RESET_GLBLJTAG_SHIFT_GLBLJTAG_UPDATE_GLBLJTAG_RUNTEST_GLBLJTAG_SEL1_GLBLJTAG_SEL2_GLBLJTAG_SEL3_GLBLJTAG_SEL4_GLBLJTAG_USER_TDO1_GLBLJTAG_USER_TDO2_GLBLJTAG_USER_TDO3_GLBLJTAG_USER_TDO4_GLBLROC_WIDTHTOC_WIDTHyour_instance_namespiloopmemclkaenaweaaddradinaclkbenbaddrbdoutbmySpiIfcspiifcResetSysClkSPI_CLKSPI_MISOSPI_MOSISPI_SStxMemAddrtxMemDatarcMemAddrrcMemDatarcMemWEdebug_outrisingSpiClkvalidSpiBitrcByteValidrcBytercBitIndexpacketStartSPI_CLK_regSPI_SS_regSPI_MOSI_regprev_spiClkprev_spiSSstate_regrcByte_regrcBitIndex_regrcMemAddr_regdebug_regtxBitIndex_regtxMemAddr_regstatetxBitIndextxMemAddr_oregAddrBitsCont_65_0spiloopinstBLK_MEM_GEN_V6_2CLKARSTAENAREGCEAWEAADDRADINADOUTACLKBRSTBENBREGCEBWEBADDRBDINBDOUTBINJECTSBITERRINJECTDBITERRSBITERRDBITERRRDADDRECCS_ACLKS_ARESETNS_AXI_AWIDS_AXI_AWADDRS_AXI_AWLENS_AXI_AWSIZES_AXI_AWBURSTS_AXI_AWVALIDS_AXI_AWREADYS_AXI_WDATAS_AXI_WSTRBS_AXI_WLASTS_AXI_WVALIDS_AXI_WREADYS_AXI_BIDS_AXI_BRESPS_AXI_BVALIDS_AXI_BREADYS_AXI_ARIDS_AXI_ARADDRS_AXI_ARLENS_AXI_ARSIZES_AXI_ARBURSTS_AXI_ARVALIDS_AXI_ARREADYS_AXI_RIDS_AXI_RDATAS_AXI_RRESPS_AXI_RLASTS_AXI_RVALIDS_AXI_RREADYS_AXI_INJECTSBITERRS_AXI_INJECTDBITERRS_AXI_SBITERRS_AXI_DBITERRS_AXI_RDADDRECCs_axi_awaddr_out_cs_axi_araddr_out_cs_axi_wr_en_cs_axi_rd_en_cs_aresetn_a_cs_axi_arlen_cs_axi_rid_cs_axi_rdata_cs_axi_rresp_cs_axi_rlast_cs_axi_rvalid_cs_axi_rready_cregceb_cs_axi_payload_cm_axi_payload_cinjectsbiterr_ininjectdbiterr_inrsta_inena_inregcea_inwea_inaddra_indina_inC_CORENAMEC_FAMILYC_XDEVICEFAMILYC_INTERFACE_TYPEC_AXI_TYPEC_AXI_SLAVE_TYPEC_HAS_AXI_IDC_AXI_ID_WIDTHC_MEM_TYPEC_BYTE_SIZEC_ALGORITHMC_PRIM_TYPEC_LOAD_INIT_FILEC_INIT_FILE_NAMEC_USE_DEFAULT_DATAC_DEFAULT_DATAC_RST_TYPEC_HAS_RSTAC_RST_PRIORITY_AC_RSTRAM_AC_INITA_VALC_HAS_ENAC_HAS_REGCEAC_USE_BYTE_WEAC_WEA_WIDTHC_WRITE_MODE_AC_WRITE_WIDTH_AC_READ_WIDTH_AC_WRITE_DEPTH_AC_READ_DEPTH_AC_ADDRA_WIDTHC_HAS_RSTBC_RST_PRIORITY_BC_RSTRAM_BC_INITB_VALC_HAS_ENBC_HAS_REGCEBC_USE_BYTE_WEBC_WEB_WIDTHC_WRITE_MODE_BC_WRITE_WIDTH_BC_READ_WIDTH_BC_WRITE_DEPTH_BC_READ_DEPTH_BC_ADDRB_WIDTHC_HAS_MEM_OUTPUT_REGS_AC_HAS_MEM_OUTPUT_REGS_BC_HAS_MUX_OUTPUT_REGS_AC_HAS_MUX_OUTPUT_REGS_BC_HAS_SOFTECC_INPUT_REGS_AC_HAS_SOFTECC_OUTPUT_REGS_BC_MUX_PIPELINE_STAGESC_USE_SOFTECCC_USE_ECCC_HAS_INJECTERRC_SIM_COLLISION_CHECKC_COMMON_CLKC_DISABLE_WARN_BHV_COLLC_DISABLE_WARN_BHV_RANGEFLOP_DELAYC_AXI_PAYLOADAXI_FULL_MEMORY_SLAVEC_AXI_ADDR_WIDTH_MSBC_AXI_ADDR_WIDTHLOWER_BOUND_VALC_AXI_ADDR_WIDTH_LSBC_AXI_OS_WRlog2rounduplog2roundupdata_valuelog2roundupwidthcntdivroundupdivroundupdata_valuedivisordivroundupdivnative_mem_module.blk_mem_gen_v6_2_instBLK_MEM_GEN_V6_2_mem_moduleCLKARSTAENAREGCEAWEAADDRADINADOUTACLKBRSTBENBREGCEBWEBADDRBDINBDOUTBINJECTSBITERRINJECTDBITERRSBITERRDBITERRRDADDRECCsbiterr_sdpdbiterr_sdpdout_idbiterr_isbiterr_irdaddrecc_irdaddrecc_sdpena_ienb_ireseta_iresetb_iwea_iweb_irea_ireb_iasync_coll.addra_delayasync_coll.wea_delayasync_coll.ena_delayasync_coll.addrb_delayasync_coll.web_delayasync_coll.enb_delaymemorydoublebit_errorsbiterr_arrdbiterr_arrsoftecc_sbiterr_arrsoftecc_dbiterr_arrmemory_out_amemory_out_bsbiterr_indbiterr_inrdaddrecc_ininita_valinitb_valis_collisionis_collision_ais_collision_delay_ais_collision_bis_collision_delay_bstatusinitfilemif_datainita_strinitb_strdefault_data_strinit_file_strcntwrite_addr_a_widthread_addr_a_widthwrite_addr_b_widthread_addr_b_widthC_CORENAMEC_FAMILYC_XDEVICEFAMILYC_MEM_TYPEC_BYTE_SIZEC_ALGORITHMC_PRIM_TYPEC_LOAD_INIT_FILEC_INIT_FILE_NAMEC_USE_DEFAULT_DATAC_DEFAULT_DATAC_RST_TYPEC_HAS_RSTAC_RST_PRIORITY_AC_RSTRAM_AC_INITA_VALC_HAS_ENAC_HAS_REGCEAC_USE_BYTE_WEAC_WEA_WIDTHC_WRITE_MODE_AC_WRITE_WIDTH_AC_READ_WIDTH_AC_WRITE_DEPTH_AC_READ_DEPTH_AC_ADDRA_WIDTHC_HAS_RSTBC_RST_PRIORITY_BC_RSTRAM_BC_INITB_VALC_HAS_ENBC_HAS_REGCEBC_USE_BYTE_WEBC_WEB_WIDTHC_WRITE_MODE_BC_WRITE_WIDTH_BC_READ_WIDTH_BC_WRITE_DEPTH_BC_READ_DEPTH_BC_ADDRB_WIDTHC_HAS_MEM_OUTPUT_REGS_AC_HAS_MEM_OUTPUT_REGS_BC_HAS_MUX_OUTPUT_REGS_AC_HAS_MUX_OUTPUT_REGS_BC_HAS_SOFTECC_INPUT_REGS_AC_HAS_SOFTECC_OUTPUT_REGS_BC_MUX_PIPELINE_STAGESC_USE_SOFTECCC_USE_ECCC_HAS_INJECTERRC_SIM_COLLISION_CHECKC_COMMON_CLKFLOP_DELAYC_DISABLE_WARN_BHV_COLLC_DISABLE_WARN_BHV_RANGEADDRFILECOLLFILEERRFILECOLL_DELAYCHKBIT_WIDTHMIN_WIDTH_AMIN_WIDTH_BMIN_WIDTHMAX_DEPTH_AMAX_DEPTH_BMAX_DEPTHWRITE_WIDTH_RATIO_AREAD_WIDTH_RATIO_AWRITE_WIDTH_RATIO_BREAD_WIDTH_RATIO_BWRITE_ADDR_A_DIVREAD_ADDR_A_DIVWRITE_ADDR_B_DIVREAD_ADDR_B_DIVBYTE_SIZEC_FAMILY_LOCALPARAMSINGLE_PORTIS_ROMHAS_A_WRITEHAS_B_WRITEHAS_A_READHAS_B_READHAS_B_PORTMUX_PIPELINE_STAGES_AMUX_PIPELINE_STAGES_BNUM_OUTPUT_STAGES_ANUM_OUTPUT_STAGES_BAlways_3888_0BLK_MEM_GEN_V6_2Cont_3999_1BLK_MEM_GEN_V6_2Cont_4000_2BLK_MEM_GEN_V6_2Cont_4001_3BLK_MEM_GEN_V6_2Cont_4002_4BLK_MEM_GEN_V6_2Cont_4003_5BLK_MEM_GEN_V6_2Cont_4004_6BLK_MEM_GEN_V6_2Cont_4014_7BLK_MEM_GEN_V6_2write_awrite_aaddrbyte_endatainj_sbiterrinj_dbiterrcurrent_contentsaddressiwrite_bwrite_baddrbyte_endatacurrent_contentsaddressiread_aread_aaddrresetaddressiread_bread_baddrresetaddressireset_areset_aresetreset_breset_bresetinit_memoryinit_memoryiaddr_stepstatusdefault_datalog2rounduplog2roundupdata_valuelog2roundupwidthcntcollision_checkcollision_checkaddr_aiswrite_aaddr_biswrite_bcollision_checkc_aw_bwc_aw_brc_ar_bwscaled_addra_to_waddrb_widthscaled_addrb_to_waddrb_widthscaled_addra_to_waddra_widthscaled_addrb_to_waddra_widthscaled_addra_to_raddrb_widthscaled_addrb_to_raddrb_widthscaled_addra_to_raddra_widthscaled_addrb_to_raddra_widthreg_aBLK_MEM_GEN_V6_2_output_stageCLKRSTENREGCEDINSBITERR_INDBITERR_INRDADDRECC_INen_iregce_irst_iDOUTSBITERRDBITERRRDADDRECCout_regsrdaddrecc_regssbiterr_regsdbiterr_regsinit_strinit_valC_FAMILYC_XDEVICEFAMILYC_RST_TYPEC_HAS_RSTC_RSTRAMC_RST_PRIORITYC_INIT_VALC_HAS_ENC_HAS_REGCEC_DATA_WIDTHC_ADDRB_WIDTHC_HAS_MEM_OUTPUT_REGSC_USE_SOFTECCC_USE_ECCNUM_STAGESFLOP_DELAYREG_STAGESreg_bBLK_MEM_GEN_V6_2_output_stageCLKRSTENREGCEDINSBITERR_INDBITERR_INRDADDRECC_INen_iregce_irst_iDOUTSBITERRDBITERRRDADDRECCout_regsrdaddrecc_regssbiterr_regsdbiterr_regsinit_strinit_valC_FAMILYC_XDEVICEFAMILYC_RST_TYPEC_HAS_RSTC_RSTRAMC_RST_PRIORITYC_INIT_VALC_HAS_ENC_HAS_REGCEC_DATA_WIDTHC_ADDRB_WIDTHC_HAS_MEM_OUTPUT_REGSC_USE_SOFTECCC_USE_ECCNUM_STAGESFLOP_DELAYREG_STAGEShas_softecc_output_reg_stageBLK_MEM_GEN_V6_2_softecc_output_reg_stageCLKDINSBITERR_INDBITERR_INRDADDRECC_INDOUTSBITERRDBITERRRDADDRECCdout_isbiterr_idbiterr_irdaddrecc_iC_DATA_WIDTHC_ADDRB_WIDTHC_HAS_SOFTECC_OUTPUT_REGS_BC_USE_SOFTECCFLOP_DELAYCont_2330_0BLK_MEM_GEN_V6_2_mem_moduleCont_2331_1BLK_MEM_GEN_V6_2_mem_moduleCont_2332_2BLK_MEM_GEN_V6_2_mem_moduleCont_2336_3BLK_MEM_GEN_V6_2_mem_moduleCont_2337_4BLK_MEM_GEN_V6_2_mem_moduleCont_2338_5BLK_MEM_GEN_V6_2_mem_moduleCont_2339_6BLK_MEM_GEN_V6_2_mem_moduleCont_2340_7BLK_MEM_GEN_V6_2_mem_moduleCont_2341_8BLK_MEM_GEN_V6_2_mem_moduleCont_2345_9BLK_MEM_GEN_V6_2_mem_moduleCont_2349_10BLK_MEM_GEN_V6_2_mem_moduleInitial_2918_11BLK_MEM_GEN_V6_2_mem_moduleAlways_3225_12BLK_MEM_GEN_V6_2_mem_moduleAlways_3267_13BLK_MEM_GEN_V6_2_mem_moduleNetDecl_3438_14BLK_MEM_GEN_V6_2_mem_moduleNetDecl_3439_15BLK_MEM_GEN_V6_2_mem_moduleNetDecl_3440_16BLK_MEM_GEN_V6_2_mem_moduleNetDecl_3441_17BLK_MEM_GEN_V6_2_mem_moduleNetDecl_3442_18BLK_MEM_GEN_V6_2_mem_moduleNetDecl_3443_19BLK_MEM_GEN_V6_2_mem_moduleAlways_3446_20BLK_MEM_GEN_V6_2_mem_moduleAlways_3487_21BLK_MEM_GEN_V6_2_mem_moduleCont_1671_0BLK_MEM_GEN_V6_2_output_stageCont_1677_1BLK_MEM_GEN_V6_2_output_stageCont_1681_2BLK_MEM_GEN_V6_2_output_stageInitial_1686_3BLK_MEM_GEN_V6_2_output_stageAlways_1705_4BLK_MEM_GEN_V6_2_output_stageCont_1671_0BLK_MEM_GEN_V6_2_output_stageCont_1677_1BLK_MEM_GEN_V6_2_output_stageCont_1681_2BLK_MEM_GEN_V6_2_output_stageInitial_1686_3BLK_MEM_GEN_V6_2_output_stageAlways_1705_4BLK_MEM_GEN_V6_2_output_stageAlways_1930_0BLK_MEM_GEN_V6_2_softecc_output_reg_stageAlways_103_0spiifcAlways_123_1spiifcCont_126_2spiifcCont_127_3spiifcAlways_130_4spiifcCont_133_5spiifcAlways_136_6spiifcCont_144_7spiifcCont_145_8spiifcCont_146_9spiifcCont_149_10spiifcCont_150_11spiifcCont_151_12spiifcAlways_152_13spiifcAlways_163_14spiifcAlways_176_15spiifcCont_184_16spiifcCont_185_17spiifcAlways_188_18spiifcAlways_198_19spiifcAlways_217_20spiifcCont_222_21spiifcNetDecl_16_0glblCont_47_1glblCont_48_2glblCont_49_3glblInitial_51_4glblInitial_59_5glbl

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