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[/] [a-z80/] [trunk/] - Rev 14

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Last modification

  • Rev 14 2016-12-10 04:16:14 GMT
  • Author: gdevic
  • Log message:
    Add hold_clk_wait to ALU CFL latch

    This correctly delays latching the C-Flag for CCF instruction when
    nWAIT was asserted at that instruction's M1/T2 cycle

    UART: fixed two synthesis warnings
Path Last modification Log RSS feed
[FOLDER] a-z80/ 14  2720d 00h gdevic View Log RSS feed
[NODE][FOLDER] branches/ 1  3448d 20h root View Log RSS feed
[NODE][FOLDER] tags/ 1  3448d 20h root View Log RSS feed
[NODE][FOLDER] trunk/ 14  2720d 00h gdevic View Log RSS feed
[NODE][NODE][FOLDER] cpu/ 14  2720d 00h gdevic View Log RSS feed
[NODE][NODE][FOLDER] docs/ 9  2992d 06h gdevic View Log RSS feed
[NODE][NODE][FOLDER] host/ 14  2720d 00h gdevic View Log RSS feed
[NODE][NODE][FOLDER] resources/ 8  2992d 08h gdevic View Log RSS feed
[NODE][NODE][FOLDER] tools/ 12  2733d 13h gdevic View Log RSS feed
[NODE][NODE][FILE] .gitignore 3  3442d 13h gdevic View Log RSS feed
[NODE][NODE][DB-FILE] license.txt 3  3442d 13h gdevic View Log RSS feed
[NODE][NODE][FILE] modelsim_pre_commit.py 8  2992d 08h gdevic View Log RSS feed
[NODE][NODE][FILE] modelsim_setup.py 8  2992d 08h gdevic View Log RSS feed
[NODE][NODE][DB-FILE] readme.txt 8  2992d 08h gdevic View Log RSS feed

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