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[/] [amber/] [trunk/] [hw/] [vlog/] - Rev 89

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  • Rev 89 2015-04-11 19:19:46 GMT
  • Author: csantifort
  • Log message:
    CHange registered outputs with non-zero initial values to wires with an internal register.
    This works around an issue with Altera (Quartus) synthesis where any port registers are given an initial vale of zero.
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[FOLDER] amber/ 89  3362d 14h csantifort View Log RSS feed
[NODE][FOLDER] branches/ 1  4932d 19h root View Log RSS feed
[NODE][FOLDER] tags/ 1  4932d 19h root View Log RSS feed
[NODE][FOLDER] trunk/ 89  3362d 14h csantifort View Log RSS feed
[NODE][NODE][FOLDER] doc/ 82  3389d 10h csantifort View Log RSS feed
[NODE][NODE][FOLDER] hw/ 89  3362d 14h csantifort View Log RSS feed
[NODE][NODE][NODE][FOLDER] fpga/ 86  3375d 15h csantifort View Log RSS feed
[NODE][NODE][NODE][FOLDER] isim/ 82  3389d 10h csantifort View Log RSS feed
[NODE][NODE][NODE][FOLDER] tests/ 87  3362d 18h csantifort View Log RSS feed
[NODE][NODE][NODE][FOLDER] tools/ 68  4075d 17h csantifort View Log RSS feed
[NODE][NODE][NODE][FOLDER] vlog/ 89  3362d 14h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] amber23/ 89  3362d 14h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] amber25/ 89  3362d 14h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] ethmac/ 82  3389d 10h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] lib/ 61  4362d 17h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] system/ 84  3375d 22h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] tb/ 82  3389d 10h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] xs6_ddr3/ 64  4075d 18h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][DB-FILE] README.txt 2  4905d 16h csantifort View Log RSS feed
[NODE][NODE][FOLDER] sw/ 87  3362d 18h csantifort View Log RSS feed

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