Subversion Repositories iqcorrection

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  • Rev 44 2011-03-06 03:23:39 GMT
  • Author: Abraxas3d
  • Log message:
    Here is an exported PDF of the workspace I used to create and test this design. Aldec Active-HDL student edition (version 7.2) was used. This PDF contains the VHDL files and two images of the waveforms. The first image highlights the gain and phase lock behavior. The second image is the first few samples. This implementation has no filter delay because the architecture is implemented with real variables instead of signed registers. This is an intermediate step along the way.
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