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[/] - Rev 14

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  • Rev 14 2019-02-19 15:05:58 GMT
  • Author: ndumitrache
  • Log message:
    Ported on Chameleon V2 board: Cyclone10LP-8, 32MB SDRAM at 185Mhz, 100Mhz bus, 50Mhz CPU, 90Mhz DSP, 8KB cache.
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