Subversion Repositories udp_ipv4_for_10g_ethernet

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  • Rev 3 2017-05-22 07:11:17 GMT
  • Author: DFC
  • Log message:
    Core released for public use on OC.
    It implements mandatory parts of UDP/IPv4 stack for Xilinx 7 series FPGA.
    Created for Vivado 2016.4.
    Released to public as part of Xenie FPGA module support.
    Xenie Module details already available on OC.
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