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[/] [a-z80/] [trunk/] [cpu/] - Rev 22

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Rev Log message Author Age Path
20 Revert "Corrected unconnected enable line" in memory_ifc module. Fixes erroneous extra delay of nIORQ signal on INT ACK. gdevic 2015d 01h /a-z80/trunk/cpu/
19 Some documentation updates gdevic 2026d 05h /a-z80/trunk/cpu/
18 Correctly latch IO RW wait request

Fixed bug: Issuing nWAIT during IO RW was ignored (IORQ, not M1)
Taping into a correct point of IORQ generator sequence train gives
an additional signal to be OR-ed when composing a generic latch_wait

Corrected unconnected enable line
gdevic 2303d 19h /a-z80/trunk/cpu/
17 z80: Release 5 gdevic 2711d 19h /a-z80/trunk/cpu/
16 Simplify by adding nhold_clk_wait

Inverted version is used to feel AND gates to enable
Keep hold_clk_wait used only in the sequencer
gdevic 2744d 10h /a-z80/trunk/cpu/
14 Add hold_clk_wait to ALU CFL latch

This correctly delays latching the C-Flag for CCF instruction when
nWAIT was asserted at that instruction's M1/T2 cycle

UART: fixed two synthesis warnings
gdevic 2744d 22h /a-z80/trunk/cpu/
13 Full support for nWAIT during M1 and memory cycles
This set of changes fixes issues with nWAIT signal
Updated reg control, resets, ir modules to handle delay
This correctly delays clearing of IR if the nWAIT was asserted at
the very first M1 cycle
Simplify decode_state to use discrete write enable for CB/ED flags
Gate CB/ED write with hold_clk_wait to enable nWAIT delay
genfuse add code to test nWAIT insertion at M1
Add host wait state circuitry from Zilog manual (wait_state.*)
Add wait test code to basic fpga/modelsim models
Select from 3 options to test wait states:
- no wait state inserted (nWAIT=1)
- insert a wait state to every M1 cycle
- insert a wait state to each memory access cycle
zxspectrum: Add custom NMI handler and a function to enter game pokes after pressing the NMI button
zxspectrum: Corrected bits 7,5 when reading ULA port 254
zxspectrum: Fix the shift key repeat bug
When using additional keys (<,>,?,...) and shift was released before
a symbol, it would repeat. This change fixes that by correctly resetting
keyboard mask state bitfields.
Added new data pins module for Lattice toolset
It has been reported that "data_pins.v" does not compile on Lattice
toolset and this variation of the code has been proposed and verified
by a user.
Fixed M1 during reset
Memory_ifc module set M1 to inactive (high) during nRESET
Exported wait_m1 signal from that module as a testpoint
gdevic 2745d 19h /a-z80/trunk/cpu/
8 z80: Release 4 gdevic 3017d 07h /a-z80/trunk/cpu/
7 z80: Fixing repeating INIR/OTIR class of instructions gdevic 3081d 11h /a-z80/trunk/cpu/
6 Added deployment folder with all files needed to use the CPU
Changed ZX Spectrum project to use deployment files as example
Changed extension for Verilog include files from *.i to *.vh
Updated documentation; added section on file generators
Minor corrections and fixes to various files
gdevic 3431d 21h /a-z80/trunk/cpu/
3 - New directory structure
- Added documentation files (and PDF versions)
- Fixed tests
gdevic 3467d 12h /a-z80/trunk/cpu/

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