URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] - Rev 49

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
49	Added a note n how to change timeouts	csantifort	5233d 09h	/
48	Fixed a bug in linux that caused the os to not return to the running application after an interrupt. Hello-world now runs stand-alone again. Added initrd-200k-dhry, a disk image that uses the dhry program for init.	csantifort	5237d 15h	/
47	Changed V6 VCo from 1000Mhz to 1200 MHz	csantifort	5257d 13h	/
46	svn ignore vmlinux.dis and vmlinux.mem	csantifort	5265d 11h	/
45	Store vmlinux.mem and vmlinux.dis in compressed form	csantifort	5265d 11h	/
44	Updated vmlinux image based on last change	csantifort	5265d 11h	/
43	Added support for the flat executable file format to vmlinux, so that the hello-world program is correctly relocated when it is loaded at the end of the vmlinux test. Changed the Virtex-5 clock configuration to use a 1200MHz VCO frequency and 80MHz system clock frequency.	csantifort	5265d 11h	/
42	Added write buffer - fixes bug if wishbone writes takes multiple cycles to complete	csantifort	5283d 08h	/
41	Added instructions on how to use Coregen to create the Spartan-6 DDR3 memory interface.	csantifort	5284d 16h	/
40	Added wishbone bus jitter testing option. Cleaned up waveform log .do files, now seperate files for a23 and a25 cores. Added vmlinux executable elf file for running on hardware.	csantifort	5289d 08h	/
39	Added a second level of buffering to a25_wishbone_buf to fix a lockup bug when write acks to not return immediately, and also to improve performance slightly	csantifort	5290d 09h	/
38	support 128-bit wishbone now used for a25 core	csantifort	5291d 09h	/
37	128-bit wide boot memory module	csantifort	5292d 07h	/
36	Changed boot_mem for the a25 system to be 128 bits wide to match the 128-bit wide wishbone bus	csantifort	5292d 08h	/
35	Amber25 improvements: Use 128-bit wishbone bus, instead of 32-bit to reduce cache miss fetch times Use a fast barrel shifter for shifts between 0 and 4 to improve timing Use a 2 cycle full barrel shifter for complex shifts	csantifort	5293d 16h	/
34	Tweaked strcpy function to speed it up slightly	csantifort	5294d 12h	/
33	Fixed bug in div assembly function. Handles negative numbers correctly. Fixed bug in printf function, negative numbers now print correctly.	csantifort	5295d 09h	/
32	Added clock cycle counting register to test_module to support dhrystone performance measurement	csantifort	5296d 09h	/
31	Added dhrystone benchmark test	csantifort	5296d 09h	/
30	Bug fix - a write access was sometimes dropped when it was in a sequence of writes with variable wb_ack delays	csantifort	5309d 15h	/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories amber

[/] - Rev 49

Filtering Options