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Rev Log message Author Age Path
49 Added a note n how to change timeouts csantifort 4860d 23h /
48 Fixed a bug in linux that caused the os to not return to the running application after an interrupt.
Hello-world now runs stand-alone again.
Added initrd-200k-dhry, a disk image that uses the dhry program for init.
csantifort 4865d 05h /
47 Changed V6 VCo from 1000Mhz to 1200 MHz csantifort 4885d 03h /
46 svn ignore vmlinux.dis and vmlinux.mem csantifort 4893d 00h /
45 Store vmlinux.mem and vmlinux.dis in compressed form csantifort 4893d 00h /
44 Updated vmlinux image based on last change csantifort 4893d 01h /
43 Added support for the flat executable file format to vmlinux, so that the hello-world program is correctly relocated when it is loaded at the end of the vmlinux test.
Changed the Virtex-5 clock configuration to use a 1200MHz VCO frequency and 80MHz system clock frequency.
csantifort 4893d 01h /
42 Added write buffer - fixes bug if wishbone writes takes multiple cycles to complete csantifort 4910d 21h /
41 Added instructions on how to use Coregen to create the Spartan-6 DDR3 memory interface. csantifort 4912d 06h /
40 Added wishbone bus jitter testing option.
Cleaned up waveform log .do files, now seperate files for a23 and a25 cores.
Added vmlinux executable elf file for running on hardware.
csantifort 4916d 22h /
39 Added a second level of buffering to a25_wishbone_buf to fix a lockup
bug when write acks to not return immediately, and also to improve performance slightly
csantifort 4917d 23h /
38 support 128-bit wishbone now used for a25 core csantifort 4918d 23h /
37 128-bit wide boot memory module csantifort 4919d 21h /
36 Changed boot_mem for the a25 system to be 128 bits wide to match the 128-bit wide wishbone bus csantifort 4919d 22h /
35 Amber25 improvements:
Use 128-bit wishbone bus, instead of 32-bit to reduce cache miss fetch times
Use a fast barrel shifter for shifts between 0 and 4 to improve timing
Use a 2 cycle full barrel shifter for complex shifts
csantifort 4921d 06h /
34 Tweaked strcpy function to speed it up slightly csantifort 4922d 02h /
33 Fixed bug in div assembly function. Handles negative numbers correctly.
Fixed bug in printf function, negative numbers now print correctly.
csantifort 4922d 22h /
32 Added clock cycle counting register to test_module to support dhrystone performance measurement csantifort 4923d 23h /
31 Added dhrystone benchmark test csantifort 4923d 23h /
30 Bug fix - a write access was sometimes dropped when it was in a sequence of writes with variable wb_ack delays csantifort 4937d 05h /
29 Use lgo command for saving waveforms in modelsim csantifort 4938d 23h /
28 Moved function prototypes to .h file csantifort 4939d 00h /
27 Got working with cadence nc simulator csantifort 4972d 06h /
26 Added wish list csantifort 4977d 06h /
25 Bug fix: boot-loader.mem became larger that the allowed 8k byte boot mem size.
Removed a struct in elfsplitter.c thats only used for debug - this reduced boot-loader.mem enough so that it fits again.
Tidy up: Removed a debug message from hw/tools/run.sh
csantifort 4979d 04h /
24 Added instructions how to build Linux kernel from source files csantifort 4981d 04h /
23 Split the source files list into a Vertex-6 only list and a Spartan-6 only list.
That way users don;t need to delete files from the list manually if they only have
a setup for one of the FPGA types.
csantifort 4981d 05h /
22 Added files and instructions to enable the building of the vmlinux image from the kernel source files. csantifort 4985d 04h /
21 Fixed bug in the conditions to create the FPGA configuration log file. I added the creation of the log file in the last release, but the way it was implemented was causing the Makefile to always rebuild from the start. csantifort 4985d 04h /
20 Added feature to A25 core to directly use a read value from the write back stage
to reduce the stall to 1 cycle when there is a register conflict with the
following instruction. This increases performance by about 3%.
csantifort 5006d 05h /

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