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Rev Log message Author Age Path
69 Updated the spec for ISE 14.5, boot-loader-ethmac. csantifort 4584d 13h /
68 Remove modelsim files. Only supporting Xilinx isim now. csantifort 4584d 13h /
67 renamed boot-loader.c to boot-loader-serial.c csantifort 4584d 13h /
66 Remove the stand-alone ethmac test. Use boot-loader-ethmac instead to verify ethmac functionality. csantifort 4584d 14h /
65 Renamed boot-loader to boot-loader-serial csantifort 4584d 14h /
64 Support latest Xilinx ISE 14.5 software. csantifort 4584d 14h /
63 Add support for Xilinx ISim Verilog simulator.
Remove Virtex-6 files.		 csantifort 4584d 19h /
62 Added source for amber-pkt2mem csantifort 4737d 07h /
61 Add new netowkr based boot loader.
Remove support for Virtex. Spartan 6 only now.		 csantifort 4871d 13h /
60 Bug fix; removed a combinational loop from the a25_decode logic. csantifort 5089d 09h /
59 Added modelsim script for reloading a wlf file after a simulation has been rerun. csantifort 5159d 07h /
58 Use TB.clk_count for the decompiler messages and removed the local counter csantifort 5159d 10h /
57 Add some debug messages csantifort 5159d 10h /
56 Remove the timeouts file from svn. Its an output file and gets now just gets created automatically
when sims are run for the first time.		 csantifort 5159d 10h /
55 Added sudo to rm mnt command csantifort 5159d 10h /
54 Bug fix for bug reported by Botao Lee. The mode bits in the decode stage did not change immediately
after a mode switch from a teqp instruction, but 1 cycle later. This meant the wrong set of registers
was selected for writing to for 1 clock cycle.		 csantifort 5176d 10h /
53 Cleaned up Amber Verilog, removing unused signals. csantifort 5191d 08h /
52 Fixed typo in notes on creating DDR memory interfaces using coregen csantifort 5191d 08h /
51 Revert vmlinux back to 48. csantifort 5232d 07h /
50 Revert to previous version csantifort 5232d 08h /
49 Added a note n how to change timeouts csantifort 5232d 08h /
48 Fixed a bug in linux that caused the os to not return to the running application after an interrupt.
Hello-world now runs stand-alone again.
Added initrd-200k-dhry, a disk image that uses the dhry program for init.		 csantifort 5236d 14h /
47 Changed V6 VCo from 1000Mhz to 1200 MHz csantifort 5256d 11h /
46 svn ignore vmlinux.dis and vmlinux.mem csantifort 5264d 09h /
45 Store vmlinux.mem and vmlinux.dis in compressed form csantifort 5264d 09h /
44 Updated vmlinux image based on last change csantifort 5264d 10h /
43 Added support for the flat executable file format to vmlinux, so that the hello-world program is correctly relocated when it is loaded at the end of the vmlinux test.
Changed the Virtex-5 clock configuration to use a 1200MHz VCO frequency and 80MHz system clock frequency.		 csantifort 5264d 10h /
42 Added write buffer - fixes bug if wishbone writes takes multiple cycles to complete csantifort 5282d 06h /
41 Added instructions on how to use Coregen to create the Spartan-6 DDR3 memory interface. csantifort 5283d 15h /
40 Added wishbone bus jitter testing option.
Cleaned up waveform log .do files, now seperate files for a23 and a25 cores.
Added vmlinux executable elf file for running on hardware.		 csantifort 5288d 07h /

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