OpenCores
URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] - Rev 14

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
14 Re-wrote the behavioral clock generation code to more accurately
calculate the sys_clk frequency. The previous version was not
producing the correct frequency at higher frequenies due to
rounding errors.		 csantifort 5140d 02h /amber/
13 Bug fix - added an extra state to the rx state machine to properly align
reading the uart input to the middle of each bit.		 csantifort 5140d 03h /amber/
12 Added INITIALIZE_TO_ZERO parameter to keep instantiation
idendical to generic sram models. The parameter is not used
in the Xilinx models (they always init to zero) but it used
in the generic models.		 csantifort 5140d 03h /amber/
11 Added vmlinux test. csantifort 5155d 03h /amber/
10 Removed parameters for unused peruipheral modules csantifort 5156d 06h /amber/
9 Change the format of mcr and mrc listings so they exactly match the dissasembly produced by the gnu tools.
Write ip instead of r12 in listings.		 csantifort 5156d 06h /amber/
8 Change the value in the ID register to be compatible with the Linux code that parses it and picks a processor type. csantifort 5156d 06h /amber/
7 Added instructions to use Veritak simulator.
Removed some unused functions from memory_configuration.v.		 csantifort 5164d 21h /amber/
6 Set ignore property for output files csantifort 5168d 00h /amber/
5 Deleted two temporary files that should not be in the release. csantifort 5168d 20h /amber/
4 Corrected a couple of minor typos csantifort 5168d 20h /amber/
3 Added trunk to $AMBER_BASE path csantifort 5169d 00h /amber/
2 Baseline release of the Amber 2 core csantifort 5169d 01h /amber/
1 The project and the structure was created root 5196d 03h /amber/

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.