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Rev Log message Author Age Path
29 Use lgo command for saving waveforms in modelsim csantifort 4965d 09h /amber/
28 Moved function prototypes to .h file csantifort 4965d 09h /amber/
27 Got working with cadence nc simulator csantifort 4998d 16h /amber/
26 Added wish list csantifort 5003d 16h /amber/
25 Bug fix: boot-loader.mem became larger that the allowed 8k byte boot mem size.
Removed a struct in elfsplitter.c thats only used for debug - this reduced boot-loader.mem enough so that it fits again.
Tidy up: Removed a debug message from hw/tools/run.sh		 csantifort 5005d 14h /amber/
24 Added instructions how to build Linux kernel from source files csantifort 5007d 14h /amber/
23 Split the source files list into a Vertex-6 only list and a Spartan-6 only list.
That way users don;t need to delete files from the list manually if they only have
a setup for one of the FPGA types.		 csantifort 5007d 15h /amber/
22 Added files and instructions to enable the building of the vmlinux image from the kernel source files. csantifort 5011d 14h /amber/
21 Fixed bug in the conditions to create the FPGA configuration log file. I added the creation of the log file in the last release, but the way it was implemented was causing the Makefile to always rebuild from the start. csantifort 5011d 14h /amber/
20 Added feature to A25 core to directly use a read value from the write back stage
to reduce the stall to 1 cycle when there is a register conflict with the
following instruction. This increases performance by about 3%.		 csantifort 5032d 15h /amber/
19 Create a configuration log file as part of the synthesis flow. This file is a useful reference to
tell the different bitfiles apart.		 csantifort 5032d 15h /amber/
18 Added list of source files and diagram for Amber25 core. csantifort 5035d 14h /amber/
17 amber25 core bug fix. The return address for irq interrupts was off by 4 bytes
when the interrupt occurred during a stm instruction with the following instruction
having some register conflicts. Added test irq_stm to catch the bug.
Cleaned up some header descriptions		 csantifort 5036d 13h /amber/
16 Deleted the old version of the 3-state amber core. Its replaced with amber23.
Added the 5-state Amber core.		 csantifort 5039d 03h /amber/
15 Copied amber to amber23, Many system changes to support new amber25 core. csantifort 5039d 03h /amber/
14 Re-wrote the behavioral clock generation code to more accurately
calculate the sys_clk frequency. The previous version was not
producing the correct frequency at higher frequenies due to
rounding errors.		 csantifort 5040d 15h /amber/
13 Bug fix - added an extra state to the rx state machine to properly align
reading the uart input to the middle of each bit.		 csantifort 5040d 15h /amber/
12 Added INITIALIZE_TO_ZERO parameter to keep instantiation
idendical to generic sram models. The parameter is not used
in the Xilinx models (they always init to zero) but it used
in the generic models.		 csantifort 5040d 15h /amber/
11 Added vmlinux test. csantifort 5055d 15h /amber/
10 Removed parameters for unused peruipheral modules csantifort 5056d 19h /amber/
9 Change the format of mcr and mrc listings so they exactly match the dissasembly produced by the gnu tools.
Write ip instead of r12 in listings.		 csantifort 5056d 19h /amber/
8 Change the value in the ID register to be compatible with the Linux code that parses it and picks a processor type. csantifort 5056d 19h /amber/
7 Added instructions to use Veritak simulator.
Removed some unused functions from memory_configuration.v.		 csantifort 5065d 10h /amber/
6 Set ignore property for output files csantifort 5068d 13h /amber/
5 Deleted two temporary files that should not be in the release. csantifort 5069d 09h /amber/
4 Corrected a couple of minor typos csantifort 5069d 09h /amber/
3 Added trunk to $AMBER_BASE path csantifort 5069d 13h /amber/
2 Baseline release of the Amber 2 core csantifort 5069d 13h /amber/
1 The project and the structure was created root 5096d 16h /amber/

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