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Rev Log message Author Age Path
41 Added instructions on how to use Coregen to create the Spartan-6 DDR3 memory interface. csantifort 4884d 01h /amber/
40 Added wishbone bus jitter testing option.
Cleaned up waveform log .do files, now seperate files for a23 and a25 cores.
Added vmlinux executable elf file for running on hardware.		 csantifort 4888d 17h /amber/
39 Added a second level of buffering to a25_wishbone_buf to fix a lockup
bug when write acks to not return immediately, and also to improve performance slightly		 csantifort 4889d 18h /amber/
38 support 128-bit wishbone now used for a25 core csantifort 4890d 18h /amber/
37 128-bit wide boot memory module csantifort 4891d 16h /amber/
36 Changed boot_mem for the a25 system to be 128 bits wide to match the 128-bit wide wishbone bus csantifort 4891d 17h /amber/
35 Amber25 improvements:
Use 128-bit wishbone bus, instead of 32-bit to reduce cache miss fetch times
Use a fast barrel shifter for shifts between 0 and 4 to improve timing
Use a 2 cycle full barrel shifter for complex shifts		 csantifort 4893d 01h /amber/
34 Tweaked strcpy function to speed it up slightly csantifort 4893d 21h /amber/
33 Fixed bug in div assembly function. Handles negative numbers correctly.
Fixed bug in printf function, negative numbers now print correctly.		 csantifort 4894d 18h /amber/
32 Added clock cycle counting register to test_module to support dhrystone performance measurement csantifort 4895d 18h /amber/
31 Added dhrystone benchmark test csantifort 4895d 18h /amber/
30 Bug fix - a write access was sometimes dropped when it was in a sequence of writes with variable wb_ack delays csantifort 4909d 01h /amber/
29 Use lgo command for saving waveforms in modelsim csantifort 4910d 18h /amber/
28 Moved function prototypes to .h file csantifort 4910d 19h /amber/
27 Got working with cadence nc simulator csantifort 4944d 01h /amber/
26 Added wish list csantifort 4949d 02h /amber/
25 Bug fix: boot-loader.mem became larger that the allowed 8k byte boot mem size.
Removed a struct in elfsplitter.c thats only used for debug - this reduced boot-loader.mem enough so that it fits again.
Tidy up: Removed a debug message from hw/tools/run.sh		 csantifort 4950d 23h /amber/
24 Added instructions how to build Linux kernel from source files csantifort 4952d 23h /amber/
23 Split the source files list into a Vertex-6 only list and a Spartan-6 only list.
That way users don;t need to delete files from the list manually if they only have
a setup for one of the FPGA types.		 csantifort 4953d 00h /amber/
22 Added files and instructions to enable the building of the vmlinux image from the kernel source files. csantifort 4956d 23h /amber/
21 Fixed bug in the conditions to create the FPGA configuration log file. I added the creation of the log file in the last release, but the way it was implemented was causing the Makefile to always rebuild from the start. csantifort 4956d 23h /amber/
20 Added feature to A25 core to directly use a read value from the write back stage
to reduce the stall to 1 cycle when there is a register conflict with the
following instruction. This increases performance by about 3%.		 csantifort 4978d 00h /amber/
19 Create a configuration log file as part of the synthesis flow. This file is a useful reference to
tell the different bitfiles apart.		 csantifort 4978d 01h /amber/
18 Added list of source files and diagram for Amber25 core. csantifort 4980d 23h /amber/
17 amber25 core bug fix. The return address for irq interrupts was off by 4 bytes
when the interrupt occurred during a stm instruction with the following instruction
having some register conflicts. Added test irq_stm to catch the bug.
Cleaned up some header descriptions		 csantifort 4981d 22h /amber/
16 Deleted the old version of the 3-state amber core. Its replaced with amber23.
Added the 5-state Amber core.		 csantifort 4984d 13h /amber/
15 Copied amber to amber23, Many system changes to support new amber25 core. csantifort 4984d 13h /amber/
14 Re-wrote the behavioral clock generation code to more accurately
calculate the sys_clk frequency. The previous version was not
producing the correct frequency at higher frequenies due to
rounding errors.		 csantifort 4986d 01h /amber/
13 Bug fix - added an extra state to the rx state machine to properly align
reading the uart input to the middle of each bit.		 csantifort 4986d 01h /amber/
12 Added INITIALIZE_TO_ZERO parameter to keep instantiation
idendical to generic sram models. The parameter is not used
in the Xilinx models (they always init to zero) but it used
in the generic models.		 csantifort 4986d 01h /amber/

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