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Rev Log message Author Age Path
60 Bug fix; removed a combinational loop from the a25_decode logic. csantifort 4609d 22h /amber/
59 Added modelsim script for reloading a wlf file after a simulation has been rerun. csantifort 4679d 20h /amber/
58 Use TB.clk_count for the decompiler messages and removed the local counter csantifort 4679d 23h /amber/
57 Add some debug messages csantifort 4679d 23h /amber/
56 Remove the timeouts file from svn. Its an output file and gets now just gets created automatically
when sims are run for the first time.
csantifort 4679d 23h /amber/
55 Added sudo to rm mnt command csantifort 4679d 23h /amber/
54 Bug fix for bug reported by Botao Lee. The mode bits in the decode stage did not change immediately
after a mode switch from a teqp instruction, but 1 cycle later. This meant the wrong set of registers
was selected for writing to for 1 clock cycle.
csantifort 4696d 23h /amber/
53 Cleaned up Amber Verilog, removing unused signals. csantifort 4711d 21h /amber/
52 Fixed typo in notes on creating DDR memory interfaces using coregen csantifort 4711d 21h /amber/
51 Revert vmlinux back to 48. csantifort 4752d 20h /amber/
50 Revert to previous version csantifort 4752d 21h /amber/
49 Added a note n how to change timeouts csantifort 4752d 21h /amber/
48 Fixed a bug in linux that caused the os to not return to the running application after an interrupt.
Hello-world now runs stand-alone again.
Added initrd-200k-dhry, a disk image that uses the dhry program for init.
csantifort 4757d 03h /amber/
47 Changed V6 VCo from 1000Mhz to 1200 MHz csantifort 4777d 00h /amber/
46 svn ignore vmlinux.dis and vmlinux.mem csantifort 4784d 22h /amber/
45 Store vmlinux.mem and vmlinux.dis in compressed form csantifort 4784d 22h /amber/
44 Updated vmlinux image based on last change csantifort 4784d 23h /amber/
43 Added support for the flat executable file format to vmlinux, so that the hello-world program is correctly relocated when it is loaded at the end of the vmlinux test.
Changed the Virtex-5 clock configuration to use a 1200MHz VCO frequency and 80MHz system clock frequency.
csantifort 4784d 23h /amber/
42 Added write buffer - fixes bug if wishbone writes takes multiple cycles to complete csantifort 4802d 19h /amber/
41 Added instructions on how to use Coregen to create the Spartan-6 DDR3 memory interface. csantifort 4804d 04h /amber/

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