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Rev Log message Author Age Path
68 Remove modelsim files. Only supporting Xilinx isim now. csantifort 4105d 03h /amber/
67 renamed boot-loader.c to boot-loader-serial.c csantifort 4105d 03h /amber/
66 Remove the stand-alone ethmac test. Use boot-loader-ethmac instead to verify ethmac functionality. csantifort 4105d 03h /amber/
65 Renamed boot-loader to boot-loader-serial csantifort 4105d 03h /amber/
64 Support latest Xilinx ISE 14.5 software. csantifort 4105d 03h /amber/
63 Add support for Xilinx ISim Verilog simulator.
Remove Virtex-6 files.
csantifort 4105d 08h /amber/
62 Added source for amber-pkt2mem csantifort 4257d 20h /amber/
61 Add new netowkr based boot loader.
Remove support for Virtex. Spartan 6 only now.
csantifort 4392d 02h /amber/
60 Bug fix; removed a combinational loop from the a25_decode logic. csantifort 4609d 22h /amber/
59 Added modelsim script for reloading a wlf file after a simulation has been rerun. csantifort 4679d 20h /amber/
58 Use TB.clk_count for the decompiler messages and removed the local counter csantifort 4679d 23h /amber/
57 Add some debug messages csantifort 4679d 23h /amber/
56 Remove the timeouts file from svn. Its an output file and gets now just gets created automatically
when sims are run for the first time.
csantifort 4679d 23h /amber/
55 Added sudo to rm mnt command csantifort 4679d 23h /amber/
54 Bug fix for bug reported by Botao Lee. The mode bits in the decode stage did not change immediately
after a mode switch from a teqp instruction, but 1 cycle later. This meant the wrong set of registers
was selected for writing to for 1 clock cycle.
csantifort 4696d 23h /amber/
53 Cleaned up Amber Verilog, removing unused signals. csantifort 4711d 21h /amber/
52 Fixed typo in notes on creating DDR memory interfaces using coregen csantifort 4711d 21h /amber/
51 Revert vmlinux back to 48. csantifort 4752d 21h /amber/
50 Revert to previous version csantifort 4752d 21h /amber/
49 Added a note n how to change timeouts csantifort 4752d 21h /amber/

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