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Rev Log message Author Age Path
87 Added support for "When an Operand2 constant is used with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to bit[31] of the constant, if the constant is greater than 255 and can be produced by shifting an 8-bit value" to amber23 csantifort 3526d 17h /amber/
86 Fixed bug in amber 25 where a read was taken from user mode register in subervisor mode immediately following a ldm to user mode registers csantifort 3539d 14h /amber/
85 Fixed bug with accigning the mac address value csantifort 3539d 21h /amber/
84 Fixed some typos - no functional change csantifort 3539d 21h /amber/
83 Fixed bug with carry bit - now only use the carry bit as an input to specific instruments that use it - add with carry and subtract with carry csantifort 3539d 21h /amber/
82 Fixed overflag bug, ldmia user regs bug and status_bits_mode set on non-ececuting command bug csantifort 3553d 09h /amber/
81 Make the tcp functionality more like a normal sockets implementation. csantifort 4217d 11h /amber/
80 Enhanced boot-loader-ethmac to handle any number of telnet connections. csantifort 4231d 13h /amber/
79 Added msc flash file csantifort 4231d 19h /amber/
78 Added a serial debug port (using UART0) to boot-loader-ethmac csantifort 4231d 20h /amber/
77 Added new a23 source files to sim and synthesis source lists. csantifort 4233d 17h /amber/
76 Split the spec document into a processor core spec, and a user guide. csantifort 4233d 17h /amber/
75 Fixed scripts after renaming boot-loader to boot-loader-serial csantifort 4239d 15h /amber/
74 The patch implements barrel shifter using rotate as a main primitive.
The design was optimized for Altera Cyclone III FPGA and can be reused
with other FPGA vendors and products.
The patch integrates the FPGA-optimized barrel shifter into the
Amber 23 core when it is build for Altera FPGA.

The patch reduces footprint from 1178 to 339 LEs keeping Fmax at 57-60 MHz.

Contributed by: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>
csantifort 4239d 15h /amber/
73 The patch introduces a new configuration option `A23_RAM_REGISTER_BANK,
which controls instantiation of Amber 23 register bank.
If the option is set, a ram-based variant of the register bank is instantiated.
It can be useful in low-end FPGA designs, where flipflops and muxes are costly.

Altera Cyclone III resource utilization:
- flipflop-based register bank: 1583 combinationals + 856 registers
- ram-based register bank: 268 combinationals + 156 registers

Contributed by Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>
csantifort 4239d 15h /amber/
72 5 bit "OH_USR" constant was used when 2 bit "USR" should be used.
Both of the constants are 0.
The fault was introduced by ram-based register bank commit.
Contributed by: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>
csantifort 4239d 15h /amber/
71 Original Amber 23 core uses asyncronous implementation of register bank.
It leads to some problems with ram-based implementation of the register bank,
because at least Altera FPGAs uses syncronous ram blocks, so the whole address
needs to be latched.

The patch exposes non-registered versions of register select signals to the
register bank, so the bank can build address and latch it in the syncronous
ram input register.

The patch is a pre-requisite for ram-based register bank implementation on Altera FPGA.

Contributed by Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>
csantifort 4239d 15h /amber/
70 The mlas_bug testcase tried to use stack without setting stack pointer
register, causing unpredictable behavoiur.
The patch uses an expilict stack area for the test.
Contributed by: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>
csantifort 4239d 15h /amber/
69 Updated the spec for ISE 14.5, boot-loader-ethmac. csantifort 4239d 16h /amber/
68 Remove modelsim files. Only supporting Xilinx isim now. csantifort 4239d 16h /amber/

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