URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] - Rev 53

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Rev	Log message	Author	Age	Path
53	Cleaned up Amber Verilog, removing unused signals.	csantifort	4955d 21h	/amber/trunk/
52	Fixed typo in notes on creating DDR memory interfaces using coregen	csantifort	4955d 21h	/amber/trunk/
51	Revert vmlinux back to 48.	csantifort	4996d 21h	/amber/trunk/
50	Revert to previous version	csantifort	4996d 21h	/amber/trunk/
49	Added a note n how to change timeouts	csantifort	4996d 21h	/amber/trunk/
48	Fixed a bug in linux that caused the os to not return to the running application after an interrupt. Hello-world now runs stand-alone again. Added initrd-200k-dhry, a disk image that uses the dhry program for init.	csantifort	5001d 04h	/amber/trunk/
47	Changed V6 VCo from 1000Mhz to 1200 MHz	csantifort	5021d 01h	/amber/trunk/
46	svn ignore vmlinux.dis and vmlinux.mem	csantifort	5028d 23h	/amber/trunk/
45	Store vmlinux.mem and vmlinux.dis in compressed form	csantifort	5028d 23h	/amber/trunk/
44	Updated vmlinux image based on last change	csantifort	5028d 23h	/amber/trunk/
43	Added support for the flat executable file format to vmlinux, so that the hello-world program is correctly relocated when it is loaded at the end of the vmlinux test. Changed the Virtex-5 clock configuration to use a 1200MHz VCO frequency and 80MHz system clock frequency.	csantifort	5028d 23h	/amber/trunk/
42	Added write buffer - fixes bug if wishbone writes takes multiple cycles to complete	csantifort	5046d 20h	/amber/trunk/
41	Added instructions on how to use Coregen to create the Spartan-6 DDR3 memory interface.	csantifort	5048d 04h	/amber/trunk/
40	Added wishbone bus jitter testing option. Cleaned up waveform log .do files, now seperate files for a23 and a25 cores. Added vmlinux executable elf file for running on hardware.	csantifort	5052d 21h	/amber/trunk/
39	Added a second level of buffering to a25_wishbone_buf to fix a lockup bug when write acks to not return immediately, and also to improve performance slightly	csantifort	5053d 22h	/amber/trunk/
38	support 128-bit wishbone now used for a25 core	csantifort	5054d 21h	/amber/trunk/
37	128-bit wide boot memory module	csantifort	5055d 20h	/amber/trunk/
36	Changed boot_mem for the a25 system to be 128 bits wide to match the 128-bit wide wishbone bus	csantifort	5055d 21h	/amber/trunk/
35	Amber25 improvements: Use 128-bit wishbone bus, instead of 32-bit to reduce cache miss fetch times Use a fast barrel shifter for shifts between 0 and 4 to improve timing Use a 2 cycle full barrel shifter for complex shifts	csantifort	5057d 04h	/amber/trunk/
34	Tweaked strcpy function to speed it up slightly	csantifort	5058d 01h	/amber/trunk/

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[/] [amber/] [trunk/] - Rev 53

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