OpenCores
URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] - Rev 69

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
69 Updated the spec for ISE 14.5, boot-loader-ethmac. csantifort 4606d 14h /amber/trunk/
68 Remove modelsim files. Only supporting Xilinx isim now. csantifort 4606d 15h /amber/trunk/
67 renamed boot-loader.c to boot-loader-serial.c csantifort 4606d 15h /amber/trunk/
66 Remove the stand-alone ethmac test. Use boot-loader-ethmac instead to verify ethmac functionality. csantifort 4606d 16h /amber/trunk/
65 Renamed boot-loader to boot-loader-serial csantifort 4606d 16h /amber/trunk/
64 Support latest Xilinx ISE 14.5 software. csantifort 4606d 16h /amber/trunk/
63 Add support for Xilinx ISim Verilog simulator.
Remove Virtex-6 files.
csantifort 4606d 20h /amber/trunk/
62 Added source for amber-pkt2mem csantifort 4759d 09h /amber/trunk/
61 Add new netowkr based boot loader.
Remove support for Virtex. Spartan 6 only now.
csantifort 4893d 15h /amber/trunk/
60 Bug fix; removed a combinational loop from the a25_decode logic. csantifort 5111d 11h /amber/trunk/
59 Added modelsim script for reloading a wlf file after a simulation has been rerun. csantifort 5181d 08h /amber/trunk/
58 Use TB.clk_count for the decompiler messages and removed the local counter csantifort 5181d 12h /amber/trunk/
57 Add some debug messages csantifort 5181d 12h /amber/trunk/
56 Remove the timeouts file from svn. Its an output file and gets now just gets created automatically
when sims are run for the first time.
csantifort 5181d 12h /amber/trunk/
55 Added sudo to rm mnt command csantifort 5181d 12h /amber/trunk/
54 Bug fix for bug reported by Botao Lee. The mode bits in the decode stage did not change immediately
after a mode switch from a teqp instruction, but 1 cycle later. This meant the wrong set of registers
was selected for writing to for 1 clock cycle.
csantifort 5198d 11h /amber/trunk/
53 Cleaned up Amber Verilog, removing unused signals. csantifort 5213d 09h /amber/trunk/
52 Fixed typo in notes on creating DDR memory interfaces using coregen csantifort 5213d 09h /amber/trunk/
51 Revert vmlinux back to 48. csantifort 5254d 09h /amber/trunk/
50 Revert to previous version csantifort 5254d 09h /amber/trunk/
49 Added a note n how to change timeouts csantifort 5254d 09h /amber/trunk/
48 Fixed a bug in linux that caused the os to not return to the running application after an interrupt.
Hello-world now runs stand-alone again.
Added initrd-200k-dhry, a disk image that uses the dhry program for init.
csantifort 5258d 16h /amber/trunk/
47 Changed V6 VCo from 1000Mhz to 1200 MHz csantifort 5278d 13h /amber/trunk/
46 svn ignore vmlinux.dis and vmlinux.mem csantifort 5286d 11h /amber/trunk/
45 Store vmlinux.mem and vmlinux.dis in compressed form csantifort 5286d 11h /amber/trunk/
44 Updated vmlinux image based on last change csantifort 5286d 11h /amber/trunk/
43 Added support for the flat executable file format to vmlinux, so that the hello-world program is correctly relocated when it is loaded at the end of the vmlinux test.
Changed the Virtex-5 clock configuration to use a 1200MHz VCO frequency and 80MHz system clock frequency.
csantifort 5286d 11h /amber/trunk/
42 Added write buffer - fixes bug if wishbone writes takes multiple cycles to complete csantifort 5304d 08h /amber/trunk/
41 Added instructions on how to use Coregen to create the Spartan-6 DDR3 memory interface. csantifort 5305d 16h /amber/trunk/
40 Added wishbone bus jitter testing option.
Cleaned up waveform log .do files, now seperate files for a23 and a25 cores.
Added vmlinux executable elf file for running on hardware.
csantifort 5310d 09h /amber/trunk/

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.