URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] - Rev 53

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Rev	Log message	Author	Age	Path
53	Cleaned up Amber Verilog, removing unused signals.	csantifort	5222d 06h	/amber/trunk/hw/
52	Fixed typo in notes on creating DDR memory interfaces using coregen	csantifort	5222d 06h	/amber/trunk/hw/
50	Revert to previous version	csantifort	5263d 06h	/amber/trunk/hw/
49	Added a note n how to change timeouts	csantifort	5263d 06h	/amber/trunk/hw/
48	Fixed a bug in linux that caused the os to not return to the running application after an interrupt. Hello-world now runs stand-alone again. Added initrd-200k-dhry, a disk image that uses the dhry program for init.	csantifort	5267d 13h	/amber/trunk/hw/
47	Changed V6 VCo from 1000Mhz to 1200 MHz	csantifort	5287d 10h	/amber/trunk/hw/
45	Store vmlinux.mem and vmlinux.dis in compressed form	csantifort	5295d 08h	/amber/trunk/hw/
43	Added support for the flat executable file format to vmlinux, so that the hello-world program is correctly relocated when it is loaded at the end of the vmlinux test. Changed the Virtex-5 clock configuration to use a 1200MHz VCO frequency and 80MHz system clock frequency.	csantifort	5295d 08h	/amber/trunk/hw/
42	Added write buffer - fixes bug if wishbone writes takes multiple cycles to complete	csantifort	5313d 05h	/amber/trunk/hw/
41	Added instructions on how to use Coregen to create the Spartan-6 DDR3 memory interface.	csantifort	5314d 13h	/amber/trunk/hw/
40	Added wishbone bus jitter testing option. Cleaned up waveform log .do files, now seperate files for a23 and a25 cores. Added vmlinux executable elf file for running on hardware.	csantifort	5319d 06h	/amber/trunk/hw/
39	Added a second level of buffering to a25_wishbone_buf to fix a lockup bug when write acks to not return immediately, and also to improve performance slightly	csantifort	5320d 06h	/amber/trunk/hw/
38	support 128-bit wishbone now used for a25 core	csantifort	5321d 06h	/amber/trunk/hw/
37	128-bit wide boot memory module	csantifort	5322d 04h	/amber/trunk/hw/
36	Changed boot_mem for the a25 system to be 128 bits wide to match the 128-bit wide wishbone bus	csantifort	5322d 05h	/amber/trunk/hw/
35	Amber25 improvements: Use 128-bit wishbone bus, instead of 32-bit to reduce cache miss fetch times Use a fast barrel shifter for shifts between 0 and 4 to improve timing Use a 2 cycle full barrel shifter for complex shifts	csantifort	5323d 13h	/amber/trunk/hw/
32	Added clock cycle counting register to test_module to support dhrystone performance measurement	csantifort	5326d 06h	/amber/trunk/hw/
30	Bug fix - a write access was sometimes dropped when it was in a sequence of writes with variable wb_ack delays	csantifort	5339d 13h	/amber/trunk/hw/
29	Use lgo command for saving waveforms in modelsim	csantifort	5341d 06h	/amber/trunk/hw/
27	Got working with cadence nc simulator	csantifort	5374d 14h	/amber/trunk/hw/

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[/] [amber/] [trunk/] [hw/] - Rev 53

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