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[/] [amber/] [trunk/] [hw/] - Rev 62

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Rev	Log message	Author	Age	Path
61	Add new netowkr based boot loader. Remove support for Virtex. Spartan 6 only now.	csantifort	4626d 00h	/amber/trunk/hw/
60	Bug fix; removed a combinational loop from the a25_decode logic.	csantifort	4843d 20h	/amber/trunk/hw/
59	Added modelsim script for reloading a wlf file after a simulation has been rerun.	csantifort	4913d 18h	/amber/trunk/hw/
58	Use TB.clk_count for the decompiler messages and removed the local counter	csantifort	4913d 21h	/amber/trunk/hw/
57	Add some debug messages	csantifort	4913d 21h	/amber/trunk/hw/
56	Remove the timeouts file from svn. Its an output file and gets now just gets created automatically when sims are run for the first time.	csantifort	4913d 21h	/amber/trunk/hw/
54	Bug fix for bug reported by Botao Lee. The mode bits in the decode stage did not change immediately after a mode switch from a teqp instruction, but 1 cycle later. This meant the wrong set of registers was selected for writing to for 1 clock cycle.	csantifort	4930d 21h	/amber/trunk/hw/
53	Cleaned up Amber Verilog, removing unused signals.	csantifort	4945d 19h	/amber/trunk/hw/
52	Fixed typo in notes on creating DDR memory interfaces using coregen	csantifort	4945d 19h	/amber/trunk/hw/
50	Revert to previous version	csantifort	4986d 19h	/amber/trunk/hw/
49	Added a note n how to change timeouts	csantifort	4986d 19h	/amber/trunk/hw/
48	Fixed a bug in linux that caused the os to not return to the running application after an interrupt. Hello-world now runs stand-alone again. Added initrd-200k-dhry, a disk image that uses the dhry program for init.	csantifort	4991d 01h	/amber/trunk/hw/
47	Changed V6 VCo from 1000Mhz to 1200 MHz	csantifort	5010d 23h	/amber/trunk/hw/
45	Store vmlinux.mem and vmlinux.dis in compressed form	csantifort	5018d 21h	/amber/trunk/hw/
43	Added support for the flat executable file format to vmlinux, so that the hello-world program is correctly relocated when it is loaded at the end of the vmlinux test. Changed the Virtex-5 clock configuration to use a 1200MHz VCO frequency and 80MHz system clock frequency.	csantifort	5018d 21h	/amber/trunk/hw/
42	Added write buffer - fixes bug if wishbone writes takes multiple cycles to complete	csantifort	5036d 17h	/amber/trunk/hw/
41	Added instructions on how to use Coregen to create the Spartan-6 DDR3 memory interface.	csantifort	5038d 02h	/amber/trunk/hw/
40	Added wishbone bus jitter testing option. Cleaned up waveform log .do files, now seperate files for a23 and a25 cores. Added vmlinux executable elf file for running on hardware.	csantifort	5042d 18h	/amber/trunk/hw/
39	Added a second level of buffering to a25_wishbone_buf to fix a lockup bug when write acks to not return immediately, and also to improve performance slightly	csantifort	5043d 19h	/amber/trunk/hw/
38	support 128-bit wishbone now used for a25 core	csantifort	5044d 19h	/amber/trunk/hw/

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[/] [amber/] [trunk/] [hw/] - Rev 62

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