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[/] [amber/] [trunk/] [hw/] - Rev 63

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Rev Log message Author Age Path
63 Add support for Xilinx ISim Verilog simulator.
Remove Virtex-6 files.
csantifort 4304d 09h /amber/trunk/hw/
61 Add new netowkr based boot loader.
Remove support for Virtex. Spartan 6 only now.
csantifort 4591d 03h /amber/trunk/hw/
60 Bug fix; removed a combinational loop from the a25_decode logic. csantifort 4809d 00h /amber/trunk/hw/
59 Added modelsim script for reloading a wlf file after a simulation has been rerun. csantifort 4878d 21h /amber/trunk/hw/
58 Use TB.clk_count for the decompiler messages and removed the local counter csantifort 4879d 01h /amber/trunk/hw/
57 Add some debug messages csantifort 4879d 01h /amber/trunk/hw/
56 Remove the timeouts file from svn. Its an output file and gets now just gets created automatically
when sims are run for the first time.
csantifort 4879d 01h /amber/trunk/hw/
54 Bug fix for bug reported by Botao Lee. The mode bits in the decode stage did not change immediately
after a mode switch from a teqp instruction, but 1 cycle later. This meant the wrong set of registers
was selected for writing to for 1 clock cycle.
csantifort 4896d 00h /amber/trunk/hw/
53 Cleaned up Amber Verilog, removing unused signals. csantifort 4910d 22h /amber/trunk/hw/
52 Fixed typo in notes on creating DDR memory interfaces using coregen csantifort 4910d 22h /amber/trunk/hw/
50 Revert to previous version csantifort 4951d 22h /amber/trunk/hw/
49 Added a note n how to change timeouts csantifort 4951d 22h /amber/trunk/hw/
48 Fixed a bug in linux that caused the os to not return to the running application after an interrupt.
Hello-world now runs stand-alone again.
Added initrd-200k-dhry, a disk image that uses the dhry program for init.
csantifort 4956d 05h /amber/trunk/hw/
47 Changed V6 VCo from 1000Mhz to 1200 MHz csantifort 4976d 02h /amber/trunk/hw/
45 Store vmlinux.mem and vmlinux.dis in compressed form csantifort 4984d 00h /amber/trunk/hw/
43 Added support for the flat executable file format to vmlinux, so that the hello-world program is correctly relocated when it is loaded at the end of the vmlinux test.
Changed the Virtex-5 clock configuration to use a 1200MHz VCO frequency and 80MHz system clock frequency.
csantifort 4984d 00h /amber/trunk/hw/
42 Added write buffer - fixes bug if wishbone writes takes multiple cycles to complete csantifort 5001d 21h /amber/trunk/hw/
41 Added instructions on how to use Coregen to create the Spartan-6 DDR3 memory interface. csantifort 5003d 05h /amber/trunk/hw/
40 Added wishbone bus jitter testing option.
Cleaned up waveform log .do files, now seperate files for a23 and a25 cores.
Added vmlinux executable elf file for running on hardware.
csantifort 5007d 22h /amber/trunk/hw/
39 Added a second level of buffering to a25_wishbone_buf to fix a lockup
bug when write acks to not return immediately, and also to improve performance slightly
csantifort 5008d 22h /amber/trunk/hw/
38 support 128-bit wishbone now used for a25 core csantifort 5009d 22h /amber/trunk/hw/
37 128-bit wide boot memory module csantifort 5010d 20h /amber/trunk/hw/
36 Changed boot_mem for the a25 system to be 128 bits wide to match the 128-bit wide wishbone bus csantifort 5010d 21h /amber/trunk/hw/
35 Amber25 improvements:
Use 128-bit wishbone bus, instead of 32-bit to reduce cache miss fetch times
Use a fast barrel shifter for shifts between 0 and 4 to improve timing
Use a 2 cycle full barrel shifter for complex shifts
csantifort 5012d 05h /amber/trunk/hw/
32 Added clock cycle counting register to test_module to support dhrystone performance measurement csantifort 5014d 22h /amber/trunk/hw/
30 Bug fix - a write access was sometimes dropped when it was in a sequence of writes with variable wb_ack delays csantifort 5028d 05h /amber/trunk/hw/
29 Use lgo command for saving waveforms in modelsim csantifort 5029d 22h /amber/trunk/hw/
27 Got working with cadence nc simulator csantifort 5063d 06h /amber/trunk/hw/
25 Bug fix: boot-loader.mem became larger that the allowed 8k byte boot mem size.
Removed a struct in elfsplitter.c thats only used for debug - this reduced boot-loader.mem enough so that it fits again.
Tidy up: Removed a debug message from hw/tools/run.sh
csantifort 5070d 03h /amber/trunk/hw/
23 Split the source files list into a Vertex-6 only list and a Spartan-6 only list.
That way users don;t need to delete files from the list manually if they only have
a setup for one of the FPGA types.
csantifort 5072d 04h /amber/trunk/hw/

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