| Rev |
Log message |
Author |
Age |
Path |
| 80 |
Enhanced boot-loader-ethmac to handle any number of telnet connections. |
csantifort |
4153d 10h |
/amber/trunk/hw/ |
| 79 |
Added msc flash file |
csantifort |
4153d 15h |
/amber/trunk/hw/ |
| 78 |
Added a serial debug port (using UART0) to boot-loader-ethmac |
csantifort |
4153d 16h |
/amber/trunk/hw/ |
| 77 |
Added new a23 source files to sim and synthesis source lists. |
csantifort |
4155d 13h |
/amber/trunk/hw/ |
| 75 |
Fixed scripts after renaming boot-loader to boot-loader-serial |
csantifort |
4161d 11h |
/amber/trunk/hw/ |
| 74 |
The patch implements barrel shifter using rotate as a main primitive.
The design was optimized for Altera Cyclone III FPGA and can be reused
with other FPGA vendors and products.
The patch integrates the FPGA-optimized barrel shifter into the
Amber 23 core when it is build for Altera FPGA.
The patch reduces footprint from 1178 to 339 LEs keeping Fmax at 57-60 MHz.
Contributed by: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no> |
csantifort |
4161d 11h |
/amber/trunk/hw/ |
| 73 |
The patch introduces a new configuration option `A23_RAM_REGISTER_BANK,
which controls instantiation of Amber 23 register bank.
If the option is set, a ram-based variant of the register bank is instantiated.
It can be useful in low-end FPGA designs, where flipflops and muxes are costly.
Altera Cyclone III resource utilization:
- flipflop-based register bank: 1583 combinationals + 856 registers
- ram-based register bank: 268 combinationals + 156 registers
Contributed by Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no> |
csantifort |
4161d 11h |
/amber/trunk/hw/ |
| 72 |
5 bit "OH_USR" constant was used when 2 bit "USR" should be used.
Both of the constants are 0.
The fault was introduced by ram-based register bank commit.
Contributed by: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no> |
csantifort |
4161d 11h |
/amber/trunk/hw/ |
| 71 |
Original Amber 23 core uses asyncronous implementation of register bank.
It leads to some problems with ram-based implementation of the register bank,
because at least Altera FPGAs uses syncronous ram blocks, so the whole address
needs to be latched.
The patch exposes non-registered versions of register select signals to the
register bank, so the bank can build address and latch it in the syncronous
ram input register.
The patch is a pre-requisite for ram-based register bank implementation on Altera FPGA.
Contributed by Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no> |
csantifort |
4161d 12h |
/amber/trunk/hw/ |
| 70 |
The mlas_bug testcase tried to use stack without setting stack pointer
register, causing unpredictable behavoiur.
The patch uses an expilict stack area for the test.
Contributed by: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no> |
csantifort |
4161d 12h |
/amber/trunk/hw/ |
| 68 |
Remove modelsim files. Only supporting Xilinx isim now. |
csantifort |
4161d 12h |
/amber/trunk/hw/ |
| 67 |
renamed boot-loader.c to boot-loader-serial.c |
csantifort |
4161d 12h |
/amber/trunk/hw/ |
| 64 |
Support latest Xilinx ISE 14.5 software. |
csantifort |
4161d 13h |
/amber/trunk/hw/ |
| 63 |
Add support for Xilinx ISim Verilog simulator.
Remove Virtex-6 files. |
csantifort |
4161d 18h |
/amber/trunk/hw/ |
| 61 |
Add new netowkr based boot loader.
Remove support for Virtex. Spartan 6 only now. |
csantifort |
4448d 12h |
/amber/trunk/hw/ |
| 60 |
Bug fix; removed a combinational loop from the a25_decode logic. |
csantifort |
4666d 08h |
/amber/trunk/hw/ |
| 59 |
Added modelsim script for reloading a wlf file after a simulation has been rerun. |
csantifort |
4736d 06h |
/amber/trunk/hw/ |
| 58 |
Use TB.clk_count for the decompiler messages and removed the local counter |
csantifort |
4736d 09h |
/amber/trunk/hw/ |
| 57 |
Add some debug messages |
csantifort |
4736d 09h |
/amber/trunk/hw/ |
| 56 |
Remove the timeouts file from svn. Its an output file and gets now just gets created automatically
when sims are run for the first time. |
csantifort |
4736d 09h |
/amber/trunk/hw/ |
| 54 |
Bug fix for bug reported by Botao Lee. The mode bits in the decode stage did not change immediately
after a mode switch from a teqp instruction, but 1 cycle later. This meant the wrong set of registers
was selected for writing to for 1 clock cycle. |
csantifort |
4753d 09h |
/amber/trunk/hw/ |
| 53 |
Cleaned up Amber Verilog, removing unused signals. |
csantifort |
4768d 07h |
/amber/trunk/hw/ |
| 52 |
Fixed typo in notes on creating DDR memory interfaces using coregen |
csantifort |
4768d 07h |
/amber/trunk/hw/ |
| 50 |
Revert to previous version |
csantifort |
4809d 07h |
/amber/trunk/hw/ |
| 49 |
Added a note n how to change timeouts |
csantifort |
4809d 07h |
/amber/trunk/hw/ |
| 48 |
Fixed a bug in linux that caused the os to not return to the running application after an interrupt.
Hello-world now runs stand-alone again.
Added initrd-200k-dhry, a disk image that uses the dhry program for init. |
csantifort |
4813d 13h |
/amber/trunk/hw/ |
| 47 |
Changed V6 VCo from 1000Mhz to 1200 MHz |
csantifort |
4833d 10h |
/amber/trunk/hw/ |
| 45 |
Store vmlinux.mem and vmlinux.dis in compressed form |
csantifort |
4841d 08h |
/amber/trunk/hw/ |
| 43 |
Added support for the flat executable file format to vmlinux, so that the hello-world program is correctly relocated when it is loaded at the end of the vmlinux test.
Changed the Virtex-5 clock configuration to use a 1200MHz VCO frequency and 80MHz system clock frequency. |
csantifort |
4841d 09h |
/amber/trunk/hw/ |
| 42 |
Added write buffer - fixes bug if wishbone writes takes multiple cycles to complete |
csantifort |
4859d 05h |
/amber/trunk/hw/ |
