URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] - Rev 89

Rev	Log message	Author	Age	Path
64	Support latest Xilinx ISE 14.5 software.	csantifort	4342d 12h	/amber/trunk/hw
63	Add support for Xilinx ISim Verilog simulator. Remove Virtex-6 files.	csantifort	4342d 17h	/amber/trunk/hw
61	Add new netowkr based boot loader. Remove support for Virtex. Spartan 6 only now.	csantifort	4629d 11h	/amber/trunk/hw
60	Bug fix; removed a combinational loop from the a25_decode logic.	csantifort	4847d 07h	/amber/trunk/hw
59	Added modelsim script for reloading a wlf file after a simulation has been rerun.	csantifort	4917d 05h	/amber/trunk/hw
58	Use TB.clk_count for the decompiler messages and removed the local counter	csantifort	4917d 08h	/amber/trunk/hw
57	Add some debug messages	csantifort	4917d 08h	/amber/trunk/hw
56	Remove the timeouts file from svn. Its an output file and gets now just gets created automatically when sims are run for the first time.	csantifort	4917d 08h	/amber/trunk/hw
54	Bug fix for bug reported by Botao Lee. The mode bits in the decode stage did not change immediately after a mode switch from a teqp instruction, but 1 cycle later. This meant the wrong set of registers was selected for writing to for 1 clock cycle.	csantifort	4934d 08h	/amber/trunk/hw
53	Cleaned up Amber Verilog, removing unused signals.	csantifort	4949d 06h	/amber/trunk/hw