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[/] [amber/] [trunk/] [hw/] [fpga/] [bin/] [xs6_source_files.prj] - Rev 63

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63 Add support for Xilinx ISim Verilog simulator.
Remove Virtex-6 files.
csantifort 4242d 01h /amber/trunk/hw/fpga/bin/xs6_source_files.prj
61 Add new netowkr based boot loader.
Remove support for Virtex. Spartan 6 only now.
csantifort 4528d 20h /amber/trunk/hw/fpga/bin/xs6_source_files.prj
36 Changed boot_mem for the a25 system to be 128 bits wide to match the 128-bit wide wishbone bus csantifort 4948d 14h /amber/trunk/hw/fpga/bin/xs6_source_files.prj
35 Amber25 improvements:
Use 128-bit wishbone bus, instead of 32-bit to reduce cache miss fetch times
Use a fast barrel shifter for shifts between 0 and 4 to improve timing
Use a 2 cycle full barrel shifter for complex shifts
csantifort 4949d 21h /amber/trunk/hw/fpga/bin/xs6_source_files.prj
23 Split the source files list into a Vertex-6 only list and a Spartan-6 only list.
That way users don;t need to delete files from the list manually if they only have
a setup for one of the FPGA types.
csantifort 5009d 21h /amber/trunk/hw/fpga/bin/xs6_source_files.prj
15 Copied amber to amber23, Many system changes to support new amber25 core. csantifort 5041d 09h /amber/trunk/hw/fpga/bin/source_files.prj
2 Baseline release of the Amber 2 core csantifort 5071d 19h /amber/trunk/hw/fpga/bin/source_files.prj

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