OpenCores
URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] [tests/] - Rev 87

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
87 Added support for "When an Operand2 constant is used with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to bit[31] of the constant, if the constant is greater than 255 and can be produced by shifting an 8-bit value" to amber23 csantifort 3573d 02h /amber/trunk/hw/tests/
86 Fixed bug in amber 25 where a read was taken from user mode register in subervisor mode immediately following a ldm to user mode registers csantifort 3585d 23h /amber/trunk/hw/tests/
83 Fixed bug with carry bit - now only use the carry bit as an input to specific instruments that use it - add with carry and subtract with carry csantifort 3586d 06h /amber/trunk/hw/tests/
82 Fixed overflag bug, ldmia user regs bug and status_bits_mode set on non-ececuting command bug csantifort 3599d 18h /amber/trunk/hw/tests/
70 The mlas_bug testcase tried to use stack without setting stack pointer
register, causing unpredictable behavoiur.
The patch uses an expilict stack area for the test.
Contributed by: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>
csantifort 4286d 00h /amber/trunk/hw/tests/
60 Bug fix; removed a combinational loop from the a25_decode logic. csantifort 4790d 21h /amber/trunk/hw/tests/
56 Remove the timeouts file from svn. Its an output file and gets now just gets created automatically
when sims are run for the first time.
csantifort 4860d 22h /amber/trunk/hw/tests/
54 Bug fix for bug reported by Botao Lee. The mode bits in the decode stage did not change immediately
after a mode switch from a teqp instruction, but 1 cycle later. This meant the wrong set of registers
was selected for writing to for 1 clock cycle.
csantifort 4877d 22h /amber/trunk/hw/tests/
50 Revert to previous version csantifort 4933d 19h /amber/trunk/hw/tests/
49 Added a note n how to change timeouts csantifort 4933d 20h /amber/trunk/hw/tests/
48 Fixed a bug in linux that caused the os to not return to the running application after an interrupt.
Hello-world now runs stand-alone again.
Added initrd-200k-dhry, a disk image that uses the dhry program for init.
csantifort 4938d 02h /amber/trunk/hw/tests/
40 Added wishbone bus jitter testing option.
Cleaned up waveform log .do files, now seperate files for a23 and a25 cores.
Added vmlinux executable elf file for running on hardware.
csantifort 4989d 19h /amber/trunk/hw/tests/
36 Changed boot_mem for the a25 system to be 128 bits wide to match the 128-bit wide wishbone bus csantifort 4992d 19h /amber/trunk/hw/tests/
35 Amber25 improvements:
Use 128-bit wishbone bus, instead of 32-bit to reduce cache miss fetch times
Use a fast barrel shifter for shifts between 0 and 4 to improve timing
Use a 2 cycle full barrel shifter for complex shifts
csantifort 4994d 02h /amber/trunk/hw/tests/
20 Added feature to A25 core to directly use a read value from the write back stage
to reduce the stall to 1 cycle when there is a register conflict with the
following instruction. This increases performance by about 3%.
csantifort 5079d 02h /amber/trunk/hw/tests/
17 amber25 core bug fix. The return address for irq interrupts was off by 4 bytes
when the interrupt occurred during a stm instruction with the following instruction
having some register conflicts. Added test irq_stm to catch the bug.
Cleaned up some header descriptions
csantifort 5083d 00h /amber/trunk/hw/tests/
15 Copied amber to amber23, Many system changes to support new amber25 core. csantifort 5085d 14h /amber/trunk/hw/tests/
11 Added vmlinux test. csantifort 5102d 02h /amber/trunk/hw/tests/
6 Set ignore property for output files csantifort 5115d 00h /amber/trunk/hw/tests/
2 Baseline release of the Amber 2 core csantifort 5116d 00h /amber/trunk/hw/tests/

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.