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[/] [amber/] [trunk/] [hw/] [vlog/] - Rev 40

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Rev	Log message	Author	Age	Path
40	Added wishbone bus jitter testing option. Cleaned up waveform log .do files, now seperate files for a23 and a25 cores. Added vmlinux executable elf file for running on hardware.	csantifort	5161d 17h	/amber/trunk/hw/vlog/
39	Added a second level of buffering to a25_wishbone_buf to fix a lockup bug when write acks to not return immediately, and also to improve performance slightly	csantifort	5162d 18h	/amber/trunk/hw/vlog/
38	support 128-bit wishbone now used for a25 core	csantifort	5163d 18h	/amber/trunk/hw/vlog/
37	128-bit wide boot memory module	csantifort	5164d 16h	/amber/trunk/hw/vlog/
36	Changed boot_mem for the a25 system to be 128 bits wide to match the 128-bit wide wishbone bus	csantifort	5164d 17h	/amber/trunk/hw/vlog/
35	Amber25 improvements: Use 128-bit wishbone bus, instead of 32-bit to reduce cache miss fetch times Use a fast barrel shifter for shifts between 0 and 4 to improve timing Use a 2 cycle full barrel shifter for complex shifts	csantifort	5166d 00h	/amber/trunk/hw/vlog/
32	Added clock cycle counting register to test_module to support dhrystone performance measurement	csantifort	5168d 17h	/amber/trunk/hw/vlog/
30	Bug fix - a write access was sometimes dropped when it was in a sequence of writes with variable wb_ack delays	csantifort	5182d 00h	/amber/trunk/hw/vlog/
27	Got working with cadence nc simulator	csantifort	5217d 01h	/amber/trunk/hw/vlog/
20	Added feature to A25 core to directly use a read value from the write back stage to reduce the stall to 1 cycle when there is a register conflict with the following instruction. This increases performance by about 3%.	csantifort	5251d 00h	/amber/trunk/hw/vlog/
17	amber25 core bug fix. The return address for irq interrupts was off by 4 bytes when the interrupt occurred during a stm instruction with the following instruction having some register conflicts. Added test irq_stm to catch the bug. Cleaned up some header descriptions	csantifort	5254d 22h	/amber/trunk/hw/vlog/
16	Deleted the old version of the 3-state amber core. Its replaced with amber23. Added the 5-state Amber core.	csantifort	5257d 12h	/amber/trunk/hw/vlog/
15	Copied amber to amber23, Many system changes to support new amber25 core.	csantifort	5257d 12h	/amber/trunk/hw/vlog/
14	Re-wrote the behavioral clock generation code to more accurately calculate the sys_clk frequency. The previous version was not producing the correct frequency at higher frequenies due to rounding errors.	csantifort	5259d 00h	/amber/trunk/hw/vlog/
13	Bug fix - added an extra state to the rx state machine to properly align reading the uart input to the middle of each bit.	csantifort	5259d 00h	/amber/trunk/hw/vlog/
12	Added INITIALIZE_TO_ZERO parameter to keep instantiation idendical to generic sram models. The parameter is not used in the Xilinx models (they always init to zero) but it used in the generic models.	csantifort	5259d 00h	/amber/trunk/hw/vlog/
11	Added vmlinux test.	csantifort	5274d 00h	/amber/trunk/hw/vlog/
10	Removed parameters for unused peruipheral modules	csantifort	5275d 04h	/amber/trunk/hw/vlog/
9	Change the format of mcr and mrc listings so they exactly match the dissasembly produced by the gnu tools. Write ip instead of r12 in listings.	csantifort	5275d 04h	/amber/trunk/hw/vlog/
8	Change the value in the ID register to be compatible with the Linux code that parses it and picks a processor type.	csantifort	5275d 04h	/amber/trunk/hw/vlog/

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[/] [amber/] [trunk/] [hw/] [vlog/] - Rev 40

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