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[/] [amber/] [trunk/] [hw/] [vlog/] - Rev 61

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Rev	Log message	Author	Age	Path
61	Add new netowkr based boot loader. Remove support for Virtex. Spartan 6 only now.	csantifort	4636d 11h	/amber/trunk/hw/vlog/
60	Bug fix; removed a combinational loop from the a25_decode logic.	csantifort	4854d 07h	/amber/trunk/hw/vlog/
58	Use TB.clk_count for the decompiler messages and removed the local counter	csantifort	4924d 08h	/amber/trunk/hw/vlog/
57	Add some debug messages	csantifort	4924d 08h	/amber/trunk/hw/vlog/
54	Bug fix for bug reported by Botao Lee. The mode bits in the decode stage did not change immediately after a mode switch from a teqp instruction, but 1 cycle later. This meant the wrong set of registers was selected for writing to for 1 clock cycle.	csantifort	4941d 08h	/amber/trunk/hw/vlog/
53	Cleaned up Amber Verilog, removing unused signals.	csantifort	4956d 06h	/amber/trunk/hw/vlog/
52	Fixed typo in notes on creating DDR memory interfaces using coregen	csantifort	4956d 06h	/amber/trunk/hw/vlog/
49	Added a note n how to change timeouts	csantifort	4997d 06h	/amber/trunk/hw/vlog/
47	Changed V6 VCo from 1000Mhz to 1200 MHz	csantifort	5021d 10h	/amber/trunk/hw/vlog/
43	Added support for the flat executable file format to vmlinux, so that the hello-world program is correctly relocated when it is loaded at the end of the vmlinux test. Changed the Virtex-5 clock configuration to use a 1200MHz VCO frequency and 80MHz system clock frequency.	csantifort	5029d 08h	/amber/trunk/hw/vlog/
42	Added write buffer - fixes bug if wishbone writes takes multiple cycles to complete	csantifort	5047d 05h	/amber/trunk/hw/vlog/
41	Added instructions on how to use Coregen to create the Spartan-6 DDR3 memory interface.	csantifort	5048d 13h	/amber/trunk/hw/vlog/
40	Added wishbone bus jitter testing option. Cleaned up waveform log .do files, now seperate files for a23 and a25 cores. Added vmlinux executable elf file for running on hardware.	csantifort	5053d 05h	/amber/trunk/hw/vlog/
39	Added a second level of buffering to a25_wishbone_buf to fix a lockup bug when write acks to not return immediately, and also to improve performance slightly	csantifort	5054d 06h	/amber/trunk/hw/vlog/
38	support 128-bit wishbone now used for a25 core	csantifort	5055d 06h	/amber/trunk/hw/vlog/
37	128-bit wide boot memory module	csantifort	5056d 04h	/amber/trunk/hw/vlog/
36	Changed boot_mem for the a25 system to be 128 bits wide to match the 128-bit wide wishbone bus	csantifort	5056d 05h	/amber/trunk/hw/vlog/
35	Amber25 improvements: Use 128-bit wishbone bus, instead of 32-bit to reduce cache miss fetch times Use a fast barrel shifter for shifts between 0 and 4 to improve timing Use a 2 cycle full barrel shifter for complex shifts	csantifort	5057d 13h	/amber/trunk/hw/vlog/
32	Added clock cycle counting register to test_module to support dhrystone performance measurement	csantifort	5060d 06h	/amber/trunk/hw/vlog/
30	Bug fix - a write access was sometimes dropped when it was in a sequence of writes with variable wb_ack delays	csantifort	5073d 13h	/amber/trunk/hw/vlog/

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[/] [amber/] [trunk/] [hw/] [vlog/] - Rev 61

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