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[/] [amber/] [trunk/] [hw/] [vlog/] - Rev 72

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72 5 bit "OH_USR" constant was used when 2 bit "USR" should be used.
Both of the constants are 0.
The fault was introduced by ram-based register bank commit.
Contributed by: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>		 csantifort 4383d 11h /amber/trunk/hw/vlog/
71 Original Amber 23 core uses asyncronous implementation of register bank.
It leads to some problems with ram-based implementation of the register bank,
because at least Altera FPGAs uses syncronous ram blocks, so the whole address
needs to be latched.

The patch exposes non-registered versions of register select signals to the
register bank, so the bank can build address and latch it in the syncronous
ram input register.

The patch is a pre-requisite for ram-based register bank implementation on Altera FPGA.

Contributed by Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>		 csantifort 4383d 11h /amber/trunk/hw/vlog/
64 Support latest Xilinx ISE 14.5 software. csantifort 4383d 13h /amber/trunk/hw/vlog/
63 Add support for Xilinx ISim Verilog simulator.
Remove Virtex-6 files.		 csantifort 4383d 17h /amber/trunk/hw/vlog/
61 Add new netowkr based boot loader.
Remove support for Virtex. Spartan 6 only now.		 csantifort 4670d 12h /amber/trunk/hw/vlog/
60 Bug fix; removed a combinational loop from the a25_decode logic. csantifort 4888d 08h /amber/trunk/hw/vlog/
58 Use TB.clk_count for the decompiler messages and removed the local counter csantifort 4958d 09h /amber/trunk/hw/vlog/
57 Add some debug messages csantifort 4958d 09h /amber/trunk/hw/vlog/
54 Bug fix for bug reported by Botao Lee. The mode bits in the decode stage did not change immediately
after a mode switch from a teqp instruction, but 1 cycle later. This meant the wrong set of registers
was selected for writing to for 1 clock cycle.		 csantifort 4975d 09h /amber/trunk/hw/vlog/
53 Cleaned up Amber Verilog, removing unused signals. csantifort 4990d 07h /amber/trunk/hw/vlog/
52 Fixed typo in notes on creating DDR memory interfaces using coregen csantifort 4990d 07h /amber/trunk/hw/vlog/
49 Added a note n how to change timeouts csantifort 5031d 07h /amber/trunk/hw/vlog/
47 Changed V6 VCo from 1000Mhz to 1200 MHz csantifort 5055d 10h /amber/trunk/hw/vlog/
43 Added support for the flat executable file format to vmlinux, so that the hello-world program is correctly relocated when it is loaded at the end of the vmlinux test.
Changed the Virtex-5 clock configuration to use a 1200MHz VCO frequency and 80MHz system clock frequency.		 csantifort 5063d 09h /amber/trunk/hw/vlog/
42 Added write buffer - fixes bug if wishbone writes takes multiple cycles to complete csantifort 5081d 05h /amber/trunk/hw/vlog/
41 Added instructions on how to use Coregen to create the Spartan-6 DDR3 memory interface. csantifort 5082d 14h /amber/trunk/hw/vlog/
40 Added wishbone bus jitter testing option.
Cleaned up waveform log .do files, now seperate files for a23 and a25 cores.
Added vmlinux executable elf file for running on hardware.		 csantifort 5087d 06h /amber/trunk/hw/vlog/
39 Added a second level of buffering to a25_wishbone_buf to fix a lockup
bug when write acks to not return immediately, and also to improve performance slightly		 csantifort 5088d 07h /amber/trunk/hw/vlog/
38 support 128-bit wishbone now used for a25 core csantifort 5089d 07h /amber/trunk/hw/vlog/
37 128-bit wide boot memory module csantifort 5090d 05h /amber/trunk/hw/vlog/

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