URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] [vlog/] - Rev 89

Rev	Log message	Author	Age	Path
52	Fixed typo in notes on creating DDR memory interfaces using coregen	csantifort	4953d 03h	/amber/trunk/hw/vlog/
49	Added a note n how to change timeouts	csantifort	4994d 03h	/amber/trunk/hw/vlog/
47	Changed V6 VCo from 1000Mhz to 1200 MHz	csantifort	5018d 07h	/amber/trunk/hw/vlog/
43	Added support for the flat executable file format to vmlinux, so that the hello-world program is correctly relocated when it is loaded at the end of the vmlinux test. Changed the Virtex-5 clock configuration to use a 1200MHz VCO frequency and 80MHz system clock frequency.	csantifort	5026d 05h	/amber/trunk/hw/vlog/
42	Added write buffer - fixes bug if wishbone writes takes multiple cycles to complete	csantifort	5044d 02h	/amber/trunk/hw/vlog/
41	Added instructions on how to use Coregen to create the Spartan-6 DDR3 memory interface.	csantifort	5045d 10h	/amber/trunk/hw/vlog/
40	Added wishbone bus jitter testing option. Cleaned up waveform log .do files, now seperate files for a23 and a25 cores. Added vmlinux executable elf file for running on hardware.	csantifort	5050d 03h	/amber/trunk/hw/vlog/
39	Added a second level of buffering to a25_wishbone_buf to fix a lockup bug when write acks to not return immediately, and also to improve performance slightly	csantifort	5051d 03h	/amber/trunk/hw/vlog/
38	support 128-bit wishbone now used for a25 core	csantifort	5052d 03h	/amber/trunk/hw/vlog/
37	128-bit wide boot memory module	csantifort	5053d 02h	/amber/trunk/hw/vlog/