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[/] [amber/] [trunk/] [hw/] [vlog/] [amber23/] - Rev 71

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71 Original Amber 23 core uses asyncronous implementation of register bank.
It leads to some problems with ram-based implementation of the register bank,
because at least Altera FPGAs uses syncronous ram blocks, so the whole address
needs to be latched.

The patch exposes non-registered versions of register select signals to the
register bank, so the bank can build address and latch it in the syncronous
ram input register.

The patch is a pre-requisite for ram-based register bank implementation on Altera FPGA.

Contributed by Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>		 csantifort 4284d 05h /amber/trunk/hw/vlog/amber23/
63 Add support for Xilinx ISim Verilog simulator.
Remove Virtex-6 files.		 csantifort 4284d 11h /amber/trunk/hw/vlog/amber23/
58 Use TB.clk_count for the decompiler messages and removed the local counter csantifort 4859d 02h /amber/trunk/hw/vlog/amber23/
54 Bug fix for bug reported by Botao Lee. The mode bits in the decode stage did not change immediately
after a mode switch from a teqp instruction, but 1 cycle later. This meant the wrong set of registers
was selected for writing to for 1 clock cycle.		 csantifort 4876d 02h /amber/trunk/hw/vlog/amber23/
53 Cleaned up Amber Verilog, removing unused signals. csantifort 4891d 00h /amber/trunk/hw/vlog/amber23/
43 Added support for the flat executable file format to vmlinux, so that the hello-world program is correctly relocated when it is loaded at the end of the vmlinux test.
Changed the Virtex-5 clock configuration to use a 1200MHz VCO frequency and 80MHz system clock frequency.		 csantifort 4964d 02h /amber/trunk/hw/vlog/amber23/
42 Added write buffer - fixes bug if wishbone writes takes multiple cycles to complete csantifort 4981d 22h /amber/trunk/hw/vlog/amber23/
15 Copied amber to amber23, Many system changes to support new amber25 core. csantifort 5083d 18h /amber/trunk/hw/vlog/amber23/
2 Baseline release of the Amber 2 core csantifort 5114d 04h /amber/trunk/hw/vlog/amber/

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