OpenCores
URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] [vlog/] [amber23/] [a23_decode.v] - Rev 87

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
87 Added support for "When an Operand2 constant is used with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to bit[31] of the constant, if the constant is greater than 255 and can be produced by shifting an 8-bit value" to amber23 csantifort 3527d 20h /amber/trunk/hw/vlog/amber23/a23_decode.v
83 Fixed bug with carry bit - now only use the carry bit as an input to specific instruments that use it - add with carry and subtract with carry csantifort 3540d 23h /amber/trunk/hw/vlog/amber23/a23_decode.v
82 Fixed overflag bug, ldmia user regs bug and status_bits_mode set on non-ececuting command bug csantifort 3554d 11h /amber/trunk/hw/vlog/amber23/a23_decode.v
71 Original Amber 23 core uses asyncronous implementation of register bank.
It leads to some problems with ram-based implementation of the register bank,
because at least Altera FPGAs uses syncronous ram blocks, so the whole address
needs to be latched.

The patch exposes non-registered versions of register select signals to the
register bank, so the bank can build address and latch it in the syncronous
ram input register.

The patch is a pre-requisite for ram-based register bank implementation on Altera FPGA.

Contributed by Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>
csantifort 4240d 18h /amber/trunk/hw/vlog/amber23/a23_decode.v
63 Add support for Xilinx ISim Verilog simulator.
Remove Virtex-6 files.
csantifort 4241d 00h /amber/trunk/hw/vlog/amber23/a23_decode.v
15 Copied amber to amber23, Many system changes to support new amber25 core. csantifort 5040d 07h /amber/trunk/hw/vlog/amber23/a23_decode.v
2 Baseline release of the Amber 2 core csantifort 5070d 18h /amber/trunk/hw/vlog/amber/a23_decode.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.