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[/] [amber/] [trunk/] [hw/] [vlog/] [amber23/] [a23_execute.v] - Rev 89

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89 CHange registered outputs with non-zero initial values to wires with an internal register.
This works around an issue with Altera (Quartus) synthesis where any port registers are given an initial vale of zero.
csantifort 3336d 01h /amber/trunk/hw/vlog/amber23/a23_execute.v
88 Added the carry in fix added recently to the a23 core to a25 core. csantifort 3336d 02h /amber/trunk/hw/vlog/amber23/a23_execute.v
87 Added support for "When an Operand2 constant is used with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to bit[31] of the constant, if the constant is greater than 255 and can be produced by shifting an 8-bit value" to amber23 csantifort 3336d 06h /amber/trunk/hw/vlog/amber23/a23_execute.v
83 Fixed bug with carry bit - now only use the carry bit as an input to specific instruments that use it - add with carry and subtract with carry csantifort 3349d 09h /amber/trunk/hw/vlog/amber23/a23_execute.v
82 Fixed overflag bug, ldmia user regs bug and status_bits_mode set on non-ececuting command bug csantifort 3362d 21h /amber/trunk/hw/vlog/amber23/a23_execute.v
74 The patch implements barrel shifter using rotate as a main primitive.
The design was optimized for Altera Cyclone III FPGA and can be reused
with other FPGA vendors and products.
The patch integrates the FPGA-optimized barrel shifter into the
Amber 23 core when it is build for Altera FPGA.

The patch reduces footprint from 1178 to 339 LEs keeping Fmax at 57-60 MHz.

Contributed by: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>
csantifort 4049d 03h /amber/trunk/hw/vlog/amber23/a23_execute.v
73 The patch introduces a new configuration option `A23_RAM_REGISTER_BANK,
which controls instantiation of Amber 23 register bank.
If the option is set, a ram-based variant of the register bank is instantiated.
It can be useful in low-end FPGA designs, where flipflops and muxes are costly.

Altera Cyclone III resource utilization:
- flipflop-based register bank: 1583 combinationals + 856 registers
- ram-based register bank: 268 combinationals + 156 registers

Contributed by Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>
csantifort 4049d 04h /amber/trunk/hw/vlog/amber23/a23_execute.v
72 5 bit "OH_USR" constant was used when 2 bit "USR" should be used.
Both of the constants are 0.
The fault was introduced by ram-based register bank commit.
Contributed by: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>
csantifort 4049d 04h /amber/trunk/hw/vlog/amber23/a23_execute.v
71 Original Amber 23 core uses asyncronous implementation of register bank.
It leads to some problems with ram-based implementation of the register bank,
because at least Altera FPGAs uses syncronous ram blocks, so the whole address
needs to be latched.

The patch exposes non-registered versions of register select signals to the
register bank, so the bank can build address and latch it in the syncronous
ram input register.

The patch is a pre-requisite for ram-based register bank implementation on Altera FPGA.

Contributed by Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>
csantifort 4049d 04h /amber/trunk/hw/vlog/amber23/a23_execute.v
54 Bug fix for bug reported by Botao Lee. The mode bits in the decode stage did not change immediately
after a mode switch from a teqp instruction, but 1 cycle later. This meant the wrong set of registers
was selected for writing to for 1 clock cycle.
csantifort 4641d 01h /amber/trunk/hw/vlog/amber23/a23_execute.v
15 Copied amber to amber23, Many system changes to support new amber25 core. csantifort 4848d 18h /amber/trunk/hw/vlog/amber23/a23_execute.v
2 Baseline release of the Amber 2 core csantifort 4879d 04h /amber/trunk/hw/vlog/amber/a23_execute.v

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