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[/] [amber/] [trunk/] [hw/] [vlog/] [amber25/] [a25_execute.v] - Rev 88

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88 Added the carry in fix added recently to the a23 core to a25 core. csantifort 3392d 19h /amber/trunk/hw/vlog/amber25/a25_execute.v
86 Fixed bug in amber 25 where a read was taken from user mode register in subervisor mode immediately following a ldm to user mode registers csantifort 3405d 19h /amber/trunk/hw/vlog/amber25/a25_execute.v
83 Fixed bug with carry bit - now only use the carry bit as an input to specific instruments that use it - add with carry and subtract with carry csantifort 3406d 02h /amber/trunk/hw/vlog/amber25/a25_execute.v
82 Fixed overflag bug, ldmia user regs bug and status_bits_mode set on non-ececuting command bug csantifort 3419d 14h /amber/trunk/hw/vlog/amber25/a25_execute.v
54 Bug fix for bug reported by Botao Lee. The mode bits in the decode stage did not change immediately
after a mode switch from a teqp instruction, but 1 cycle later. This meant the wrong set of registers
was selected for writing to for 1 clock cycle.
csantifort 4697d 18h /amber/trunk/hw/vlog/amber25/a25_execute.v
53 Cleaned up Amber Verilog, removing unused signals. csantifort 4712d 16h /amber/trunk/hw/vlog/amber25/a25_execute.v
35 Amber25 improvements:
Use 128-bit wishbone bus, instead of 32-bit to reduce cache miss fetch times
Use a fast barrel shifter for shifts between 0 and 4 to improve timing
Use a 2 cycle full barrel shifter for complex shifts
csantifort 4813d 22h /amber/trunk/hw/vlog/amber25/a25_execute.v
20 Added feature to A25 core to directly use a read value from the write back stage
to reduce the stall to 1 cycle when there is a register conflict with the
following instruction. This increases performance by about 3%.
csantifort 4898d 22h /amber/trunk/hw/vlog/amber25/a25_execute.v
16 Deleted the old version of the 3-state amber core. Its replaced with amber23.
Added the 5-state Amber core.
csantifort 4905d 10h /amber/trunk/hw/vlog/amber25/a25_execute.v

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