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[/] [amber/] [trunk/] [hw/] [vlog/] [amber25/] [a25_wishbone.v] - Rev 35

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Rev Log message Author Age Path
35 Amber25 improvements:
Use 128-bit wishbone bus, instead of 32-bit to reduce cache miss fetch times
Use a fast barrel shifter for shifts between 0 and 4 to improve timing
Use a 2 cycle full barrel shifter for complex shifts
csantifort 4956d 04h /amber/trunk/hw/vlog/amber25/a25_wishbone.v
30 Bug fix - a write access was sometimes dropped when it was in a sequence of writes with variable wb_ack delays csantifort 4972d 04h /amber/trunk/hw/vlog/amber25/a25_wishbone.v
17 amber25 core bug fix. The return address for irq interrupts was off by 4 bytes
when the interrupt occurred during a stm instruction with the following instruction
having some register conflicts. Added test irq_stm to catch the bug.
Cleaned up some header descriptions
csantifort 5045d 01h /amber/trunk/hw/vlog/amber25/a25_wishbone.v
16 Deleted the old version of the 3-state amber core. Its replaced with amber23.
Added the 5-state Amber core.
csantifort 5047d 16h /amber/trunk/hw/vlog/amber25/a25_wishbone.v

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