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[/] [amber/] [trunk/] [hw/] [vlog/] [system/] - Rev 64

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Rev Log message Author Age Path
64 Support latest Xilinx ISE 14.5 software. csantifort 4311d 14h /amber/trunk/hw/vlog/system/
63 Add support for Xilinx ISim Verilog simulator.
Remove Virtex-6 files.
csantifort 4311d 18h /amber/trunk/hw/vlog/system/
61 Add new netowkr based boot loader.
Remove support for Virtex. Spartan 6 only now.
csantifort 4598d 13h /amber/trunk/hw/vlog/system/
57 Add some debug messages csantifort 4886d 10h /amber/trunk/hw/vlog/system/
47 Changed V6 VCo from 1000Mhz to 1200 MHz csantifort 4983d 11h /amber/trunk/hw/vlog/system/
43 Added support for the flat executable file format to vmlinux, so that the hello-world program is correctly relocated when it is loaded at the end of the vmlinux test.
Changed the Virtex-5 clock configuration to use a 1200MHz VCO frequency and 80MHz system clock frequency.
csantifort 4991d 09h /amber/trunk/hw/vlog/system/
40 Added wishbone bus jitter testing option.
Cleaned up waveform log .do files, now seperate files for a23 and a25 cores.
Added vmlinux executable elf file for running on hardware.
csantifort 5015d 07h /amber/trunk/hw/vlog/system/
38 support 128-bit wishbone now used for a25 core csantifort 5017d 08h /amber/trunk/hw/vlog/system/
36 Changed boot_mem for the a25 system to be 128 bits wide to match the 128-bit wide wishbone bus csantifort 5018d 07h /amber/trunk/hw/vlog/system/
35 Amber25 improvements:
Use 128-bit wishbone bus, instead of 32-bit to reduce cache miss fetch times
Use a fast barrel shifter for shifts between 0 and 4 to improve timing
Use a 2 cycle full barrel shifter for complex shifts
csantifort 5019d 14h /amber/trunk/hw/vlog/system/
32 Added clock cycle counting register to test_module to support dhrystone performance measurement csantifort 5022d 07h /amber/trunk/hw/vlog/system/
27 Got working with cadence nc simulator csantifort 5070d 15h /amber/trunk/hw/vlog/system/
17 amber25 core bug fix. The return address for irq interrupts was off by 4 bytes
when the interrupt occurred during a stm instruction with the following instruction
having some register conflicts. Added test irq_stm to catch the bug.
Cleaned up some header descriptions
csantifort 5108d 12h /amber/trunk/hw/vlog/system/
15 Copied amber to amber23, Many system changes to support new amber25 core. csantifort 5111d 02h /amber/trunk/hw/vlog/system/
14 Re-wrote the behavioral clock generation code to more accurately
calculate the sys_clk frequency. The previous version was not
producing the correct frequency at higher frequenies due to
rounding errors.
csantifort 5112d 14h /amber/trunk/hw/vlog/system/
13 Bug fix - added an extra state to the rx state machine to properly align
reading the uart input to the middle of each bit.
csantifort 5112d 14h /amber/trunk/hw/vlog/system/
11 Added vmlinux test. csantifort 5127d 14h /amber/trunk/hw/vlog/system/
10 Removed parameters for unused peruipheral modules csantifort 5128d 18h /amber/trunk/hw/vlog/system/
7 Added instructions to use Veritak simulator.
Removed some unused functions from memory_configuration.v.
csantifort 5137d 08h /amber/trunk/hw/vlog/system/
2 Baseline release of the Amber 2 core csantifort 5141d 12h /amber/trunk/hw/vlog/system/

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