OpenCores
URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] [vlog/] [system/] [uart.v] - Rev 82

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
82 Fixed overflag bug, ldmia user regs bug and status_bits_mode set on non-ececuting command bug csantifort 3557d 21h /amber/trunk/hw/vlog/system/uart.v
63 Add support for Xilinx ISim Verilog simulator.
Remove Virtex-6 files.
csantifort 4244d 10h /amber/trunk/hw/vlog/system/uart.v
47 Changed V6 VCo from 1000Mhz to 1200 MHz csantifort 4916d 03h /amber/trunk/hw/vlog/system/uart.v
35 Amber25 improvements:
Use 128-bit wishbone bus, instead of 32-bit to reduce cache miss fetch times
Use a fast barrel shifter for shifts between 0 and 4 to improve timing
Use a 2 cycle full barrel shifter for complex shifts
csantifort 4952d 06h /amber/trunk/hw/vlog/system/uart.v
27 Got working with cadence nc simulator csantifort 5003d 07h /amber/trunk/hw/vlog/system/uart.v
13 Bug fix - added an extra state to the rx state machine to properly align
reading the uart input to the middle of each bit.
csantifort 5045d 06h /amber/trunk/hw/vlog/system/uart.v
2 Baseline release of the Amber 2 core csantifort 5074d 04h /amber/trunk/hw/vlog/system/uart.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.