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[/] [amber/] [trunk/] [hw/] [vlog/] [system/] [wb_xs6_ddr3_bridge.v] - Rev 63

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63 Add support for Xilinx ISim Verilog simulator.
Remove Virtex-6 files.
csantifort 4242d 12h /amber/trunk/hw/vlog/system/wb_xs6_ddr3_bridge.v
36 Changed boot_mem for the a25 system to be 128 bits wide to match the 128-bit wide wishbone bus csantifort 4949d 01h /amber/trunk/hw/vlog/system/wb_xs6_ddr3_bridge.v
15 Copied amber to amber23, Many system changes to support new amber25 core. csantifort 5041d 20h /amber/trunk/hw/vlog/system/wb_xs6_ddr3_bridge.v
11 Added vmlinux test. csantifort 5058d 08h /amber/trunk/hw/vlog/system/wb_xs6_ddr3_bridge.v
2 Baseline release of the Amber 2 core csantifort 5072d 06h /amber/trunk/hw/vlog/system/wb_xs6_ddr3_bridge.v

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