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[/] [amber/] [trunk/] [hw/] [vlog] - Rev 89

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89 CHange registered outputs with non-zero initial values to wires with an internal register.
This works around an issue with Altera (Quartus) synthesis where any port registers are given an initial vale of zero.
csantifort 3523d 20h /amber/trunk/hw/vlog
88 Added the carry in fix added recently to the a23 core to a25 core. csantifort 3523d 21h /amber/trunk/hw/vlog
87 Added support for "When an Operand2 constant is used with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to bit[31] of the constant, if the constant is greater than 255 and can be produced by shifting an 8-bit value" to amber23 csantifort 3524d 00h /amber/trunk/hw/vlog
86 Fixed bug in amber 25 where a read was taken from user mode register in subervisor mode immediately following a ldm to user mode registers csantifort 3536d 21h /amber/trunk/hw/vlog
84 Fixed some typos - no functional change csantifort 3537d 04h /amber/trunk/hw/vlog
83 Fixed bug with carry bit - now only use the carry bit as an input to specific instruments that use it - add with carry and subtract with carry csantifort 3537d 04h /amber/trunk/hw/vlog
82 Fixed overflag bug, ldmia user regs bug and status_bits_mode set on non-ececuting command bug csantifort 3550d 16h /amber/trunk/hw/vlog
78 Added a serial debug port (using UART0) to boot-loader-ethmac csantifort 4229d 03h /amber/trunk/hw/vlog
74 The patch implements barrel shifter using rotate as a main primitive.
The design was optimized for Altera Cyclone III FPGA and can be reused
with other FPGA vendors and products.
The patch integrates the FPGA-optimized barrel shifter into the
Amber 23 core when it is build for Altera FPGA.

The patch reduces footprint from 1178 to 339 LEs keeping Fmax at 57-60 MHz.

Contributed by: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>
csantifort 4236d 22h /amber/trunk/hw/vlog
73 The patch introduces a new configuration option `A23_RAM_REGISTER_BANK,
which controls instantiation of Amber 23 register bank.
If the option is set, a ram-based variant of the register bank is instantiated.
It can be useful in low-end FPGA designs, where flipflops and muxes are costly.

Altera Cyclone III resource utilization:
- flipflop-based register bank: 1583 combinationals + 856 registers
- ram-based register bank: 268 combinationals + 156 registers

Contributed by Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>
csantifort 4236d 22h /amber/trunk/hw/vlog
72 5 bit "OH_USR" constant was used when 2 bit "USR" should be used.
Both of the constants are 0.
The fault was introduced by ram-based register bank commit.
Contributed by: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>
csantifort 4236d 22h /amber/trunk/hw/vlog
71 Original Amber 23 core uses asyncronous implementation of register bank.
It leads to some problems with ram-based implementation of the register bank,
because at least Altera FPGAs uses syncronous ram blocks, so the whole address
needs to be latched.

The patch exposes non-registered versions of register select signals to the
register bank, so the bank can build address and latch it in the syncronous
ram input register.

The patch is a pre-requisite for ram-based register bank implementation on Altera FPGA.

Contributed by Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>
csantifort 4236d 22h /amber/trunk/hw/vlog
64 Support latest Xilinx ISE 14.5 software. csantifort 4237d 00h /amber/trunk/hw/vlog
63 Add support for Xilinx ISim Verilog simulator.
Remove Virtex-6 files.
csantifort 4237d 04h /amber/trunk/hw/vlog
61 Add new netowkr based boot loader.
Remove support for Virtex. Spartan 6 only now.
csantifort 4523d 23h /amber/trunk/hw/vlog
60 Bug fix; removed a combinational loop from the a25_decode logic. csantifort 4741d 19h /amber/trunk/hw/vlog
58 Use TB.clk_count for the decompiler messages and removed the local counter csantifort 4811d 20h /amber/trunk/hw/vlog
57 Add some debug messages csantifort 4811d 20h /amber/trunk/hw/vlog
54 Bug fix for bug reported by Botao Lee. The mode bits in the decode stage did not change immediately
after a mode switch from a teqp instruction, but 1 cycle later. This meant the wrong set of registers
was selected for writing to for 1 clock cycle.
csantifort 4828d 20h /amber/trunk/hw/vlog
53 Cleaned up Amber Verilog, removing unused signals. csantifort 4843d 17h /amber/trunk/hw/vlog
52 Fixed typo in notes on creating DDR memory interfaces using coregen csantifort 4843d 17h /amber/trunk/hw/vlog
49 Added a note n how to change timeouts csantifort 4884d 17h /amber/trunk/hw/vlog
47 Changed V6 VCo from 1000Mhz to 1200 MHz csantifort 4908d 21h /amber/trunk/hw/vlog
43 Added support for the flat executable file format to vmlinux, so that the hello-world program is correctly relocated when it is loaded at the end of the vmlinux test.
Changed the Virtex-5 clock configuration to use a 1200MHz VCO frequency and 80MHz system clock frequency.
csantifort 4916d 20h /amber/trunk/hw/vlog
42 Added write buffer - fixes bug if wishbone writes takes multiple cycles to complete csantifort 4934d 16h /amber/trunk/hw/vlog
41 Added instructions on how to use Coregen to create the Spartan-6 DDR3 memory interface. csantifort 4936d 01h /amber/trunk/hw/vlog
40 Added wishbone bus jitter testing option.
Cleaned up waveform log .do files, now seperate files for a23 and a25 cores.
Added vmlinux executable elf file for running on hardware.
csantifort 4940d 17h /amber/trunk/hw/vlog
39 Added a second level of buffering to a25_wishbone_buf to fix a lockup
bug when write acks to not return immediately, and also to improve performance slightly
csantifort 4941d 18h /amber/trunk/hw/vlog
38 support 128-bit wishbone now used for a25 core csantifort 4942d 18h /amber/trunk/hw/vlog
37 128-bit wide boot memory module csantifort 4943d 16h /amber/trunk/hw/vlog

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