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Rev Log message Author Age Path
54 Bug fix for bug reported by Botao Lee. The mode bits in the decode stage did not change immediately
after a mode switch from a teqp instruction, but 1 cycle later. This meant the wrong set of registers
was selected for writing to for 1 clock cycle.		 csantifort 4966d 23h /
53 Cleaned up Amber Verilog, removing unused signals. csantifort 4981d 21h /
52 Fixed typo in notes on creating DDR memory interfaces using coregen csantifort 4981d 21h /
51 Revert vmlinux back to 48. csantifort 5022d 21h /
50 Revert to previous version csantifort 5022d 21h /
49 Added a note n how to change timeouts csantifort 5022d 21h /
48 Fixed a bug in linux that caused the os to not return to the running application after an interrupt.
Hello-world now runs stand-alone again.
Added initrd-200k-dhry, a disk image that uses the dhry program for init.		 csantifort 5027d 04h /
47 Changed V6 VCo from 1000Mhz to 1200 MHz csantifort 5047d 01h /
46 svn ignore vmlinux.dis and vmlinux.mem csantifort 5054d 23h /
45 Store vmlinux.mem and vmlinux.dis in compressed form csantifort 5054d 23h /
44 Updated vmlinux image based on last change csantifort 5054d 23h /
43 Added support for the flat executable file format to vmlinux, so that the hello-world program is correctly relocated when it is loaded at the end of the vmlinux test.
Changed the Virtex-5 clock configuration to use a 1200MHz VCO frequency and 80MHz system clock frequency.		 csantifort 5055d 00h /
42 Added write buffer - fixes bug if wishbone writes takes multiple cycles to complete csantifort 5072d 20h /
41 Added instructions on how to use Coregen to create the Spartan-6 DDR3 memory interface. csantifort 5074d 05h /
40 Added wishbone bus jitter testing option.
Cleaned up waveform log .do files, now seperate files for a23 and a25 cores.
Added vmlinux executable elf file for running on hardware.		 csantifort 5078d 21h /
39 Added a second level of buffering to a25_wishbone_buf to fix a lockup
bug when write acks to not return immediately, and also to improve performance slightly		 csantifort 5079d 22h /
38 support 128-bit wishbone now used for a25 core csantifort 5080d 22h /
37 128-bit wide boot memory module csantifort 5081d 20h /
36 Changed boot_mem for the a25 system to be 128 bits wide to match the 128-bit wide wishbone bus csantifort 5081d 21h /
35 Amber25 improvements:
Use 128-bit wishbone bus, instead of 32-bit to reduce cache miss fetch times
Use a fast barrel shifter for shifts between 0 and 4 to improve timing
Use a 2 cycle full barrel shifter for complex shifts		 csantifort 5083d 04h /
34 Tweaked strcpy function to speed it up slightly csantifort 5084d 01h /
33 Fixed bug in div assembly function. Handles negative numbers correctly.
Fixed bug in printf function, negative numbers now print correctly.		 csantifort 5084d 21h /
32 Added clock cycle counting register to test_module to support dhrystone performance measurement csantifort 5085d 21h /
31 Added dhrystone benchmark test csantifort 5085d 22h /
30 Bug fix - a write access was sometimes dropped when it was in a sequence of writes with variable wb_ack delays csantifort 5099d 04h /
29 Use lgo command for saving waveforms in modelsim csantifort 5100d 22h /
28 Moved function prototypes to .h file csantifort 5100d 22h /
27 Got working with cadence nc simulator csantifort 5134d 05h /
26 Added wish list csantifort 5139d 05h /
25 Bug fix: boot-loader.mem became larger that the allowed 8k byte boot mem size.
Removed a struct in elfsplitter.c thats only used for debug - this reduced boot-loader.mem enough so that it fits again.
Tidy up: Removed a debug message from hw/tools/run.sh		 csantifort 5141d 02h /

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