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Rev	Log message	Author	Age	Path
127	Fixing the core to be Bosch VHDL Reference compatible.	mohor	7661d 06h	/
126	Error counters fixed to be compatible with Bosch VHDL reference model. Small synchronization changes.	mohor	7662d 02h	/
125	Synchronization changed, error counters fixed.	mohor	7666d 08h	/
124	ALTERA_RAM supported.	mohor	7686d 15h	/
123	This commit was manufactured by cvs2svn to create tag 'rel_17'.		7693d 20h	/
122	This commit was manufactured by cvs2svn to create tag 'rel_16'.		7693d 20h	/
121	When detecting bus-free, signal bus_free_cnt_en was cleared to zero although the last sampled bit was zero instead of one.	mohor	7693d 20h	/
120	This commit was manufactured by cvs2svn to create tag 'rel_15'.		7702d 17h	/
119	Artisan RAMs added.	mohor	7702d 17h	/
118	Artisan RAM fixed (when not using BIST).	mohor	7702d 17h	/
117	Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need to be joined together on higher level.	mohor	7702d 17h	/
116	This commit was manufactured by cvs2svn to create tag 'rel_14'.		7708d 11h	/
115	Artisan ram instances added.	simons	7708d 11h	/
114	This commit was manufactured by cvs2svn to create tag 'rel_13'.		7735d 12h	/
113	This commit was manufactured by cvs2svn to create tag 'rel_12'.		7735d 12h	/
112	Tx and rx length are limited to 8 bytes regardless to the DLC value.	tadejm	7735d 12h	/
111	Fixed according to the linter. Case statement for data_out joined.	mohor	7737d 12h	/
110	Fixed according to the linter.	mohor	7737d 12h	/
109	Fixed according to the linter.	mohor	7737d 13h	/
108	Fixed according to the linter.	mohor	7737d 14h	/

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